clk/samsung/clk-s3c2443.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
0004  *
0005  * Common Clock Framework support for S3C2443 and following SoCs.
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/clk/samsung.h>
0010 #include <linux/io.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013 #include <linux/reboot.h>
0014
0015 #include <dt-bindings/clock/s3c2443.h>
0016
0017 #include "clk.h"
0018 #include "clk-pll.h"
0019
0020 /* S3C2416 clock controller register offsets */
0021 #define LOCKCON0    0x00
0022 #define LOCKCON1    0x04
0023 #define MPLLCON     0x10
0024 #define EPLLCON     0x18
0025 #define EPLLCON_K   0x1C
0026 #define CLKSRC      0x20
0027 #define CLKDIV0     0x24
0028 #define CLKDIV1     0x28
0029 #define CLKDIV2     0x2C
0030 #define HCLKCON     0x30
0031 #define PCLKCON     0x34
0032 #define SCLKCON     0x38
0033 #define SWRST       0x44
0034
0035 /* the soc types */
0036 enum supported_socs {
0037     S3C2416,
0038     S3C2443,
0039     S3C2450,
0040 };
0041
0042 static void __iomem *reg_base;
0043
0044 /*
0045  * list of controller registers to be saved and restored during a
0046  * suspend/resume cycle.
0047  */
0048 static unsigned long s3c2443_clk_regs[] __initdata = {
0049     LOCKCON0,
0050     LOCKCON1,
0051     MPLLCON,
0052     EPLLCON,
0053     EPLLCON_K,
0054     CLKSRC,
0055     CLKDIV0,
0056     CLKDIV1,
0057     CLKDIV2,
0058     PCLKCON,
0059     HCLKCON,
0060     SCLKCON,
0061 };
0062
0063 PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" };
0064 PNAME(esysclk_p) = { "epllref", "epll" };
0065 PNAME(mpllref_p) = { "xti", "mdivclk" };
0066 PNAME(msysclk_p) = { "mpllref", "mpll" };
0067 PNAME(armclk_p) = { "armdiv" , "hclk" };
0068 PNAME(i2s0_p) = { "div_i2s0", "ext_i2s", "epllref", "epllref" };
0069
0070 static struct samsung_mux_clock s3c2443_common_muxes[] __initdata = {
0071     MUX(0, "epllref", epllref_p, CLKSRC, 7, 2),
0072     MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1),
0073     MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1),
0074     MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
0075     MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1),
0076     MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2),
0077 };
0078
0079 static struct clk_div_table hclk_d[] = {
0080     { .val = 0, .div = 1 },
0081     { .val = 1, .div = 2 },
0082     { .val = 3, .div = 4 },
0083     { /* sentinel */ },
0084 };
0085
0086 static struct clk_div_table mdivclk_d[] = {
0087     { .val = 0, .div = 1 },
0088     { .val = 1, .div = 3 },
0089     { .val = 2, .div = 5 },
0090     { .val = 3, .div = 7 },
0091     { .val = 4, .div = 9 },
0092     { .val = 5, .div = 11 },
0093     { .val = 6, .div = 13 },
0094     { .val = 7, .div = 15 },
0095     { /* sentinel */ },
0096 };
0097
0098 static struct samsung_div_clock s3c2443_common_dividers[] __initdata = {
0099     DIV_T(0, "mdivclk", "xti", CLKDIV0, 6, 3, mdivclk_d),
0100     DIV(0, "prediv", "msysclk", CLKDIV0, 4, 2),
0101     DIV_T(HCLK, "hclk", "prediv", CLKDIV0, 0, 2, hclk_d),
0102     DIV(PCLK, "pclk", "hclk", CLKDIV0, 2, 1),
0103     DIV(0, "div_hsspi0_epll", "esysclk", CLKDIV1, 24, 2),
0104     DIV(0, "div_fimd", "esysclk", CLKDIV1, 16, 8),
0105     DIV(0, "div_i2s0", "esysclk", CLKDIV1, 12, 4),
0106     DIV(0, "div_uart", "esysclk", CLKDIV1, 8, 4),
0107     DIV(0, "div_hsmmc1", "esysclk", CLKDIV1, 6, 2),
0108     DIV(0, "div_usbhost", "esysclk", CLKDIV1, 4, 2),
0109 };
0110
0111 static struct samsung_gate_clock s3c2443_common_gates[] __initdata = {
0112     GATE(SCLK_HSMMC_EXT, "sclk_hsmmcext", "ext", SCLKCON, 13, 0, 0),
0113     GATE(SCLK_HSMMC1, "sclk_hsmmc1", "div_hsmmc1", SCLKCON, 12, 0, 0),
0114     GATE(SCLK_FIMD, "sclk_fimd", "div_fimd", SCLKCON, 10, 0, 0),
0115     GATE(SCLK_I2S0, "sclk_i2s0", "mux_i2s0", SCLKCON, 9, 0, 0),
0116     GATE(SCLK_UART, "sclk_uart", "div_uart", SCLKCON, 8, 0, 0),
0117     GATE(SCLK_USBH, "sclk_usbhost", "div_usbhost", SCLKCON, 1, 0, 0),
0118     GATE(HCLK_DRAM, "dram", "hclk", HCLKCON, 19, CLK_IGNORE_UNUSED, 0),
0119     GATE(HCLK_SSMC, "ssmc", "hclk", HCLKCON, 18, CLK_IGNORE_UNUSED, 0),
0120     GATE(HCLK_HSMMC1, "hsmmc1", "hclk", HCLKCON, 16, 0, 0),
0121     GATE(HCLK_USBD, "usb-device", "hclk", HCLKCON, 12, 0, 0),
0122     GATE(HCLK_USBH, "usb-host", "hclk", HCLKCON, 11, 0, 0),
0123     GATE(HCLK_LCD, "lcd", "hclk", HCLKCON, 9, 0, 0),
0124     GATE(HCLK_DMA5, "dma5", "hclk", HCLKCON, 5, CLK_IGNORE_UNUSED, 0),
0125     GATE(HCLK_DMA4, "dma4", "hclk", HCLKCON, 4, CLK_IGNORE_UNUSED, 0),
0126     GATE(HCLK_DMA3, "dma3", "hclk", HCLKCON, 3, CLK_IGNORE_UNUSED, 0),
0127     GATE(HCLK_DMA2, "dma2", "hclk", HCLKCON, 2, CLK_IGNORE_UNUSED, 0),
0128     GATE(HCLK_DMA1, "dma1", "hclk", HCLKCON, 1, CLK_IGNORE_UNUSED, 0),
0129     GATE(HCLK_DMA0, "dma0", "hclk", HCLKCON, 0, CLK_IGNORE_UNUSED, 0),
0130     GATE(PCLK_GPIO, "gpio", "pclk", PCLKCON, 13, CLK_IGNORE_UNUSED, 0),
0131     GATE(PCLK_RTC, "rtc", "pclk", PCLKCON, 12, 0, 0),
0132     GATE(PCLK_WDT, "wdt", "pclk", PCLKCON, 11, 0, 0),
0133     GATE(PCLK_PWM, "pwm", "pclk", PCLKCON, 10, 0, 0),
0134     GATE(PCLK_I2S0, "i2s0", "pclk", PCLKCON, 9, 0, 0),
0135     GATE(PCLK_AC97, "ac97", "pclk", PCLKCON, 8, 0, 0),
0136     GATE(PCLK_ADC, "adc", "pclk", PCLKCON, 7, 0, 0),
0137     GATE(PCLK_SPI0, "spi0", "pclk", PCLKCON, 6, 0, 0),
0138     GATE(PCLK_I2C0, "i2c0", "pclk", PCLKCON, 4, 0, 0),
0139     GATE(PCLK_UART3, "uart3", "pclk", PCLKCON, 3, 0, 0),
0140     GATE(PCLK_UART2, "uart2", "pclk", PCLKCON, 2, 0, 0),
0141     GATE(PCLK_UART1, "uart1", "pclk", PCLKCON, 1, 0, 0),
0142     GATE(PCLK_UART0, "uart0", "pclk", PCLKCON, 0, 0, 0),
0143 };
0144
0145 static struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
0146     ALIAS(MSYSCLK, NULL, "msysclk"),
0147     ALIAS(ARMCLK, NULL, "armclk"),
0148     ALIAS(MPLL, NULL, "mpll"),
0149     ALIAS(EPLL, NULL, "epll"),
0150     ALIAS(HCLK, NULL, "hclk"),
0151     ALIAS(HCLK_SSMC, NULL, "nand"),
0152     ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
0153     ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
0154     ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
0155     ALIAS(PCLK_UART3, "s3c2440-uart.3", "uart"),
0156     ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
0157     ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
0158     ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
0159     ALIAS(PCLK_UART3, "s3c2440-uart.3", "clk_uart_baud2"),
0160     ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
0161     ALIAS(PCLK_PWM, NULL, "timers"),
0162     ALIAS(PCLK_RTC, NULL, "rtc"),
0163     ALIAS(PCLK_WDT, NULL, "watchdog"),
0164     ALIAS(PCLK_ADC, NULL, "adc"),
0165     ALIAS(PCLK_I2C0, "s3c2410-i2c.0", "i2c"),
0166     ALIAS(HCLK_USBD, NULL, "usb-device"),
0167     ALIAS(HCLK_USBH, NULL, "usb-host"),
0168     ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
0169     ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi"),
0170     ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi_busclk0"),
0171     ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"),
0172     ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
0173     ALIAS(PCLK_I2S0, "samsung-i2s.0", "iis"),
0174     ALIAS(SCLK_I2S0, NULL, "i2s-if"),
0175     ALIAS(HCLK_LCD, NULL, "lcd"),
0176     ALIAS(SCLK_FIMD, NULL, "sclk_fimd"),
0177 };
0178
0179 /* S3C2416 specific clocks */
0180
0181 static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = {
0182     PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
0183     PLL(pll_6553, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
0184 };
0185
0186 PNAME(s3c2416_hsmmc0_p) = { "sclk_hsmmc0", "sclk_hsmmcext" };
0187 PNAME(s3c2416_hsmmc1_p) = { "sclk_hsmmc1", "sclk_hsmmcext" };
0188 PNAME(s3c2416_hsspi0_p) = { "hsspi0_epll", "hsspi0_mpll" };
0189
0190 static struct clk_div_table armdiv_s3c2416_d[] = {
0191     { .val = 0, .div = 1 },
0192     { .val = 1, .div = 2 },
0193     { .val = 2, .div = 3 },
0194     { .val = 3, .div = 4 },
0195     { .val = 5, .div = 6 },
0196     { .val = 7, .div = 8 },
0197     { /* sentinel */ },
0198 };
0199
0200 static struct samsung_div_clock s3c2416_dividers[] __initdata = {
0201     DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 3, armdiv_s3c2416_d),
0202     DIV(0, "div_hsspi0_mpll", "msysclk", CLKDIV2, 0, 4),
0203     DIV(0, "div_hsmmc0", "esysclk", CLKDIV2, 6, 2),
0204 };
0205
0206 static struct samsung_mux_clock s3c2416_muxes[] __initdata = {
0207     MUX(MUX_HSMMC0, "mux_hsmmc0", s3c2416_hsmmc0_p, CLKSRC, 16, 1),
0208     MUX(MUX_HSMMC1, "mux_hsmmc1", s3c2416_hsmmc1_p, CLKSRC, 17, 1),
0209     MUX(MUX_HSSPI0, "mux_hsspi0", s3c2416_hsspi0_p, CLKSRC, 18, 1),
0210 };
0211
0212 static struct samsung_gate_clock s3c2416_gates[] __initdata = {
0213     GATE(0, "hsspi0_mpll", "div_hsspi0_mpll", SCLKCON, 19, 0, 0),
0214     GATE(0, "hsspi0_epll", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
0215     GATE(0, "sclk_hsmmc0", "div_hsmmc0", SCLKCON, 6, 0, 0),
0216     GATE(HCLK_2D, "2d", "hclk", HCLKCON, 20, 0, 0),
0217     GATE(HCLK_HSMMC0, "hsmmc0", "hclk", HCLKCON, 15, 0, 0),
0218     GATE(HCLK_IROM, "irom", "hclk", HCLKCON, 13, CLK_IGNORE_UNUSED, 0),
0219     GATE(PCLK_PCM, "pcm", "pclk", PCLKCON, 19, 0, 0),
0220 };
0221
0222 static struct samsung_clock_alias s3c2416_aliases[] __initdata = {
0223     ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
0224     ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
0225     ALIAS(MUX_HSMMC0, "s3c-sdhci.0", "mmc_busclk.2"),
0226     ALIAS(MUX_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"),
0227     ALIAS(MUX_HSSPI0, "s3c2443-spi.0", "spi_busclk2"),
0228     ALIAS(ARMDIV, NULL, "armdiv"),
0229 };
0230
0231 /* S3C2443 specific clocks */
0232
0233 static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = {
0234     PLL(pll_3000, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
0235     PLL(pll_2126, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
0236 };
0237
0238 static struct clk_div_table armdiv_s3c2443_d[] = {
0239     { .val = 0, .div = 1 },
0240     { .val = 8, .div = 2 },
0241     { .val = 2, .div = 3 },
0242     { .val = 9, .div = 4 },
0243     { .val = 10, .div = 6 },
0244     { .val = 11, .div = 8 },
0245     { .val = 13, .div = 12 },
0246     { .val = 15, .div = 16 },
0247     { /* sentinel */ },
0248 };
0249
0250 static struct samsung_div_clock s3c2443_dividers[] __initdata = {
0251     DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 4, armdiv_s3c2443_d),
0252     DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4),
0253 };
0254
0255 static struct samsung_gate_clock s3c2443_gates[] __initdata = {
0256     GATE(SCLK_HSSPI0, "sclk_hsspi0", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
0257     GATE(SCLK_CAM, "sclk_cam", "div_cam", SCLKCON, 11, 0, 0),
0258     GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, CLK_IGNORE_UNUSED, 0),
0259     GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
0260     GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 15, 0, 0),
0261     GATE(PCLK_SDI, "sdi", "pclk", PCLKCON, 5, 0, 0),
0262 };
0263
0264 static struct samsung_clock_alias s3c2443_aliases[] __initdata = {
0265     ALIAS(SCLK_HSSPI0, "s3c2443-spi.0", "spi_busclk2"),
0266     ALIAS(SCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"),
0267     ALIAS(SCLK_CAM, NULL, "camif-upll"),
0268     ALIAS(PCLK_SPI1, "s3c2410-spi.0", "spi"),
0269     ALIAS(PCLK_SDI, NULL, "sdi"),
0270     ALIAS(HCLK_CFC, NULL, "cfc"),
0271     ALIAS(ARMDIV, NULL, "armdiv"),
0272 };
0273
0274 /* S3C2450 specific clocks */
0275
0276 PNAME(s3c2450_cam_p) = { "div_cam", "hclk" };
0277 PNAME(s3c2450_hsspi1_p) = { "hsspi1_epll", "hsspi1_mpll" };
0278 PNAME(i2s1_p) = { "div_i2s1", "ext_i2s", "epllref", "epllref" };
0279
0280 static struct samsung_div_clock s3c2450_dividers[] __initdata = {
0281     DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4),
0282     DIV(0, "div_hsspi1_epll", "esysclk", CLKDIV2, 24, 2),
0283     DIV(0, "div_hsspi1_mpll", "msysclk", CLKDIV2, 16, 4),
0284     DIV(0, "div_i2s1", "esysclk", CLKDIV2, 12, 4),
0285 };
0286
0287 static struct samsung_mux_clock s3c2450_muxes[] __initdata = {
0288     MUX(0, "mux_cam", s3c2450_cam_p, CLKSRC, 20, 1),
0289     MUX(MUX_HSSPI1, "mux_hsspi1", s3c2450_hsspi1_p, CLKSRC, 19, 1),
0290     MUX(0, "mux_i2s1", i2s1_p, CLKSRC, 12, 2),
0291 };
0292
0293 static struct samsung_gate_clock s3c2450_gates[] __initdata = {
0294     GATE(SCLK_I2S1, "sclk_i2s1", "div_i2s1", SCLKCON, 5, 0, 0),
0295     GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, 0, 0),
0296     GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
0297     GATE(HCLK_DMA7, "dma7", "hclk", HCLKCON, 7, CLK_IGNORE_UNUSED, 0),
0298     GATE(HCLK_DMA6, "dma6", "hclk", HCLKCON, 6, CLK_IGNORE_UNUSED, 0),
0299     GATE(PCLK_I2S1, "i2s1", "pclk", PCLKCON, 17, 0, 0),
0300     GATE(PCLK_I2C1, "i2c1", "pclk", PCLKCON, 16, 0, 0),
0301     GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 14, 0, 0),
0302 };
0303
0304 static struct samsung_clock_alias s3c2450_aliases[] __initdata = {
0305     ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi"),
0306     ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi_busclk0"),
0307     ALIAS(MUX_HSSPI1, "s3c2443-spi.1", "spi_busclk2"),
0308     ALIAS(PCLK_I2C1, "s3c2410-i2c.1", "i2c"),
0309 };
0310
0311 static int s3c2443_restart(struct notifier_block *this,
0312                unsigned long mode, void *cmd)
0313 {
0314     __raw_writel(0x533c2443, reg_base + SWRST);
0315     return NOTIFY_DONE;
0316 }
0317
0318 static struct notifier_block s3c2443_restart_handler = {
0319     .notifier_call = s3c2443_restart,
0320     .priority = 129,
0321 };
0322
0323 /*
0324  * fixed rate clocks generated outside the soc
0325  * Only necessary until the devicetree-move is complete
0326  */
0327 static struct samsung_fixed_rate_clock s3c2443_common_frate_clks[] __initdata = {
0328     FRATE(0, "xti", NULL, 0, 0),
0329     FRATE(0, "ext", NULL, 0, 0),
0330     FRATE(0, "ext_i2s", NULL, 0, 0),
0331     FRATE(0, "ext_uart", NULL, 0, 0),
0332 };
0333
0334 static void __init s3c2443_common_clk_register_fixed_ext(
0335         struct samsung_clk_provider *ctx, unsigned long xti_f)
0336 {
0337     s3c2443_common_frate_clks[0].fixed_rate = xti_f;
0338     samsung_clk_register_fixed_rate(ctx, s3c2443_common_frate_clks,
0339                 ARRAY_SIZE(s3c2443_common_frate_clks));
0340 }
0341
0342 void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
0343                     int current_soc,
0344                     void __iomem *base)
0345 {
0346     struct samsung_clk_provider *ctx;
0347     int ret;
0348     reg_base = base;
0349
0350     if (np) {
0351         reg_base = of_iomap(np, 0);
0352         if (!reg_base)
0353             panic("%s: failed to map registers\n", __func__);
0354     }
0355
0356     ctx = samsung_clk_init(np, reg_base, NR_CLKS);
0357
0358     /* Register external clocks only in non-dt cases */
0359     if (!np)
0360         s3c2443_common_clk_register_fixed_ext(ctx, xti_f);
0361
0362     /* Register PLLs. */
0363     if (current_soc == S3C2416 || current_soc == S3C2450)
0364         samsung_clk_register_pll(ctx, s3c2416_pll_clks,
0365                 ARRAY_SIZE(s3c2416_pll_clks), reg_base);
0366     else
0367         samsung_clk_register_pll(ctx, s3c2443_pll_clks,
0368                 ARRAY_SIZE(s3c2443_pll_clks), reg_base);
0369
0370     /* Register common internal clocks. */
0371     samsung_clk_register_mux(ctx, s3c2443_common_muxes,
0372             ARRAY_SIZE(s3c2443_common_muxes));
0373     samsung_clk_register_div(ctx, s3c2443_common_dividers,
0374             ARRAY_SIZE(s3c2443_common_dividers));
0375     samsung_clk_register_gate(ctx, s3c2443_common_gates,
0376         ARRAY_SIZE(s3c2443_common_gates));
0377     samsung_clk_register_alias(ctx, s3c2443_common_aliases,
0378         ARRAY_SIZE(s3c2443_common_aliases));
0379
0380     /* Register SoC-specific clocks. */
0381     switch (current_soc) {
0382     case S3C2450:
0383         samsung_clk_register_div(ctx, s3c2450_dividers,
0384                 ARRAY_SIZE(s3c2450_dividers));
0385         samsung_clk_register_mux(ctx, s3c2450_muxes,
0386                 ARRAY_SIZE(s3c2450_muxes));
0387         samsung_clk_register_gate(ctx, s3c2450_gates,
0388                 ARRAY_SIZE(s3c2450_gates));
0389         samsung_clk_register_alias(ctx, s3c2450_aliases,
0390                 ARRAY_SIZE(s3c2450_aliases));
0391         fallthrough;    /* as s3c2450 extends the s3c2416 clocks */
0392     case S3C2416:
0393         samsung_clk_register_div(ctx, s3c2416_dividers,
0394                 ARRAY_SIZE(s3c2416_dividers));
0395         samsung_clk_register_mux(ctx, s3c2416_muxes,
0396                 ARRAY_SIZE(s3c2416_muxes));
0397         samsung_clk_register_gate(ctx, s3c2416_gates,
0398                 ARRAY_SIZE(s3c2416_gates));
0399         samsung_clk_register_alias(ctx, s3c2416_aliases,
0400                 ARRAY_SIZE(s3c2416_aliases));
0401         break;
0402     case S3C2443:
0403         samsung_clk_register_div(ctx, s3c2443_dividers,
0404                 ARRAY_SIZE(s3c2443_dividers));
0405         samsung_clk_register_gate(ctx, s3c2443_gates,
0406                 ARRAY_SIZE(s3c2443_gates));
0407         samsung_clk_register_alias(ctx, s3c2443_aliases,
0408                 ARRAY_SIZE(s3c2443_aliases));
0409         break;
0410     }
0411
0412     samsung_clk_sleep_init(reg_base, s3c2443_clk_regs,
0413                    ARRAY_SIZE(s3c2443_clk_regs));
0414
0415     samsung_clk_of_add_provider(np, ctx);
0416
0417     ret = register_restart_handler(&s3c2443_restart_handler);
0418     if (ret)
0419         pr_warn("cannot register restart handler, %d\n", ret);
0420 }
0421
0422 static void __init s3c2416_clk_init(struct device_node *np)
0423 {
0424     s3c2443_common_clk_init(np, 0, S3C2416, NULL);
0425 }
0426 CLK_OF_DECLARE(s3c2416_clk, "samsung,s3c2416-clock", s3c2416_clk_init);
0427
0428 static void __init s3c2443_clk_init(struct device_node *np)
0429 {
0430     s3c2443_common_clk_init(np, 0, S3C2443, NULL);
0431 }
0432 CLK_OF_DECLARE(s3c2443_clk, "samsung,s3c2443-clock", s3c2443_clk_init);
0433
0434 static void __init s3c2450_clk_init(struct device_node *np)
0435 {
0436     s3c2443_common_clk_init(np, 0, S3C2450, NULL);
0437 }
0438 CLK_OF_DECLARE(s3c2450_clk, "samsung,s3c2450-clock", s3c2450_clk_init);