clk/samsung/clk-s3c2412.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
0004  *
0005  * Common Clock Framework support for S3C2412 and S3C2413.
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/clk/samsung.h>
0010 #include <linux/io.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013 #include <linux/reboot.h>
0014
0015 #include <dt-bindings/clock/s3c2412.h>
0016
0017 #include "clk.h"
0018 #include "clk-pll.h"
0019
0020 #define LOCKTIME    0x00
0021 #define MPLLCON     0x04
0022 #define UPLLCON     0x08
0023 #define CLKCON      0x0c
0024 #define CLKDIVN     0x14
0025 #define CLKSRC      0x1c
0026 #define SWRST       0x30
0027
0028 static void __iomem *reg_base;
0029
0030 /*
0031  * list of controller registers to be saved and restored during a
0032  * suspend/resume cycle.
0033  */
0034 static unsigned long s3c2412_clk_regs[] __initdata = {
0035     LOCKTIME,
0036     MPLLCON,
0037     UPLLCON,
0038     CLKCON,
0039     CLKDIVN,
0040     CLKSRC,
0041 };
0042
0043 static struct clk_div_table divxti_d[] = {
0044     { .val = 0, .div = 1 },
0045     { .val = 1, .div = 2 },
0046     { .val = 2, .div = 4 },
0047     { .val = 3, .div = 6 },
0048     { .val = 4, .div = 8 },
0049     { .val = 5, .div = 10 },
0050     { .val = 6, .div = 12 },
0051     { .val = 7, .div = 14 },
0052     { /* sentinel */ },
0053 };
0054
0055 static struct samsung_div_clock s3c2412_dividers[] __initdata = {
0056     DIV_T(0, "div_xti", "xti", CLKSRC, 0, 3, divxti_d),
0057     DIV(0, "div_cam", "mux_cam", CLKDIVN, 16, 4),
0058     DIV(0, "div_i2s", "mux_i2s", CLKDIVN, 12, 4),
0059     DIV(0, "div_uart", "mux_uart", CLKDIVN, 8, 4),
0060     DIV(0, "div_usb", "mux_usb", CLKDIVN, 6, 1),
0061     DIV(0, "div_hclk_half", "hclk", CLKDIVN, 5, 1),
0062     DIV(ARMDIV, "armdiv", "msysclk", CLKDIVN, 3, 1),
0063     DIV(PCLK, "pclk", "hclk", CLKDIVN, 2, 1),
0064     DIV(HCLK, "hclk", "armdiv", CLKDIVN, 0, 2),
0065 };
0066
0067 static struct samsung_fixed_factor_clock s3c2412_ffactor[] __initdata = {
0068     FFACTOR(0, "ff_hclk", "hclk", 2, 1, CLK_SET_RATE_PARENT),
0069 };
0070
0071 /*
0072  * The first two use the OM[4] setting, which is not readable from
0073  * software, so assume it is set to xti.
0074  */
0075 PNAME(erefclk_p) = { "xti", "xti", "xti", "ext" };
0076 PNAME(urefclk_p) = { "xti", "xti", "xti", "ext" };
0077
0078 PNAME(camclk_p) = { "usysclk", "hclk" };
0079 PNAME(usbclk_p) = { "usysclk", "hclk" };
0080 PNAME(i2sclk_p) = { "erefclk", "mpll" };
0081 PNAME(uartclk_p) = { "erefclk", "mpll" };
0082 PNAME(usysclk_p) = { "urefclk", "upll" };
0083 PNAME(msysclk_p) = { "mdivclk", "mpll" };
0084 PNAME(mdivclk_p) = { "xti", "div_xti" };
0085 PNAME(armclk_p) = { "armdiv", "hclk" };
0086
0087 static struct samsung_mux_clock s3c2412_muxes[] __initdata = {
0088     MUX(0, "erefclk", erefclk_p, CLKSRC, 14, 2),
0089     MUX(0, "urefclk", urefclk_p, CLKSRC, 12, 2),
0090     MUX(0, "mux_cam", camclk_p, CLKSRC, 11, 1),
0091     MUX(0, "mux_usb", usbclk_p, CLKSRC, 10, 1),
0092     MUX(0, "mux_i2s", i2sclk_p, CLKSRC, 9, 1),
0093     MUX(0, "mux_uart", uartclk_p, CLKSRC, 8, 1),
0094     MUX(USYSCLK, "usysclk", usysclk_p, CLKSRC, 5, 1),
0095     MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
0096     MUX(MDIVCLK, "mdivclk", mdivclk_p, CLKSRC, 3, 1),
0097     MUX(ARMCLK, "armclk", armclk_p, CLKDIVN, 4, 1),
0098 };
0099
0100 static struct samsung_pll_clock s3c2412_plls[] __initdata = {
0101     PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL),
0102     PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk", LOCKTIME, UPLLCON, NULL),
0103 };
0104
0105 static struct samsung_gate_clock s3c2412_gates[] __initdata = {
0106     GATE(PCLK_WDT, "wdt", "pclk", CLKCON, 28, 0, 0),
0107     GATE(PCLK_SPI, "spi", "pclk", CLKCON, 27, 0, 0),
0108     GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 26, 0, 0),
0109     GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 25, 0, 0),
0110     GATE(PCLK_ADC, "adc", "pclk", CLKCON, 24, 0, 0),
0111     GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 23, 0, 0),
0112     GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 22, CLK_IGNORE_UNUSED, 0),
0113     GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 21, 0, 0),
0114     GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 20, 0, 0),
0115     GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 19, 0, 0),
0116     GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 18, 0, 0),
0117     GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 17, 0, 0),
0118     GATE(PCLK_USBD, "usb-device", "pclk", CLKCON, 16, 0, 0),
0119     GATE(SCLK_CAM, "sclk_cam", "div_cam", CLKCON, 15, 0, 0),
0120     GATE(SCLK_UART, "sclk_uart", "div_uart", CLKCON, 14, 0, 0),
0121     GATE(SCLK_I2S, "sclk_i2s", "div_i2s", CLKCON, 13, 0, 0),
0122     GATE(SCLK_USBH, "sclk_usbh", "div_usb", CLKCON, 12, 0, 0),
0123     GATE(SCLK_USBD, "sclk_usbd", "div_usb", CLKCON, 11, 0, 0),
0124     GATE(HCLK_HALF, "hclk_half", "div_hclk_half", CLKCON, 10, CLK_IGNORE_UNUSED, 0),
0125     GATE(HCLK_X2, "hclkx2", "ff_hclk", CLKCON, 9, CLK_IGNORE_UNUSED, 0),
0126     GATE(HCLK_SDRAM, "sdram", "hclk", CLKCON, 8, CLK_IGNORE_UNUSED, 0),
0127     GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
0128     GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
0129     GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
0130     GATE(HCLK_DMA3, "dma3", "hclk", CLKCON, 3, CLK_IGNORE_UNUSED, 0),
0131     GATE(HCLK_DMA2, "dma2", "hclk", CLKCON, 2, CLK_IGNORE_UNUSED, 0),
0132     GATE(HCLK_DMA1, "dma1", "hclk", CLKCON, 1, CLK_IGNORE_UNUSED, 0),
0133     GATE(HCLK_DMA0, "dma0", "hclk", CLKCON, 0, CLK_IGNORE_UNUSED, 0),
0134 };
0135
0136 static struct samsung_clock_alias s3c2412_aliases[] __initdata = {
0137     ALIAS(PCLK_UART0, "s3c2412-uart.0", "uart"),
0138     ALIAS(PCLK_UART1, "s3c2412-uart.1", "uart"),
0139     ALIAS(PCLK_UART2, "s3c2412-uart.2", "uart"),
0140     ALIAS(PCLK_UART0, "s3c2412-uart.0", "clk_uart_baud2"),
0141     ALIAS(PCLK_UART1, "s3c2412-uart.1", "clk_uart_baud2"),
0142     ALIAS(PCLK_UART2, "s3c2412-uart.2", "clk_uart_baud2"),
0143     ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
0144     ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
0145     ALIAS(PCLK_ADC, NULL, "adc"),
0146     ALIAS(PCLK_RTC, NULL, "rtc"),
0147     ALIAS(PCLK_PWM, NULL, "timers"),
0148     ALIAS(HCLK_LCD, NULL, "lcd"),
0149     ALIAS(PCLK_USBD, NULL, "usb-device"),
0150     ALIAS(SCLK_USBD, NULL, "usb-bus-gadget"),
0151     ALIAS(HCLK_USBH, NULL, "usb-host"),
0152     ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
0153     ALIAS(ARMCLK, NULL, "armclk"),
0154     ALIAS(HCLK, NULL, "hclk"),
0155     ALIAS(MPLL, NULL, "mpll"),
0156     ALIAS(MSYSCLK, NULL, "fclk"),
0157 };
0158
0159 static int s3c2412_restart(struct notifier_block *this,
0160                unsigned long mode, void *cmd)
0161 {
0162     /* errata "Watch-dog/Software Reset Problem" specifies that
0163      * this reset must be done with the SYSCLK sourced from
0164      * EXTCLK instead of FOUT to avoid a glitch in the reset
0165      * mechanism.
0166      *
0167      * See the watchdog section of the S3C2412 manual for more
0168      * information on this fix.
0169      */
0170
0171     __raw_writel(0x00, reg_base + CLKSRC);
0172     __raw_writel(0x533C2412, reg_base + SWRST);
0173     return NOTIFY_DONE;
0174 }
0175
0176 static struct notifier_block s3c2412_restart_handler = {
0177     .notifier_call = s3c2412_restart,
0178     .priority = 129,
0179 };
0180
0181 /*
0182  * fixed rate clocks generated outside the soc
0183  * Only necessary until the devicetree-move is complete
0184  */
0185 #define XTI 1
0186 static struct samsung_fixed_rate_clock s3c2412_common_frate_clks[] __initdata = {
0187     FRATE(XTI, "xti", NULL, 0, 0),
0188     FRATE(0, "ext", NULL, 0, 0),
0189 };
0190
0191 static void __init s3c2412_common_clk_register_fixed_ext(
0192         struct samsung_clk_provider *ctx,
0193         unsigned long xti_f, unsigned long ext_f)
0194 {
0195     /* xtal alias is necessary for the current cpufreq driver */
0196     struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
0197
0198     s3c2412_common_frate_clks[0].fixed_rate = xti_f;
0199     s3c2412_common_frate_clks[1].fixed_rate = ext_f;
0200     samsung_clk_register_fixed_rate(ctx, s3c2412_common_frate_clks,
0201                 ARRAY_SIZE(s3c2412_common_frate_clks));
0202
0203     samsung_clk_register_alias(ctx, &xti_alias, 1);
0204 }
0205
0206 void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
0207                     unsigned long ext_f, void __iomem *base)
0208 {
0209     struct samsung_clk_provider *ctx;
0210     int ret;
0211     reg_base = base;
0212
0213     if (np) {
0214         reg_base = of_iomap(np, 0);
0215         if (!reg_base)
0216             panic("%s: failed to map registers\n", __func__);
0217     }
0218
0219     ctx = samsung_clk_init(np, reg_base, NR_CLKS);
0220
0221     /* Register external clocks only in non-dt cases */
0222     if (!np)
0223         s3c2412_common_clk_register_fixed_ext(ctx, xti_f, ext_f);
0224
0225     /* Register PLLs. */
0226     samsung_clk_register_pll(ctx, s3c2412_plls, ARRAY_SIZE(s3c2412_plls),
0227                  reg_base);
0228
0229     /* Register common internal clocks. */
0230     samsung_clk_register_mux(ctx, s3c2412_muxes, ARRAY_SIZE(s3c2412_muxes));
0231     samsung_clk_register_div(ctx, s3c2412_dividers,
0232                       ARRAY_SIZE(s3c2412_dividers));
0233     samsung_clk_register_gate(ctx, s3c2412_gates,
0234                     ARRAY_SIZE(s3c2412_gates));
0235     samsung_clk_register_fixed_factor(ctx, s3c2412_ffactor,
0236                       ARRAY_SIZE(s3c2412_ffactor));
0237     samsung_clk_register_alias(ctx, s3c2412_aliases,
0238                    ARRAY_SIZE(s3c2412_aliases));
0239
0240     samsung_clk_sleep_init(reg_base, s3c2412_clk_regs,
0241                    ARRAY_SIZE(s3c2412_clk_regs));
0242
0243     samsung_clk_of_add_provider(np, ctx);
0244
0245     ret = register_restart_handler(&s3c2412_restart_handler);
0246     if (ret)
0247         pr_warn("cannot register restart handler, %d\n", ret);
0248 }
0249
0250 static void __init s3c2412_clk_init(struct device_node *np)
0251 {
0252     s3c2412_common_clk_init(np, 0, 0, NULL);
0253 }
0254 CLK_OF_DECLARE(s3c2412_clk, "samsung,s3c2412-clock", s3c2412_clk_init);