clk/samsung/clk-s3c2410.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
0004  *
0005  * Common Clock Framework support for S3C2410 and following SoCs.
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/clk/samsung.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012
0013 #include <dt-bindings/clock/s3c2410.h>
0014
0015 #include "clk.h"
0016 #include "clk-pll.h"
0017
0018 #define LOCKTIME    0x00
0019 #define MPLLCON     0x04
0020 #define UPLLCON     0x08
0021 #define CLKCON      0x0c
0022 #define CLKSLOW     0x10
0023 #define CLKDIVN     0x14
0024 #define CAMDIVN     0x18
0025
0026 /* the soc types */
0027 enum supported_socs {
0028     S3C2410,
0029     S3C2440,
0030     S3C2442,
0031 };
0032
0033 /* list of PLLs to be registered */
0034 enum s3c2410_plls {
0035     mpll, upll,
0036 };
0037
0038 static void __iomem *reg_base;
0039
0040 /*
0041  * list of controller registers to be saved and restored during a
0042  * suspend/resume cycle.
0043  */
0044 static unsigned long s3c2410_clk_regs[] __initdata = {
0045     LOCKTIME,
0046     MPLLCON,
0047     UPLLCON,
0048     CLKCON,
0049     CLKSLOW,
0050     CLKDIVN,
0051     CAMDIVN,
0052 };
0053
0054 PNAME(fclk_p) = { "mpll", "div_slow" };
0055
0056 static struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {
0057     MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
0058 };
0059
0060 static struct clk_div_table divslow_d[] = {
0061     { .val = 0, .div = 1 },
0062     { .val = 1, .div = 2 },
0063     { .val = 2, .div = 4 },
0064     { .val = 3, .div = 6 },
0065     { .val = 4, .div = 8 },
0066     { .val = 5, .div = 10 },
0067     { .val = 6, .div = 12 },
0068     { .val = 7, .div = 14 },
0069     { /* sentinel */ },
0070 };
0071
0072 static struct samsung_div_clock s3c2410_common_dividers[] __initdata = {
0073     DIV_T(0, "div_slow", "xti", CLKSLOW, 0, 3, divslow_d),
0074     DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
0075 };
0076
0077 static struct samsung_gate_clock s3c2410_common_gates[] __initdata = {
0078     GATE(PCLK_SPI, "spi", "pclk", CLKCON, 18, 0, 0),
0079     GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 17, 0, 0),
0080     GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 16, 0, 0),
0081     GATE(PCLK_ADC, "adc", "pclk", CLKCON, 15, 0, 0),
0082     GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 14, 0, 0),
0083     GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 13, CLK_IGNORE_UNUSED, 0),
0084     GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 12, 0, 0),
0085     GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0),
0086     GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0),
0087     GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 9, 0, 0),
0088     GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 8, 0, 0),
0089     GATE(HCLK_USBD, "usb-device", "hclk", CLKCON, 7, 0, 0),
0090     GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
0091     GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
0092     GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
0093 };
0094
0095 /* should be added _after_ the soc-specific clocks are created */
0096 static struct samsung_clock_alias s3c2410_common_aliases[] __initdata = {
0097     ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
0098     ALIAS(PCLK_ADC, NULL, "adc"),
0099     ALIAS(PCLK_RTC, NULL, "rtc"),
0100     ALIAS(PCLK_PWM, NULL, "timers"),
0101     ALIAS(HCLK_LCD, NULL, "lcd"),
0102     ALIAS(HCLK_USBD, NULL, "usb-device"),
0103     ALIAS(HCLK_USBH, NULL, "usb-host"),
0104     ALIAS(UCLK, NULL, "usb-bus-host"),
0105     ALIAS(UCLK, NULL, "usb-bus-gadget"),
0106     ALIAS(ARMCLK, NULL, "armclk"),
0107     ALIAS(UCLK, NULL, "uclk"),
0108     ALIAS(HCLK, NULL, "hclk"),
0109     ALIAS(MPLL, NULL, "mpll"),
0110     ALIAS(FCLK, NULL, "fclk"),
0111     ALIAS(PCLK, NULL, "watchdog"),
0112     ALIAS(PCLK_SDI, NULL, "sdi"),
0113     ALIAS(HCLK_NAND, NULL, "nand"),
0114     ALIAS(PCLK_I2S, NULL, "iis"),
0115     ALIAS(PCLK_I2C, NULL, "i2c"),
0116 };
0117
0118 /* S3C2410 specific clocks */
0119
0120 static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = {
0121     /* sorted in descending order */
0122     /* 2410A extras */
0123     PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
0124     PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
0125     PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
0126     PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
0127     PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
0128     /* 2410 common */
0129     PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
0130     PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
0131     PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
0132     PLL_S3C2410_MPLL_RATE(12 * MHZ, 180000000, 82, 1, 1),
0133     PLL_S3C2410_MPLL_RATE(12 * MHZ, 170000000, 77, 1, 1),
0134     PLL_S3C2410_MPLL_RATE(12 * MHZ, 158000000, 71, 1, 1),
0135     PLL_S3C2410_MPLL_RATE(12 * MHZ, 152000000, 68, 1, 1),
0136     PLL_S3C2410_MPLL_RATE(12 * MHZ, 147000000, 90, 2, 1),
0137     PLL_S3C2410_MPLL_RATE(12 * MHZ, 135000000, 82, 2, 1),
0138     PLL_S3C2410_MPLL_RATE(12 * MHZ, 124000000, 116, 1, 2),
0139     PLL_S3C2410_MPLL_RATE(12 * MHZ, 118500000, 150, 2, 2),
0140     PLL_S3C2410_MPLL_RATE(12 * MHZ, 113000000, 105, 1, 2),
0141     PLL_S3C2410_MPLL_RATE(12 * MHZ, 101250000, 127, 2, 2),
0142     PLL_S3C2410_MPLL_RATE(12 * MHZ, 90000000, 112, 2, 2),
0143     PLL_S3C2410_MPLL_RATE(12 * MHZ, 84750000, 105, 2, 2),
0144     PLL_S3C2410_MPLL_RATE(12 * MHZ, 79000000, 71, 1, 2),
0145     PLL_S3C2410_MPLL_RATE(12 * MHZ, 67500000, 82, 2, 2),
0146     PLL_S3C2410_MPLL_RATE(12 * MHZ, 56250000, 142, 2, 3),
0147     PLL_S3C2410_MPLL_RATE(12 * MHZ, 48000000, 120, 2, 3),
0148     PLL_S3C2410_MPLL_RATE(12 * MHZ, 50700000, 161, 3, 3),
0149     PLL_S3C2410_MPLL_RATE(12 * MHZ, 45000000, 82, 1, 3),
0150     PLL_S3C2410_MPLL_RATE(12 * MHZ, 33750000, 82, 2, 3),
0151     { /* sentinel */ },
0152 };
0153
0154 static struct samsung_pll_clock s3c2410_plls[] __initdata = {
0155     [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
0156                         LOCKTIME, MPLLCON, NULL),
0157     [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
0158                         LOCKTIME, UPLLCON, NULL),
0159 };
0160
0161 static struct samsung_div_clock s3c2410_dividers[] __initdata = {
0162     DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
0163 };
0164
0165 static struct samsung_fixed_factor_clock s3c2410_ffactor[] __initdata = {
0166     /*
0167      * armclk is directly supplied by the fclk, without
0168      * switching possibility like on the s3c244x below.
0169      */
0170     FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
0171
0172     /* uclk is fed from the unmodified upll */
0173     FFACTOR(UCLK, "uclk", "upll", 1, 1, 0),
0174 };
0175
0176 static struct samsung_clock_alias s3c2410_aliases[] __initdata = {
0177     ALIAS(PCLK_UART0, "s3c2410-uart.0", "uart"),
0178     ALIAS(PCLK_UART1, "s3c2410-uart.1", "uart"),
0179     ALIAS(PCLK_UART2, "s3c2410-uart.2", "uart"),
0180     ALIAS(PCLK_UART0, "s3c2410-uart.0", "clk_uart_baud0"),
0181     ALIAS(PCLK_UART1, "s3c2410-uart.1", "clk_uart_baud0"),
0182     ALIAS(PCLK_UART2, "s3c2410-uart.2", "clk_uart_baud0"),
0183     ALIAS(UCLK, NULL, "clk_uart_baud1"),
0184 };
0185
0186 /* S3C244x specific clocks */
0187
0188 static struct samsung_pll_rate_table pll_s3c244x_12mhz_tbl[] __initdata = {
0189     /* sorted in descending order */
0190     PLL_S3C2440_MPLL_RATE(12 * MHZ, 400000000, 0x5c, 1, 1),
0191     PLL_S3C2440_MPLL_RATE(12 * MHZ, 390000000, 0x7a, 2, 1),
0192     PLL_S3C2440_MPLL_RATE(12 * MHZ, 380000000, 0x57, 1, 1),
0193     PLL_S3C2440_MPLL_RATE(12 * MHZ, 370000000, 0xb1, 4, 1),
0194     PLL_S3C2440_MPLL_RATE(12 * MHZ, 360000000, 0x70, 2, 1),
0195     PLL_S3C2440_MPLL_RATE(12 * MHZ, 350000000, 0xa7, 4, 1),
0196     PLL_S3C2440_MPLL_RATE(12 * MHZ, 340000000, 0x4d, 1, 1),
0197     PLL_S3C2440_MPLL_RATE(12 * MHZ, 330000000, 0x66, 2, 1),
0198     PLL_S3C2440_MPLL_RATE(12 * MHZ, 320000000, 0x98, 4, 1),
0199     PLL_S3C2440_MPLL_RATE(12 * MHZ, 310000000, 0x93, 4, 1),
0200     PLL_S3C2440_MPLL_RATE(12 * MHZ, 300000000, 0x75, 3, 1),
0201     PLL_S3C2440_MPLL_RATE(12 * MHZ, 240000000, 0x70, 1, 2),
0202     PLL_S3C2440_MPLL_RATE(12 * MHZ, 230000000, 0x6b, 1, 2),
0203     PLL_S3C2440_MPLL_RATE(12 * MHZ, 220000000, 0x66, 1, 2),
0204     PLL_S3C2440_MPLL_RATE(12 * MHZ, 210000000, 0x84, 2, 2),
0205     PLL_S3C2440_MPLL_RATE(12 * MHZ, 200000000, 0x5c, 1, 2),
0206     PLL_S3C2440_MPLL_RATE(12 * MHZ, 190000000, 0x57, 1, 2),
0207     PLL_S3C2440_MPLL_RATE(12 * MHZ, 180000000, 0x70, 2, 2),
0208     PLL_S3C2440_MPLL_RATE(12 * MHZ, 170000000, 0x4d, 1, 2),
0209     PLL_S3C2440_MPLL_RATE(12 * MHZ, 160000000, 0x98, 4, 2),
0210     PLL_S3C2440_MPLL_RATE(12 * MHZ, 150000000, 0x75, 3, 2),
0211     PLL_S3C2440_MPLL_RATE(12 * MHZ, 120000000, 0x70, 1, 3),
0212     PLL_S3C2440_MPLL_RATE(12 * MHZ, 110000000, 0x66, 1, 3),
0213     PLL_S3C2440_MPLL_RATE(12 * MHZ, 100000000, 0x5c, 1, 3),
0214     PLL_S3C2440_MPLL_RATE(12 * MHZ, 90000000, 0x70, 2, 3),
0215     PLL_S3C2440_MPLL_RATE(12 * MHZ, 80000000, 0x98, 4, 3),
0216     PLL_S3C2440_MPLL_RATE(12 * MHZ, 75000000, 0x75, 3, 3),
0217     { /* sentinel */ },
0218 };
0219
0220 static struct samsung_pll_clock s3c244x_common_plls[] __initdata = {
0221     [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
0222                         LOCKTIME, MPLLCON, NULL),
0223     [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
0224                         LOCKTIME, UPLLCON, NULL),
0225 };
0226
0227 PNAME(hclk_p) = { "fclk", "div_hclk_2", "div_hclk_4", "div_hclk_3" };
0228 PNAME(armclk_p) = { "fclk", "hclk" };
0229
0230 static struct samsung_mux_clock s3c244x_common_muxes[] __initdata = {
0231     MUX(HCLK, "hclk", hclk_p, CLKDIVN, 1, 2),
0232     MUX(ARMCLK, "armclk", armclk_p, CAMDIVN, 12, 1),
0233 };
0234
0235 static struct samsung_fixed_factor_clock s3c244x_common_ffactor[] __initdata = {
0236     FFACTOR(0, "div_hclk_2", "fclk", 1, 2, 0),
0237     FFACTOR(0, "ff_cam", "div_cam", 2, 1, CLK_SET_RATE_PARENT),
0238 };
0239
0240 static struct clk_div_table div_hclk_4_d[] = {
0241     { .val = 0, .div = 4 },
0242     { .val = 1, .div = 8 },
0243     { /* sentinel */ },
0244 };
0245
0246 static struct clk_div_table div_hclk_3_d[] = {
0247     { .val = 0, .div = 3 },
0248     { .val = 1, .div = 6 },
0249     { /* sentinel */ },
0250 };
0251
0252 static struct samsung_div_clock s3c244x_common_dividers[] __initdata = {
0253     DIV(UCLK, "uclk", "upll", CLKDIVN, 3, 1),
0254     DIV(0, "div_hclk", "fclk", CLKDIVN, 1, 1),
0255     DIV_T(0, "div_hclk_4", "fclk", CAMDIVN, 9, 1, div_hclk_4_d),
0256     DIV_T(0, "div_hclk_3", "fclk", CAMDIVN, 8, 1, div_hclk_3_d),
0257     DIV(0, "div_cam", "upll", CAMDIVN, 0, 3),
0258 };
0259
0260 static struct samsung_gate_clock s3c244x_common_gates[] __initdata = {
0261     GATE(HCLK_CAM, "cam", "hclk", CLKCON, 19, 0, 0),
0262 };
0263
0264 static struct samsung_clock_alias s3c244x_common_aliases[] __initdata = {
0265     ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
0266     ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
0267     ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
0268     ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
0269     ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
0270     ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
0271     ALIAS(HCLK_CAM, NULL, "camif"),
0272     ALIAS(CAMIF, NULL, "camif-upll"),
0273 };
0274
0275 /* S3C2440 specific clocks */
0276
0277 PNAME(s3c2440_camif_p) = { "upll", "ff_cam" };
0278
0279 static struct samsung_mux_clock s3c2440_muxes[] __initdata = {
0280     MUX(CAMIF, "camif", s3c2440_camif_p, CAMDIVN, 4, 1),
0281 };
0282
0283 static struct samsung_gate_clock s3c2440_gates[] __initdata = {
0284     GATE(PCLK_AC97, "ac97", "pclk", CLKCON, 20, 0, 0),
0285 };
0286
0287 /* S3C2442 specific clocks */
0288
0289 static struct samsung_fixed_factor_clock s3c2442_ffactor[] __initdata = {
0290     FFACTOR(0, "upll_3", "upll", 1, 3, 0),
0291 };
0292
0293 PNAME(s3c2442_camif_p) = { "upll", "ff_cam", "upll", "upll_3" };
0294
0295 static struct samsung_mux_clock s3c2442_muxes[] __initdata = {
0296     MUX(CAMIF, "camif", s3c2442_camif_p, CAMDIVN, 4, 2),
0297 };
0298
0299 /*
0300  * fixed rate clocks generated outside the soc
0301  * Only necessary until the devicetree-move is complete
0302  */
0303 #define XTI 1
0304 static struct samsung_fixed_rate_clock s3c2410_common_frate_clks[] __initdata = {
0305     FRATE(XTI, "xti", NULL, 0, 0),
0306 };
0307
0308 static void __init s3c2410_common_clk_register_fixed_ext(
0309         struct samsung_clk_provider *ctx,
0310         unsigned long xti_f)
0311 {
0312     struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
0313
0314     s3c2410_common_frate_clks[0].fixed_rate = xti_f;
0315     samsung_clk_register_fixed_rate(ctx, s3c2410_common_frate_clks,
0316                 ARRAY_SIZE(s3c2410_common_frate_clks));
0317
0318     samsung_clk_register_alias(ctx, &xti_alias, 1);
0319 }
0320
0321 void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
0322                     int current_soc,
0323                     void __iomem *base)
0324 {
0325     struct samsung_clk_provider *ctx;
0326     struct clk_hw **hws;
0327     reg_base = base;
0328
0329     if (np) {
0330         reg_base = of_iomap(np, 0);
0331         if (!reg_base)
0332             panic("%s: failed to map registers\n", __func__);
0333     }
0334
0335     ctx = samsung_clk_init(np, reg_base, NR_CLKS);
0336     hws = ctx->clk_data.hws;
0337
0338     /* Register external clocks only in non-dt cases */
0339     if (!np)
0340         s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
0341
0342     if (current_soc == S3C2410) {
0343         if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) {
0344             s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
0345             s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
0346         }
0347
0348         /* Register PLLs. */
0349         samsung_clk_register_pll(ctx, s3c2410_plls,
0350                 ARRAY_SIZE(s3c2410_plls), reg_base);
0351
0352     } else { /* S3C2440, S3C2442 */
0353         if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) {
0354             /*
0355              * plls follow different calculation schemes, with the
0356              * upll following the same scheme as the s3c2410 plls
0357              */
0358             s3c244x_common_plls[mpll].rate_table =
0359                             pll_s3c244x_12mhz_tbl;
0360             s3c244x_common_plls[upll].rate_table =
0361                             pll_s3c2410_12mhz_tbl;
0362         }
0363
0364         /* Register PLLs. */
0365         samsung_clk_register_pll(ctx, s3c244x_common_plls,
0366                 ARRAY_SIZE(s3c244x_common_plls), reg_base);
0367     }
0368
0369     /* Register common internal clocks. */
0370     samsung_clk_register_mux(ctx, s3c2410_common_muxes,
0371             ARRAY_SIZE(s3c2410_common_muxes));
0372     samsung_clk_register_div(ctx, s3c2410_common_dividers,
0373             ARRAY_SIZE(s3c2410_common_dividers));
0374     samsung_clk_register_gate(ctx, s3c2410_common_gates,
0375         ARRAY_SIZE(s3c2410_common_gates));
0376
0377     if (current_soc == S3C2440 || current_soc == S3C2442) {
0378         samsung_clk_register_div(ctx, s3c244x_common_dividers,
0379                 ARRAY_SIZE(s3c244x_common_dividers));
0380         samsung_clk_register_gate(ctx, s3c244x_common_gates,
0381                 ARRAY_SIZE(s3c244x_common_gates));
0382         samsung_clk_register_mux(ctx, s3c244x_common_muxes,
0383                 ARRAY_SIZE(s3c244x_common_muxes));
0384         samsung_clk_register_fixed_factor(ctx, s3c244x_common_ffactor,
0385                 ARRAY_SIZE(s3c244x_common_ffactor));
0386     }
0387
0388     /* Register SoC-specific clocks. */
0389     switch (current_soc) {
0390     case S3C2410:
0391         samsung_clk_register_div(ctx, s3c2410_dividers,
0392                 ARRAY_SIZE(s3c2410_dividers));
0393         samsung_clk_register_fixed_factor(ctx, s3c2410_ffactor,
0394                 ARRAY_SIZE(s3c2410_ffactor));
0395         samsung_clk_register_alias(ctx, s3c2410_aliases,
0396             ARRAY_SIZE(s3c2410_aliases));
0397         break;
0398     case S3C2440:
0399         samsung_clk_register_mux(ctx, s3c2440_muxes,
0400                 ARRAY_SIZE(s3c2440_muxes));
0401         samsung_clk_register_gate(ctx, s3c2440_gates,
0402                 ARRAY_SIZE(s3c2440_gates));
0403         break;
0404     case S3C2442:
0405         samsung_clk_register_mux(ctx, s3c2442_muxes,
0406                 ARRAY_SIZE(s3c2442_muxes));
0407         samsung_clk_register_fixed_factor(ctx, s3c2442_ffactor,
0408                 ARRAY_SIZE(s3c2442_ffactor));
0409         break;
0410     }
0411
0412     /*
0413      * Register common aliases at the end, as some of the aliased clocks
0414      * are SoC specific.
0415      */
0416     samsung_clk_register_alias(ctx, s3c2410_common_aliases,
0417         ARRAY_SIZE(s3c2410_common_aliases));
0418
0419     if (current_soc == S3C2440 || current_soc == S3C2442) {
0420         samsung_clk_register_alias(ctx, s3c244x_common_aliases,
0421             ARRAY_SIZE(s3c244x_common_aliases));
0422     }
0423
0424     samsung_clk_sleep_init(reg_base, s3c2410_clk_regs,
0425                    ARRAY_SIZE(s3c2410_clk_regs));
0426
0427     samsung_clk_of_add_provider(np, ctx);
0428 }
0429
0430 static void __init s3c2410_clk_init(struct device_node *np)
0431 {
0432     s3c2410_common_clk_init(np, 0, S3C2410, NULL);
0433 }
0434 CLK_OF_DECLARE(s3c2410_clk, "samsung,s3c2410-clock", s3c2410_clk_init);
0435
0436 static void __init s3c2440_clk_init(struct device_node *np)
0437 {
0438     s3c2410_common_clk_init(np, 0, S3C2440, NULL);
0439 }
0440 CLK_OF_DECLARE(s3c2440_clk, "samsung,s3c2440-clock", s3c2440_clk_init);
0441
0442 static void __init s3c2442_clk_init(struct device_node *np)
0443 {
0444     s3c2410_common_clk_init(np, 0, S3C2442, NULL);
0445 }
0446 CLK_OF_DECLARE(s3c2442_clk, "samsung,s3c2442-clock", s3c2442_clk_init);