clk/samsung/clk-pll.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
0004  * Copyright (c) 2013 Linaro Ltd.
0005  *
0006  * Common Clock Framework support for all PLL's in Samsung platforms
0007 */
0008
0009 #ifndef __SAMSUNG_CLK_PLL_H
0010 #define __SAMSUNG_CLK_PLL_H
0011
0012 enum samsung_pll_type {
0013     pll_2126,
0014     pll_3000,
0015     pll_35xx,
0016     pll_36xx,
0017     pll_2550,
0018     pll_2650,
0019     pll_4500,
0020     pll_4502,
0021     pll_4508,
0022     pll_4600,
0023     pll_4650,
0024     pll_4650c,
0025     pll_6552,
0026     pll_6552_s3c2416,
0027     pll_6553,
0028     pll_s3c2410_mpll,
0029     pll_s3c2410_upll,
0030     pll_s3c2440_mpll,
0031     pll_2550x,
0032     pll_2550xx,
0033     pll_2650x,
0034     pll_2650xx,
0035     pll_1417x,
0036     pll_1450x,
0037     pll_1451x,
0038     pll_1452x,
0039     pll_1460x,
0040     pll_0822x,
0041     pll_0831x,
0042     pll_142xx,
0043 };
0044
0045 #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
0046     ((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
0047 #define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
0048     BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
0049
0050 #define PLL_35XX_RATE(_fin, _rate, _m, _p, _s)          \
0051     {                           \
0052         .rate   =   PLL_VALID_RATE(_fin, _rate, \
0053                 _m, _p, _s, 0, 16),     \
0054         .mdiv   =   (_m),               \
0055         .pdiv   =   (_p),               \
0056         .sdiv   =   (_s),               \
0057     }
0058
0059 #define PLL_S3C2410_MPLL_RATE(_fin, _rate, _m, _p, _s)      \
0060     {                           \
0061         .rate   =   PLL_VALID_RATE(_fin, _rate, \
0062                 _m + 8, _p + 2, _s, 0, 16), \
0063         .mdiv   =   (_m),               \
0064         .pdiv   =   (_p),               \
0065         .sdiv   =   (_s),               \
0066     }
0067
0068 #define PLL_S3C2440_MPLL_RATE(_fin, _rate, _m, _p, _s)      \
0069     {                           \
0070         .rate   =   PLL_VALID_RATE(_fin, _rate, \
0071                 2 * (_m + 8), _p + 2, _s, 0, 16), \
0072         .mdiv   =   (_m),               \
0073         .pdiv   =   (_p),               \
0074         .sdiv   =   (_s),               \
0075     }
0076
0077 #define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k)      \
0078     {                           \
0079         .rate   =   PLL_VALID_RATE(_fin, _rate, \
0080                 _m, _p, _s, _k, 16),        \
0081         .mdiv   =   (_m),               \
0082         .pdiv   =   (_p),               \
0083         .sdiv   =   (_s),               \
0084         .kdiv   =   (_k),               \
0085     }
0086
0087 #define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc)        \
0088     {                           \
0089         .rate   =   PLL_VALID_RATE(_fin, _rate, \
0090                 _m, _p, _s - 1, 0, 16),     \
0091         .mdiv   =   (_m),               \
0092         .pdiv   =   (_p),               \
0093         .sdiv   =   (_s),               \
0094         .afc    =   (_afc),             \
0095     }
0096
0097 #define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel)   \
0098     {                           \
0099         .rate   =   PLL_VALID_RATE(_fin, _rate, \
0100                 _m, _p, _s, _k, 16),        \
0101         .mdiv   =   (_m),               \
0102         .pdiv   =   (_p),               \
0103         .sdiv   =   (_s),               \
0104         .kdiv   =   (_k),               \
0105         .vsel   =   (_vsel),            \
0106     }
0107
0108 #define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
0109     {                           \
0110         .rate   =   PLL_VALID_RATE(_fin, _rate, \
0111                 _m, _p, _s, _k, 10),        \
0112         .mdiv   =   (_m),               \
0113         .pdiv   =   (_p),               \
0114         .sdiv   =   (_s),               \
0115         .kdiv   =   (_k),               \
0116         .mfr    =   (_mfr),             \
0117         .mrr    =   (_mrr),             \
0118         .vsel   =   (_vsel),            \
0119     }
0120
0121 /* NOTE: Rate table should be kept sorted in descending order. */
0122
0123 struct samsung_pll_rate_table {
0124     unsigned int rate;
0125     unsigned int pdiv;
0126     unsigned int mdiv;
0127     unsigned int sdiv;
0128     unsigned int kdiv;
0129     unsigned int afc;
0130     unsigned int mfr;
0131     unsigned int mrr;
0132     unsigned int vsel;
0133 };
0134
0135 #endif /* __SAMSUNG_CLK_PLL_H */