clk/samsung/clk-exynosautov9.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2022 Samsung Electronics Co., Ltd.
0004  * Author: Chanho Park <chanho61.park@samsung.com>
0005  *
0006  * Common Clock Framework support for ExynosAuto V9 SoC.
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013 #include <linux/of_device.h>
0014 #include <linux/platform_device.h>
0015
0016 #include <dt-bindings/clock/samsung,exynosautov9.h>
0017
0018 #include "clk.h"
0019 #include "clk-exynos-arm64.h"
0020
0021 /* ---- CMU_TOP ------------------------------------------------------------ */
0022
0023 /* Register Offset definitions for CMU_TOP (0x1b240000) */
0024 #define PLL_LOCKTIME_PLL_SHARED0        0x0000
0025 #define PLL_LOCKTIME_PLL_SHARED1        0x0004
0026 #define PLL_LOCKTIME_PLL_SHARED2        0x0008
0027 #define PLL_LOCKTIME_PLL_SHARED3        0x000c
0028 #define PLL_LOCKTIME_PLL_SHARED4        0x0010
0029 #define PLL_CON0_PLL_SHARED0            0x0100
0030 #define PLL_CON3_PLL_SHARED0            0x010c
0031 #define PLL_CON0_PLL_SHARED1            0x0140
0032 #define PLL_CON3_PLL_SHARED1            0x014c
0033 #define PLL_CON0_PLL_SHARED2            0x0180
0034 #define PLL_CON3_PLL_SHARED2            0x018c
0035 #define PLL_CON0_PLL_SHARED3            0x01c0
0036 #define PLL_CON3_PLL_SHARED3            0x01cc
0037 #define PLL_CON0_PLL_SHARED4            0x0200
0038 #define PLL_CON3_PLL_SHARED4            0x020c
0039
0040 /* MUX */
0041 #define CLK_CON_MUX_MUX_CLKCMU_ACC_BUS      0x1000
0042 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS      0x1004
0043 #define CLK_CON_MUX_MUX_CLKCMU_AUD_BUS      0x1008
0044 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU      0x100c
0045 #define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS     0x1010
0046 #define CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS    0x1018
0047 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST    0x101c
0048 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS     0x1020
0049 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER   0x1024
0050 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH    0x102c
0051 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER   0x1030
0052 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH    0x1034
0053 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS     0x1040
0054 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC   0x1044
0055 #define CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS     0x1048
0056 #define CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS    0x104c
0057 #define CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS    0x1050
0058 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS    0x1054
0059 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE   0x1058
0060 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS    0x105c
0061 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD   0x1060
0062 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD 0x1064
0063 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS    0x1068
0064 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET   0x106c
0065 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD   0x1070
0066 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D      0x1074
0067 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL     0x1078
0068 #define CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH 0x107c
0069 #define CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH 0x1080
0070 #define CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH  0x1084
0071 #define CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS     0x108c
0072 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC      0x1090
0073 #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD      0x1094
0074 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH   0x109c
0075 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP     0x1098
0076 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH   0x109c
0077 #define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS      0x10a0
0078 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS   0x10a4
0079 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP    0x10a8
0080 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS   0x10ac
0081 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP    0x10b0
0082 #define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS    0x10b4
0083 #define CLK_CON_MUX_MUX_CMU_CMUREF      0x10c0
0084
0085 /* DIV */
0086 #define CLK_CON_DIV_CLKCMU_ACC_BUS      0x1800
0087 #define CLK_CON_DIV_CLKCMU_APM_BUS      0x1804
0088 #define CLK_CON_DIV_CLKCMU_AUD_BUS      0x1808
0089 #define CLK_CON_DIV_CLKCMU_AUD_CPU      0x180c
0090 #define CLK_CON_DIV_CLKCMU_BUSC_BUS     0x1810
0091 #define CLK_CON_DIV_CLKCMU_BUSMC_BUS        0x1818
0092 #define CLK_CON_DIV_CLKCMU_CORE_BUS     0x181c
0093 #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER   0x1820
0094 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH    0x1828
0095 #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER   0x182c
0096 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH    0x1830
0097 #define CLK_CON_DIV_CLKCMU_DPTX_BUS     0x183c
0098 #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC       0x1840
0099 #define CLK_CON_DIV_CLKCMU_DPUM_BUS     0x1844
0100 #define CLK_CON_DIV_CLKCMU_DPUS0_BUS        0x1848
0101 #define CLK_CON_DIV_CLKCMU_DPUS1_BUS        0x184c
0102 #define CLK_CON_DIV_CLKCMU_FSYS0_BUS        0x1850
0103 #define CLK_CON_DIV_CLKCMU_FSYS0_PCIE       0x1854
0104 #define CLK_CON_DIV_CLKCMU_FSYS1_BUS        0x1858
0105 #define CLK_CON_DIV_CLKCMU_FSYS1_USBDRD     0x185c
0106 #define CLK_CON_DIV_CLKCMU_FSYS2_BUS        0x1860
0107 #define CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET   0x1864
0108 #define CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD   0x1868
0109 #define CLK_CON_DIV_CLKCMU_G2D_G2D      0x186c
0110 #define CLK_CON_DIV_CLKCMU_G2D_MSCL     0x1870
0111 #define CLK_CON_DIV_CLKCMU_G3D00_SWITCH     0x1874
0112 #define CLK_CON_DIV_CLKCMU_G3D01_SWITCH     0x1878
0113 #define CLK_CON_DIV_CLKCMU_G3D1_SWITCH      0x187c
0114 #define CLK_CON_DIV_CLKCMU_ISPB_BUS     0x1884
0115 #define CLK_CON_DIV_CLKCMU_MFC_MFC      0x1888
0116 #define CLK_CON_DIV_CLKCMU_MFC_WFD      0x188c
0117 #define CLK_CON_DIV_CLKCMU_MIF_BUSP     0x1890
0118 #define CLK_CON_DIV_CLKCMU_NPU_BUS      0x1894
0119 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS       0x1898
0120 #define CLK_CON_DIV_CLKCMU_PERIC0_IP        0x189c
0121 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS       0x18a0
0122 #define CLK_CON_DIV_CLKCMU_PERIC1_IP        0x18a4
0123 #define CLK_CON_DIV_CLKCMU_PERIS_BUS        0x18a8
0124 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST    0x18b4
0125
0126 #define CLK_CON_DIV_PLL_SHARED0_DIV2        0x18b8
0127 #define CLK_CON_DIV_PLL_SHARED0_DIV3        0x18bc
0128 #define CLK_CON_DIV_PLL_SHARED1_DIV2        0x18c0
0129 #define CLK_CON_DIV_PLL_SHARED1_DIV3        0x18c4
0130 #define CLK_CON_DIV_PLL_SHARED1_DIV4        0x18c8
0131 #define CLK_CON_DIV_PLL_SHARED2_DIV2        0x18cc
0132 #define CLK_CON_DIV_PLL_SHARED2_DIV3        0x18d0
0133 #define CLK_CON_DIV_PLL_SHARED2_DIV4        0x18d4
0134 #define CLK_CON_DIV_PLL_SHARED4_DIV2        0x18d4
0135 #define CLK_CON_DIV_PLL_SHARED4_DIV4        0x18d8
0136
0137 /* GATE */
0138 #define CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST   0x2000
0139 #define CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST  0x2004
0140 #define CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST   0x2008
0141 #define CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST 0x2010
0142 #define CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST 0x2018
0143 #define CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST    0x2020
0144 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD  0x2024
0145 #define CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH  0x2028
0146 #define CLK_CON_GAT_GATE_CLKCMU_ACC_BUS     0x202c
0147 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS     0x2030
0148 #define CLK_CON_GAT_GATE_CLKCMU_AUD_BUS     0x2034
0149 #define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU     0x2038
0150 #define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS    0x203c
0151 #define CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS   0x2044
0152 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST   0x2048
0153 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS    0x204c
0154 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER  0x2050
0155 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH   0x2058
0156 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER  0x205c
0157 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH   0x2060
0158 #define CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS    0x206c
0159 #define CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC  0x2070
0160 #define CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS    0x2060
0161 #define CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS   0x2064
0162 #define CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS   0x207c
0163 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS   0x2080
0164 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE  0x2084
0165 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS   0x2088
0166 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD    0x208c
0167 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS   0x2090
0168 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET  0x2094
0169 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD  0x2098
0170 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D     0x209c
0171 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL    0x20a0
0172 #define CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH    0x20a4
0173 #define CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH    0x20a8
0174 #define CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH 0x20ac
0175 #define CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS    0x20b4
0176 #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC     0x20b8
0177 #define CLK_CON_GAT_GATE_CLKCMU_MFC_WFD     0x20bc
0178 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP    0x20c0
0179 #define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS     0x20c4
0180 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS  0x20c8
0181 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP   0x20cc
0182 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS  0x20d0
0183 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP   0x20d4
0184 #define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS   0x20d8
0185
0186 static const unsigned long top_clk_regs[] __initconst = {
0187     PLL_LOCKTIME_PLL_SHARED0,
0188     PLL_LOCKTIME_PLL_SHARED1,
0189     PLL_LOCKTIME_PLL_SHARED2,
0190     PLL_LOCKTIME_PLL_SHARED3,
0191     PLL_LOCKTIME_PLL_SHARED4,
0192     PLL_CON0_PLL_SHARED0,
0193     PLL_CON3_PLL_SHARED0,
0194     PLL_CON0_PLL_SHARED1,
0195     PLL_CON3_PLL_SHARED1,
0196     PLL_CON0_PLL_SHARED2,
0197     PLL_CON3_PLL_SHARED2,
0198     PLL_CON0_PLL_SHARED3,
0199     PLL_CON3_PLL_SHARED3,
0200     PLL_CON0_PLL_SHARED4,
0201     PLL_CON3_PLL_SHARED4,
0202     CLK_CON_MUX_MUX_CLKCMU_ACC_BUS,
0203     CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
0204     CLK_CON_MUX_MUX_CLKCMU_AUD_BUS,
0205     CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
0206     CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS,
0207     CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
0208     CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
0209     CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER,
0210     CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
0211     CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER,
0212     CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
0213     CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS,
0214     CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC,
0215     CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS,
0216     CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS,
0217     CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS,
0218     CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS,
0219     CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE,
0220     CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS,
0221     CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD,
0222     CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD,
0223     CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS,
0224     CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET,
0225     CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD,
0226     CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
0227     CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
0228     CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH,
0229     CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH,
0230     CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH,
0231     CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS,
0232     CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
0233     CLK_CON_MUX_MUX_CLKCMU_MFC_WFD,
0234     CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
0235     CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
0236     CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
0237     CLK_CON_MUX_MUX_CLKCMU_NPU_BUS,
0238     CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
0239     CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
0240     CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
0241     CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
0242     CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS,
0243     CLK_CON_MUX_MUX_CMU_CMUREF,
0244     CLK_CON_DIV_CLKCMU_ACC_BUS,
0245     CLK_CON_DIV_CLKCMU_APM_BUS,
0246     CLK_CON_DIV_CLKCMU_AUD_BUS,
0247     CLK_CON_DIV_CLKCMU_AUD_CPU,
0248     CLK_CON_DIV_CLKCMU_BUSC_BUS,
0249     CLK_CON_DIV_CLKCMU_BUSMC_BUS,
0250     CLK_CON_DIV_CLKCMU_CORE_BUS,
0251     CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
0252     CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
0253     CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
0254     CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
0255     CLK_CON_DIV_CLKCMU_DPTX_BUS,
0256     CLK_CON_DIV_CLKCMU_DPTX_DPGTC,
0257     CLK_CON_DIV_CLKCMU_DPUM_BUS,
0258     CLK_CON_DIV_CLKCMU_DPUS0_BUS,
0259     CLK_CON_DIV_CLKCMU_DPUS1_BUS,
0260     CLK_CON_DIV_CLKCMU_FSYS0_BUS,
0261     CLK_CON_DIV_CLKCMU_FSYS0_PCIE,
0262     CLK_CON_DIV_CLKCMU_FSYS1_BUS,
0263     CLK_CON_DIV_CLKCMU_FSYS1_USBDRD,
0264     CLK_CON_DIV_CLKCMU_FSYS2_BUS,
0265     CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET,
0266     CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD,
0267     CLK_CON_DIV_CLKCMU_G2D_G2D,
0268     CLK_CON_DIV_CLKCMU_G2D_MSCL,
0269     CLK_CON_DIV_CLKCMU_G3D00_SWITCH,
0270     CLK_CON_DIV_CLKCMU_G3D01_SWITCH,
0271     CLK_CON_DIV_CLKCMU_G3D1_SWITCH,
0272     CLK_CON_DIV_CLKCMU_ISPB_BUS,
0273     CLK_CON_DIV_CLKCMU_MFC_MFC,
0274     CLK_CON_DIV_CLKCMU_MFC_WFD,
0275     CLK_CON_DIV_CLKCMU_MIF_BUSP,
0276     CLK_CON_DIV_CLKCMU_NPU_BUS,
0277     CLK_CON_DIV_CLKCMU_PERIC0_BUS,
0278     CLK_CON_DIV_CLKCMU_PERIC0_IP,
0279     CLK_CON_DIV_CLKCMU_PERIC1_BUS,
0280     CLK_CON_DIV_CLKCMU_PERIC1_IP,
0281     CLK_CON_DIV_CLKCMU_PERIS_BUS,
0282     CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
0283     CLK_CON_DIV_PLL_SHARED0_DIV2,
0284     CLK_CON_DIV_PLL_SHARED0_DIV3,
0285     CLK_CON_DIV_PLL_SHARED1_DIV2,
0286     CLK_CON_DIV_PLL_SHARED1_DIV3,
0287     CLK_CON_DIV_PLL_SHARED1_DIV4,
0288     CLK_CON_DIV_PLL_SHARED2_DIV2,
0289     CLK_CON_DIV_PLL_SHARED2_DIV3,
0290     CLK_CON_DIV_PLL_SHARED2_DIV4,
0291     CLK_CON_DIV_PLL_SHARED4_DIV2,
0292     CLK_CON_DIV_PLL_SHARED4_DIV4,
0293     CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST,
0294     CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST,
0295     CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST,
0296     CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST,
0297     CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST,
0298     CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST,
0299     CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD,
0300     CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH,
0301     CLK_CON_GAT_GATE_CLKCMU_ACC_BUS,
0302     CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
0303     CLK_CON_GAT_GATE_CLKCMU_AUD_BUS,
0304     CLK_CON_GAT_GATE_CLKCMU_AUD_CPU,
0305     CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS,
0306     CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS,
0307     CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
0308     CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
0309     CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER,
0310     CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
0311     CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER,
0312     CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
0313     CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS,
0314     CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC,
0315     CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS,
0316     CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS,
0317     CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS,
0318     CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,
0319     CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE,
0320     CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
0321     CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD,
0322     CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS,
0323     CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET,
0324     CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD,
0325     CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
0326     CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
0327     CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH,
0328     CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH,
0329     CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH,
0330     CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS,
0331     CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
0332     CLK_CON_GAT_GATE_CLKCMU_MFC_WFD,
0333     CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
0334     CLK_CON_GAT_GATE_CLKCMU_NPU_BUS,
0335     CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
0336     CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
0337     CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
0338     CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
0339     CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
0340 };
0341
0342 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
0343     /* CMU_TOP_PURECLKCOMP */
0344     PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
0345         PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
0346     PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared1_pll", "oscclk",
0347         PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
0348     PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared2_pll", "oscclk",
0349         PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
0350     PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared3_pll", "oscclk",
0351         PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
0352     PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared4_pll", "oscclk",
0353         PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
0354 };
0355
0356 /* List of parent clocks for Muxes in CMU_TOP */
0357 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
0358 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
0359 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
0360 PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
0361 PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
0362
0363 PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared2_div3", "dout_shared1_div4",
0364                    "dout_shared2_div4", "dout_shared4_div4" };
0365 PNAME(mout_clkcmu_cmu_cmuref_p) = { "oscclk", "dout_cmu_boost" };
0366 PNAME(mout_clkcmu_acc_bus_p) = { "dout_shared1_div3", "dout_shared2_div3",
0367                  "dout_shared1_div4", "dout_shared2_div4" };
0368 PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
0369                  "dout_shared2_div4", "dout_shared4_div4" };
0370 PNAME(mout_clkcmu_aud_cpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
0371                  "dout_shared2_div2", "dout_shared0_div3",
0372                  "dout_shared4_div2", "dout_shared1_div3",
0373                  "fout_shared3_pll" };
0374 PNAME(mout_clkcmu_aud_bus_p) = { "dout_shared4_div2", "dout_shared1_div3",
0375                   "dout_shared2_div3", "dout_shared1_div4" };
0376 PNAME(mout_clkcmu_busc_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
0377                   "dout_shared2_div4", "dout_shared4_div4" };
0378 PNAME(mout_clkcmu_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
0379                   "dout_shared2_div2", "dout_shared0_div3",
0380                   "dout_shared4_div2", "dout_shared1_div3",
0381                   "dout_shared2_div3", "fout_shared3_pll" };
0382 PNAME(mout_clkcmu_cpucl0_switch_p) = {
0383     "dout_shared0_div2", "dout_shared1_div2",
0384     "dout_shared2_div2", "dout_shared4_div2" };
0385 PNAME(mout_clkcmu_cpucl0_cluster_p) = {
0386     "fout_shared2_pll", "fout_shared4_pll",
0387     "dout_shared0_div2", "dout_shared1_div2",
0388     "dout_shared2_div2", "dout_shared4_div2",
0389     "dout_shared2_div3", "fout_shared3_pll" };
0390 PNAME(mout_clkcmu_dptx_bus_p) = { "dout_shared4_div2", "dout_shared2_div3",
0391                   "dout_shared1_div4", "dout_shared2_div4" };
0392 PNAME(mout_clkcmu_dptx_dpgtc_p) = { "oscclk", "dout_shared2_div3",
0393                     "dout_shared2_div4", "dout_shared4_div4" };
0394 PNAME(mout_clkcmu_dpum_bus_p) = { "dout_shared1_div3", "dout_shared2_div3",
0395                   "dout_shared1_div4", "dout_shared2_div4",
0396                   "dout_shared4_div4", "fout_shared3_pll" };
0397 PNAME(mout_clkcmu_fsys0_bus_p)  = {
0398     "dout_shared4_div2", "dout_shared2_div3",
0399     "dout_shared1_div4", "dout_shared2_div4" };
0400 PNAME(mout_clkcmu_fsys0_pcie_p) = { "oscclk", "dout_shared2_div4" };
0401 PNAME(mout_clkcmu_fsys1_bus_p)  = { "dout_shared2_div3", "dout_shared1_div4",
0402                     "dout_shared2_div4", "dout_shared4_div4" };
0403 PNAME(mout_clkcmu_fsys1_usbdrd_p) = {
0404     "oscclk", "dout_shared2_div3",
0405     "dout_shared2_div4", "dout_shared4_div4" };
0406 PNAME(mout_clkcmu_fsys1_mmc_card_p) = {
0407     "oscclk", "dout_shared2_div2",
0408     "dout_shared4_div2", "dout_shared2_div3" };
0409 PNAME(mout_clkcmu_fsys2_ethernet_p) = {
0410     "oscclk", "dout_shared2_div2",
0411     "dout_shared0_div3", "dout_shared2_div3",
0412     "dout_shared1_div4", "fout_shared3_pll" };
0413 PNAME(mout_clkcmu_g2d_g2d_p) = { "dout_shared2_div2", "dout_shared0_div3",
0414                  "dout_shared4_div2", "dout_shared1_div3",
0415                  "dout_shared2_div3", "dout_shared1_div4",
0416                  "dout_shared2_div4", "dout_shared4_div4" };
0417 PNAME(mout_clkcmu_g3d0_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
0418                      "dout_shared2_div2", "dout_shared4_div2" };
0419 PNAME(mout_clkcmu_g3d1_switch_p) = { "dout_shared2_div2", "dout_shared4_div2",
0420                      "dout_shared2_div3", "dout_shared1_div4" };
0421 PNAME(mout_clkcmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
0422                     "fout_shared2_pll", "fout_shared4_pll",
0423                     "dout_shared0_div2", "dout_shared1_div2",
0424                     "dout_shared2_div2", "fout_shared3_pll" };
0425 PNAME(mout_clkcmu_npu_bus_p) = { "dout_shared1_div2", "dout_shared2_div2",
0426                  "dout_shared0_div3", "dout_shared4_div2",
0427                  "dout_shared1_div3", "dout_shared2_div3",
0428                  "dout_shared1_div4", "fout_shared3_pll" };
0429 PNAME(mout_clkcmu_peric0_bus_p) = { "dout_shared2_div3", "dout_shared2_div4" };
0430
0431 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
0432     /* CMU_TOP_PURECLKCOMP */
0433     MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
0434         PLL_CON0_PLL_SHARED0, 4, 1),
0435     MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
0436         PLL_CON0_PLL_SHARED1, 4, 1),
0437     MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
0438         PLL_CON0_PLL_SHARED2, 4, 1),
0439     MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
0440         PLL_CON0_PLL_SHARED3, 4, 1),
0441     MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p,
0442         PLL_CON0_PLL_SHARED4, 4, 1),
0443
0444     /* BOOST */
0445     MUX(MOUT_CLKCMU_CMU_BOOST, "mout_clkcmu_cmu_boost",
0446         mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
0447     MUX(MOUT_CLKCMU_CMU_CMUREF, "mout_clkcmu_cmu_cmuref",
0448         mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
0449
0450     /* ACC */
0451     MUX(MOUT_CLKCMU_ACC_BUS, "mout_clkcmu_acc_bus", mout_clkcmu_acc_bus_p,
0452         CLK_CON_MUX_MUX_CLKCMU_ACC_BUS, 0, 2),
0453
0454     /* APM */
0455     MUX(MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", mout_clkcmu_apm_bus_p,
0456         CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 2),
0457
0458     /* AUD */
0459     MUX(MOUT_CLKCMU_AUD_CPU, "mout_clkcmu_aud_cpu", mout_clkcmu_aud_cpu_p,
0460         CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
0461     MUX(MOUT_CLKCMU_AUD_BUS, "mout_clkcmu_aud_bus", mout_clkcmu_aud_bus_p,
0462         CLK_CON_MUX_MUX_CLKCMU_AUD_BUS, 0, 2),
0463
0464     /* BUSC */
0465     MUX(MOUT_CLKCMU_BUSC_BUS, "mout_clkcmu_busc_bus",
0466         mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 0, 2),
0467
0468     /* BUSMC */
0469     MUX(MOUT_CLKCMU_BUSMC_BUS, "mout_clkcmu_busmc_bus",
0470         mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS, 0, 2),
0471
0472     /* CORE */
0473     MUX(MOUT_CLKCMU_CORE_BUS, "mout_clkcmu_core_bus",
0474         mout_clkcmu_core_bus_p, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
0475
0476     /* CPUCL0 */
0477     MUX(MOUT_CLKCMU_CPUCL0_SWITCH, "mout_clkcmu_cpucl0_switch",
0478         mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
0479         0, 2),
0480     MUX(MOUT_CLKCMU_CPUCL0_CLUSTER, "mout_clkcmu_cpucl0_cluster",
0481         mout_clkcmu_cpucl0_cluster_p,
0482         CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER, 0, 3),
0483
0484     /* CPUCL1 */
0485     MUX(MOUT_CLKCMU_CPUCL1_SWITCH, "mout_clkcmu_cpucl1_switch",
0486         mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
0487         0, 2),
0488     MUX(MOUT_CLKCMU_CPUCL1_CLUSTER, "mout_clkcmu_cpucl1_cluster",
0489         mout_clkcmu_cpucl0_cluster_p,
0490         CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER, 0, 3),
0491
0492     /* DPTX */
0493     MUX(MOUT_CLKCMU_DPTX_BUS, "mout_clkcmu_dptx_bus",
0494         mout_clkcmu_dptx_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS, 0, 2),
0495     MUX(MOUT_CLKCMU_DPTX_DPGTC, "mout_clkcmu_dptx_dpgtc",
0496         mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2),
0497
0498     /* DPUM */
0499     MUX(MOUT_CLKCMU_DPUM_BUS, "mout_clkcmu_dpum_bus",
0500         mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS, 0, 3),
0501
0502     /* DPUS */
0503     MUX(MOUT_CLKCMU_DPUS0_BUS, "mout_clkcmu_dpus0_bus",
0504         mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS, 0, 3),
0505     MUX(MOUT_CLKCMU_DPUS1_BUS, "mout_clkcmu_dpus1_bus",
0506         mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS, 0, 3),
0507
0508     /* FSYS0 */
0509     MUX(MOUT_CLKCMU_FSYS0_BUS, "mout_clkcmu_fsys0_bus",
0510         mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, 0, 2),
0511     MUX(MOUT_CLKCMU_FSYS0_PCIE, "mout_clkcmu_fsys0_pcie",
0512         mout_clkcmu_fsys0_pcie_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE, 0, 1),
0513
0514     /* FSYS1 */
0515     MUX(MOUT_CLKCMU_FSYS1_BUS, "mout_clkcmu_fsys1_bus",
0516         mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, 0, 2),
0517     MUX(MOUT_CLKCMU_FSYS1_USBDRD, "mout_clkcmu_fsys1_usbdrd",
0518         mout_clkcmu_fsys1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD,
0519         0, 2),
0520     MUX(MOUT_CLKCMU_FSYS1_MMC_CARD, "mout_clkcmu_fsys1_mmc_card",
0521         mout_clkcmu_fsys1_mmc_card_p,
0522         CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD, 0, 2),
0523
0524     /* FSYS2 */
0525     MUX(MOUT_CLKCMU_FSYS2_BUS, "mout_clkcmu_fsys2_bus",
0526         mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS, 0, 2),
0527     MUX(MOUT_CLKCMU_FSYS2_UFS_EMBD, "mout_clkcmu_fsys2_ufs_embd",
0528         mout_clkcmu_fsys1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD,
0529         0, 2),
0530     MUX(MOUT_CLKCMU_FSYS2_ETHERNET, "mout_clkcmu_fsys2_ethernet",
0531         mout_clkcmu_fsys2_ethernet_p,
0532         CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET, 0, 3),
0533
0534     /* G2D */
0535     MUX(MOUT_CLKCMU_G2D_G2D, "mout_clkcmu_g2d_g2d", mout_clkcmu_g2d_g2d_p,
0536         CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3),
0537     MUX(MOUT_CLKCMU_G2D_MSCL, "mout_clkcmu_g2d_mscl",
0538         mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
0539
0540     /* G3D0 */
0541     MUX(MOUT_CLKCMU_G3D00_SWITCH, "mout_clkcmu_g3d00_switch",
0542         mout_clkcmu_g3d0_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH,
0543         0, 2),
0544     MUX(MOUT_CLKCMU_G3D01_SWITCH, "mout_clkcmu_g3d01_switch",
0545         mout_clkcmu_g3d0_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH,
0546         0, 2),
0547
0548     /* G3D1 */
0549     MUX(MOUT_CLKCMU_G3D1_SWITCH, "mout_clkcmu_g3d1_switch",
0550         mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH,
0551         0, 2),
0552
0553     /* ISPB */
0554     MUX(MOUT_CLKCMU_ISPB_BUS, "mout_clkcmu_ispb_bus",
0555         mout_clkcmu_acc_bus_p, CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS, 0, 2),
0556
0557     /* MFC */
0558     MUX(MOUT_CLKCMU_MFC_MFC, "mout_clkcmu_mfc_mfc",
0559         mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
0560     MUX(MOUT_CLKCMU_MFC_WFD, "mout_clkcmu_mfc_wfd",
0561         mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
0562
0563     /* MIF */
0564     MUX(MOUT_CLKCMU_MIF_SWITCH, "mout_clkcmu_mif_switch",
0565         mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
0566     MUX(MOUT_CLKCMU_MIF_BUSP, "mout_clkcmu_mif_busp",
0567         mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
0568
0569     /* NPU */
0570     MUX(MOUT_CLKCMU_NPU_BUS, "mout_clkcmu_npu_bus", mout_clkcmu_npu_bus_p,
0571         CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0, 3),
0572
0573     /* PERIC0 */
0574     MUX(MOUT_CLKCMU_PERIC0_BUS, "mout_clkcmu_peric0_bus",
0575         mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
0576     MUX(MOUT_CLKCMU_PERIC0_IP, "mout_clkcmu_peric0_ip",
0577         mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
0578
0579     /* PERIC1 */
0580     MUX(MOUT_CLKCMU_PERIC1_BUS, "mout_clkcmu_peric1_bus",
0581         mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
0582     MUX(MOUT_CLKCMU_PERIC1_IP, "mout_clkcmu_peric1_ip",
0583         mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
0584
0585     /* PERIS */
0586     MUX(MOUT_CLKCMU_PERIS_BUS, "mout_clkcmu_peris_bus",
0587         mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
0588 };
0589
0590 static const struct samsung_div_clock top_div_clks[] __initconst = {
0591     /* CMU_TOP_PURECLKCOMP */
0592     DIV(DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
0593         CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
0594     DIV(DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
0595         CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
0596
0597     DIV(DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
0598         CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
0599     DIV(DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
0600         CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
0601     DIV(DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
0602         CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
0603
0604     DIV(DOUT_SHARED2_DIV3, "dout_shared2_div3", "mout_shared2_pll",
0605         CLK_CON_DIV_PLL_SHARED2_DIV3, 0, 2),
0606     DIV(DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
0607         CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
0608     DIV(DOUT_SHARED2_DIV4, "dout_shared2_div4", "dout_shared2_div2",
0609         CLK_CON_DIV_PLL_SHARED2_DIV4, 0, 1),
0610
0611     DIV(DOUT_SHARED4_DIV2, "dout_shared4_div2", "mout_shared4_pll",
0612         CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
0613     DIV(DOUT_SHARED4_DIV4, "dout_shared4_div4", "dout_shared4_div2",
0614         CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
0615
0616     /* BOOST */
0617     DIV(DOUT_CLKCMU_CMU_BOOST, "dout_clkcmu_cmu_boost",
0618         "gout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
0619
0620     /* ACC */
0621     DIV(DOUT_CLKCMU_ACC_BUS, "dout_clkcmu_acc_bus", "gout_clkcmu_acc_bus",
0622         CLK_CON_DIV_CLKCMU_ACC_BUS, 0, 4),
0623
0624     /* APM */
0625     DIV(DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", "gout_clkcmu_apm_bus",
0626         CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
0627
0628     /* AUD */
0629     DIV(DOUT_CLKCMU_AUD_CPU, "dout_clkcmu_aud_cpu", "gout_clkcmu_aud_cpu",
0630         CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
0631     DIV(DOUT_CLKCMU_AUD_BUS, "dout_clkcmu_aud_bus", "gout_clkcmu_aud_bus",
0632         CLK_CON_DIV_CLKCMU_AUD_BUS, 0, 4),
0633
0634     /* BUSC */
0635     DIV(DOUT_CLKCMU_BUSC_BUS, "dout_clkcmu_busc_bus",
0636         "gout_clkcmu_busc_bus", CLK_CON_DIV_CLKCMU_BUSC_BUS, 0, 4),
0637
0638     /* BUSMC */
0639     DIV(DOUT_CLKCMU_BUSMC_BUS, "dout_clkcmu_busmc_bus",
0640         "gout_clkcmu_busmc_bus", CLK_CON_DIV_CLKCMU_BUSMC_BUS, 0, 4),
0641
0642     /* CORE */
0643     DIV(DOUT_CLKCMU_CORE_BUS, "dout_clkcmu_core_bus",
0644         "gout_clkcmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
0645
0646     /* CPUCL0 */
0647     DIV(DOUT_CLKCMU_CPUCL0_SWITCH, "dout_clkcmu_cpucl0_switch",
0648         "gout_clkcmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
0649         0, 3),
0650     DIV(DOUT_CLKCMU_CPUCL0_CLUSTER, "dout_clkcmu_cpucl0_cluster",
0651         "gout_clkcmu_cpucl0_cluster", CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
0652         0, 3),
0653
0654     /* CPUCL1 */
0655     DIV(DOUT_CLKCMU_CPUCL1_SWITCH, "dout_clkcmu_cpucl1_switch",
0656         "gout_clkcmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
0657         0, 3),
0658     DIV(DOUT_CLKCMU_CPUCL1_CLUSTER, "dout_clkcmu_cpucl1_cluster",
0659         "gout_clkcmu_cpucl1_cluster", CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
0660         0, 3),
0661
0662     /* DPTX */
0663     DIV(DOUT_CLKCMU_DPTX_BUS, "dout_clkcmu_dptx_bus",
0664         "gout_clkcmu_dptx_bus", CLK_CON_DIV_CLKCMU_DPTX_BUS, 0, 4),
0665     DIV(DOUT_CLKCMU_DPTX_DPGTC, "dout_clkcmu_dptx_dpgtc",
0666         "gout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
0667
0668     /* DPUM */
0669     DIV(DOUT_CLKCMU_DPUM_BUS, "dout_clkcmu_dpum_bus",
0670         "gout_clkcmu_dpum_bus", CLK_CON_DIV_CLKCMU_DPUM_BUS, 0, 4),
0671
0672     /* DPUS */
0673     DIV(DOUT_CLKCMU_DPUS0_BUS, "dout_clkcmu_dpus0_bus",
0674         "gout_clkcmu_dpus0_bus", CLK_CON_DIV_CLKCMU_DPUS0_BUS, 0, 4),
0675     DIV(DOUT_CLKCMU_DPUS1_BUS, "dout_clkcmu_dpus1_bus",
0676         "gout_clkcmu_dpus1_bus", CLK_CON_DIV_CLKCMU_DPUS1_BUS, 0, 4),
0677
0678     /* FSYS0 */
0679     DIV(DOUT_CLKCMU_FSYS0_BUS, "dout_clkcmu_fsys0_bus",
0680         "gout_clkcmu_fsys0_bus", CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0, 4),
0681
0682     /* FSYS1 */
0683     DIV(DOUT_CLKCMU_FSYS1_BUS, "dout_clkcmu_fsys1_bus",
0684         "gout_clkcmu_fsys1_bus", CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0, 4),
0685     DIV(DOUT_CLKCMU_FSYS1_USBDRD, "dout_clkcmu_fsys1_usbdrd",
0686         "gout_clkcmu_fsys1_usbdrd", CLK_CON_DIV_CLKCMU_FSYS1_USBDRD, 0, 4),
0687
0688     /* FSYS2 */
0689     DIV(DOUT_CLKCMU_FSYS2_BUS, "dout_clkcmu_fsys2_bus",
0690         "gout_clkcmu_fsys2_bus", CLK_CON_DIV_CLKCMU_FSYS2_BUS, 0, 4),
0691     DIV(DOUT_CLKCMU_FSYS2_UFS_EMBD, "dout_clkcmu_fsys2_ufs_embd",
0692         "gout_clkcmu_fsys2_ufs_embd", CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD,
0693         0, 3),
0694     DIV(DOUT_CLKCMU_FSYS2_ETHERNET, "dout_clkcmu_fsys2_ethernet",
0695         "gout_clkcmu_fsys2_ethernet", CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET,
0696         0, 3),
0697
0698     /* G2D */
0699     DIV(DOUT_CLKCMU_G2D_G2D, "dout_clkcmu_g2d_g2d", "gout_clkcmu_g2d_g2d",
0700         CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
0701     DIV(DOUT_CLKCMU_G2D_MSCL, "dout_clkcmu_g2d_mscl",
0702         "gout_clkcmu_g2d_mscl", CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
0703
0704     /* G3D0 */
0705     DIV(DOUT_CLKCMU_G3D00_SWITCH, "dout_clkcmu_g3d00_switch",
0706         "gout_clkcmu_g3d00_switch", CLK_CON_DIV_CLKCMU_G3D00_SWITCH, 0, 3),
0707     DIV(DOUT_CLKCMU_G3D01_SWITCH, "dout_clkcmu_g3d01_switch",
0708         "gout_clkcmu_g3d01_switch", CLK_CON_DIV_CLKCMU_G3D01_SWITCH, 0, 3),
0709
0710     /* G3D1 */
0711     DIV(DOUT_CLKCMU_G3D1_SWITCH, "dout_clkcmu_g3d1_switch",
0712         "gout_clkcmu_g3d1_switch", CLK_CON_DIV_CLKCMU_G3D1_SWITCH, 0, 3),
0713
0714     /* ISPB */
0715     DIV(DOUT_CLKCMU_ISPB_BUS, "dout_clkcmu_ispb_bus",
0716         "gout_clkcmu_ispb_bus", CLK_CON_DIV_CLKCMU_ISPB_BUS, 0, 4),
0717
0718     /* MFC */
0719     DIV(DOUT_CLKCMU_MFC_MFC, "dout_clkcmu_mfc_mfc", "gout_clkcmu_mfc_mfc",
0720         CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
0721     DIV(DOUT_CLKCMU_MFC_WFD, "dout_clkcmu_mfc_wfd", "gout_clkcmu_mfc_wfd",
0722         CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
0723
0724     /* MIF */
0725     DIV(DOUT_CLKCMU_MIF_BUSP, "dout_clkcmu_mif_busp",
0726         "gout_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
0727
0728     /* NPU */
0729     DIV(DOUT_CLKCMU_NPU_BUS, "dout_clkcmu_npu_bus", "gout_clkcmu_npu_bus",
0730         CLK_CON_DIV_CLKCMU_NPU_BUS, 0, 4),
0731
0732     /* PERIC0 */
0733     DIV(DOUT_CLKCMU_PERIC0_BUS, "dout_clkcmu_peric0_bus",
0734         "gout_clkcmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
0735     DIV(DOUT_CLKCMU_PERIC0_IP, "dout_clkcmu_peric0_ip",
0736         "gout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
0737
0738     /* PERIC1 */
0739     DIV(DOUT_CLKCMU_PERIC1_BUS, "dout_clkcmu_peric1_bus",
0740         "gout_clkcmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
0741     DIV(DOUT_CLKCMU_PERIC1_IP, "dout_clkcmu_peric1_ip",
0742         "gout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
0743
0744     /* PERIS */
0745     DIV(DOUT_CLKCMU_PERIS_BUS, "dout_clkcmu_peris_bus",
0746         "gout_clkcmu_peris_bus", CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
0747 };
0748
0749 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
0750     FFACTOR(DOUT_CLKCMU_FSYS0_PCIE, "dout_clkcmu_fsys0_pcie",
0751         "gout_clkcmu_fsys0_pcie", 1, 4, 0),
0752 };
0753
0754 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
0755     /* BOOST */
0756     GATE(GOUT_CLKCMU_CMU_BOOST, "gout_clkcmu_cmu_boost",
0757          "mout_clkcmu_cmu_boost", CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
0758          21, 0, 0),
0759
0760     GATE(GOUT_CLKCMU_CPUCL0_BOOST, "gout_clkcmu_cpucl0_boost",
0761          "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST, 21, 0, 0),
0762     GATE(GOUT_CLKCMU_CPUCL1_BOOST, "gout_clkcmu_cpucl1_boost",
0763          "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST, 21, 0, 0),
0764     GATE(GOUT_CLKCMU_CORE_BOOST, "gout_clkcmu_core_boost",
0765          "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST, 21, 0, 0),
0766     GATE(GOUT_CLKCMU_BUSC_BOOST, "gout_clkcmu_busc_boost",
0767          "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST, 21, 0, 0),
0768
0769     GATE(GOUT_CLKCMU_BUSMC_BOOST, "gout_clkcmu_busmc_boost",
0770          "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST, 21, 0, 0),
0771     GATE(GOUT_CLKCMU_MIF_BOOST, "gout_clkcmu_mif_boost", "dout_cmu_boost",
0772          CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST, 21, 0, 0),
0773
0774     /* ACC */
0775     GATE(GOUT_CLKCMU_ACC_BUS, "gout_clkcmu_acc_bus", "mout_clkcmu_acc_bus",
0776          CLK_CON_GAT_GATE_CLKCMU_ACC_BUS, 21, 0, 0),
0777
0778     /* APM */
0779     GATE(GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", "mout_clkcmu_apm_bus",
0780          CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
0781
0782     /* AUD */
0783     GATE(GOUT_CLKCMU_AUD_CPU, "gout_clkcmu_aud_cpu", "mout_clkcmu_aud_cpu",
0784          CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 21, 0, 0),
0785     GATE(GOUT_CLKCMU_AUD_BUS, "gout_clkcmu_aud_bus", "mout_clkcmu_aud_bus",
0786          CLK_CON_GAT_GATE_CLKCMU_AUD_BUS, 21, 0, 0),
0787
0788     /* BUSC */
0789     GATE(GOUT_CLKCMU_BUSC_BUS, "gout_clkcmu_busc_bus",
0790          "mout_clkcmu_busc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, 21,
0791          CLK_IS_CRITICAL, 0),
0792
0793     /* BUSMC */
0794     GATE(GOUT_CLKCMU_BUSMC_BUS, "gout_clkcmu_busmc_bus",
0795          "mout_clkcmu_busmc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS, 21,
0796          CLK_IS_CRITICAL, 0),
0797
0798     /* CORE */
0799     GATE(GOUT_CLKCMU_CORE_BUS, "gout_clkcmu_core_bus",
0800          "mout_clkcmu_core_bus", CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
0801          21, 0, 0),
0802
0803     /* CPUCL0 */
0804     GATE(GOUT_CLKCMU_CPUCL0_SWITCH, "gout_clkcmu_cpucl0_switch",
0805          "mout_clkcmu_cpucl0_switch",
0806          CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
0807     GATE(GOUT_CLKCMU_CPUCL0_CLUSTER, "gout_clkcmu_cpucl0_cluster",
0808          "mout_clkcmu_cpucl0_cluster",
0809          CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
0810
0811     /* CPUCL1 */
0812     GATE(GOUT_CLKCMU_CPUCL1_SWITCH, "gout_clkcmu_cpucl1_switch",
0813          "mout_clkcmu_cpucl1_switch",
0814          CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
0815     GATE(GOUT_CLKCMU_CPUCL1_CLUSTER, "gout_clkcmu_cpucl1_cluster",
0816          "mout_clkcmu_cpucl1_cluster",
0817          CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
0818
0819     /* DPTX */
0820     GATE(GOUT_CLKCMU_DPTX_BUS, "gout_clkcmu_dptx_bus",
0821          "mout_clkcmu_dptx_bus", CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS,
0822          21, 0, 0),
0823     GATE(GOUT_CLKCMU_DPTX_DPGTC, "gout_clkcmu_dptx_dpgtc",
0824          "mout_clkcmu_dptx_dpgtc", CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC,
0825          21, 0, 0),
0826
0827     /* DPUM */
0828     GATE(GOUT_CLKCMU_DPUM_BUS, "gout_clkcmu_dpum_bus",
0829          "mout_clkcmu_dpum_bus", CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS,
0830          21, 0, 0),
0831
0832     /* DPUS */
0833     GATE(GOUT_CLKCMU_DPUS0_BUS, "gout_clkcmu_dpus0_bus",
0834          "mout_clkcmu_dpus0_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS,
0835          21, 0, 0),
0836     GATE(GOUT_CLKCMU_DPUS1_BUS, "gout_clkcmu_dpus1_bus",
0837          "mout_clkcmu_dpus1_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS,
0838          21, 0, 0),
0839
0840     /* FSYS0 */
0841     GATE(GOUT_CLKCMU_FSYS0_BUS, "gout_clkcmu_fsys0_bus",
0842          "mout_clkcmu_fsys0_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,
0843          21, 0, 0),
0844     GATE(GOUT_CLKCMU_FSYS0_PCIE, "gout_clkcmu_fsys0_pcie",
0845          "mout_clkcmu_fsys0_pcie", CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE,
0846          21, 0, 0),
0847
0848     /* FSYS1 */
0849     GATE(GOUT_CLKCMU_FSYS1_BUS, "gout_clkcmu_fsys1_bus",
0850          "mout_clkcmu_fsys1_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
0851          21, 0, 0),
0852     GATE(GOUT_CLKCMU_FSYS1_USBDRD, "gout_clkcmu_fsys1_usbdrd",
0853          "mout_clkcmu_fsys1_usbdrd", CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD,
0854          21, 0, 0),
0855     GATE(GOUT_CLKCMU_FSYS1_MMC_CARD, "gout_clkcmu_fsys1_mmc_card",
0856          "mout_clkcmu_fsys1_mmc_card",
0857          CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD, 21, 0, 0),
0858
0859     /* FSYS2 */
0860     GATE(GOUT_CLKCMU_FSYS2_BUS, "gout_clkcmu_fsys2_bus",
0861          "mout_clkcmu_fsys2_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS,
0862          21, 0, 0),
0863     GATE(GOUT_CLKCMU_FSYS2_UFS_EMBD, "gout_clkcmu_fsys2_ufs_embd",
0864          "mout_clkcmu_fsys2_ufs_embd",
0865          CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD, 21, 0, 0),
0866     GATE(GOUT_CLKCMU_FSYS2_ETHERNET, "gout_clkcmu_fsys2_ethernet",
0867          "mout_clkcmu_fsys2_ethernet",
0868          CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET, 21, 0, 0),
0869
0870     /* G2D */
0871     GATE(GOUT_CLKCMU_G2D_G2D, "gout_clkcmu_g2d_g2d",
0872          "mout_clkcmu_g2d_g2d", CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
0873     GATE(GOUT_CLKCMU_G2D_MSCL, "gout_clkcmu_g2d_mscl",
0874          "mout_clkcmu_g2d_mscl", CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
0875          21, 0, 0),
0876
0877     /* G3D0 */
0878     GATE(GOUT_CLKCMU_G3D00_SWITCH, "gout_clkcmu_g3d00_switch",
0879          "mout_clkcmu_g3d00_switch", CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH,
0880          21, 0, 0),
0881     GATE(GOUT_CLKCMU_G3D01_SWITCH, "gout_clkcmu_g3d01_switch",
0882          "mout_clkcmu_g3d01_switch", CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH,
0883          21, 0, 0),
0884
0885     /* G3D1 */
0886     GATE(GOUT_CLKCMU_G3D1_SWITCH, "gout_clkcmu_g3d1_switch",
0887          "mout_clkcmu_g3d1_switch", CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH,
0888          21, 0, 0),
0889
0890     /* ISPB */
0891     GATE(GOUT_CLKCMU_ISPB_BUS, "gout_clkcmu_ispb_bus",
0892          "mout_clkcmu_ispb_bus", CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS,
0893          21, 0, 0),
0894
0895     /* MFC */
0896     GATE(GOUT_CLKCMU_MFC_MFC, "gout_clkcmu_mfc_mfc", "mout_clkcmu_mfc_mfc",
0897          CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
0898     GATE(GOUT_CLKCMU_MFC_WFD, "gout_clkcmu_mfc_wfd", "mout_clkcmu_mfc_wfd",
0899          CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 21, 0, 0),
0900
0901     /* MIF */
0902     GATE(GOUT_CLKCMU_MIF_SWITCH, "gout_clkcmu_mif_switch",
0903          "mout_clkcmu_mif_switch", CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH,
0904          21, CLK_IGNORE_UNUSED, 0),
0905     GATE(GOUT_CLKCMU_MIF_BUSP, "gout_clkcmu_mif_busp",
0906          "mout_clkcmu_mif_busp", CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
0907          21, CLK_IGNORE_UNUSED, 0),
0908
0909     /* NPU */
0910     GATE(GOUT_CLKCMU_NPU_BUS, "gout_clkcmu_npu_bus", "mout_clkcmu_npu_bus",
0911          CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 21, 0, 0),
0912
0913     /* PERIC0 */
0914     GATE(GOUT_CLKCMU_PERIC0_BUS, "gout_clkcmu_peric0_bus",
0915          "mout_clkcmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
0916          21, 0, 0),
0917     GATE(GOUT_CLKCMU_PERIC0_IP, "gout_clkcmu_peric0_ip",
0918          "mout_clkcmu_peric0_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
0919          21, 0, 0),
0920
0921     /* PERIC1 */
0922     GATE(GOUT_CLKCMU_PERIC1_BUS, "gout_clkcmu_peric1_bus",
0923          "mout_clkcmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
0924          21, 0, 0),
0925     GATE(GOUT_CLKCMU_PERIC1_IP, "gout_clkcmu_peric1_ip",
0926          "mout_clkcmu_peric1_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
0927          21, 0, 0),
0928
0929     /* PERIS */
0930     GATE(GOUT_CLKCMU_PERIS_BUS, "gout_clkcmu_peris_bus",
0931          "mout_clkcmu_peris_bus", CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
0932          21, CLK_IGNORE_UNUSED, 0),
0933 };
0934
0935 static const struct samsung_cmu_info top_cmu_info __initconst = {
0936     .pll_clks       = top_pll_clks,
0937     .nr_pll_clks        = ARRAY_SIZE(top_pll_clks),
0938     .mux_clks       = top_mux_clks,
0939     .nr_mux_clks        = ARRAY_SIZE(top_mux_clks),
0940     .div_clks       = top_div_clks,
0941     .nr_div_clks        = ARRAY_SIZE(top_div_clks),
0942     .fixed_factor_clks  = top_fixed_factor_clks,
0943     .nr_fixed_factor_clks   = ARRAY_SIZE(top_fixed_factor_clks),
0944     .gate_clks      = top_gate_clks,
0945     .nr_gate_clks       = ARRAY_SIZE(top_gate_clks),
0946     .nr_clk_ids     = TOP_NR_CLK,
0947     .clk_regs       = top_clk_regs,
0948     .nr_clk_regs        = ARRAY_SIZE(top_clk_regs),
0949 };
0950
0951 static void __init exynosautov9_cmu_top_init(struct device_node *np)
0952 {
0953     exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
0954 }
0955
0956 /* Register CMU_TOP early, as it's a dependency for other early domains */
0957 CLK_OF_DECLARE(exynosautov9_cmu_top, "samsung,exynosautov9-cmu-top",
0958            exynosautov9_cmu_top_init);
0959
0960 /* ---- CMU_BUSMC ---------------------------------------------------------- */
0961
0962 /* Register Offset definitions for CMU_BUSMC (0x1b200000) */
0963 #define PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER              0x0600
0964 #define CLK_CON_DIV_DIV_CLK_BUSMC_BUSP                  0x1800
0965 #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK      0x2078
0966 #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK      0x2080
0967
0968 static const unsigned long busmc_clk_regs[] __initconst = {
0969     PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER,
0970     CLK_CON_DIV_DIV_CLK_BUSMC_BUSP,
0971     CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK,
0972     CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK,
0973 };
0974
0975 /* List of parent clocks for Muxes in CMU_BUSMC */
0976 PNAME(mout_busmc_bus_user_p) = { "oscclk", "dout_clkcmu_busmc_bus" };
0977
0978 static const struct samsung_mux_clock busmc_mux_clks[] __initconst = {
0979     MUX(CLK_MOUT_BUSMC_BUS_USER, "mout_busmc_bus_user",
0980         mout_busmc_bus_user_p, PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER, 4, 1),
0981 };
0982
0983 static const struct samsung_div_clock busmc_div_clks[] __initconst = {
0984     DIV(CLK_DOUT_BUSMC_BUSP, "dout_busmc_busp", "mout_busmc_bus_user",
0985         CLK_CON_DIV_DIV_CLK_BUSMC_BUSP, 0, 3),
0986 };
0987
0988 static const struct samsung_gate_clock busmc_gate_clks[] __initconst = {
0989     GATE(CLK_GOUT_BUSMC_PDMA0_PCLK, "gout_busmc_pdma0_pclk",
0990          "dout_busmc_busp",
0991          CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK, 21,
0992          0, 0),
0993     GATE(CLK_GOUT_BUSMC_SPDMA_PCLK, "gout_busmc_spdma_pclk",
0994          "dout_busmc_busp",
0995          CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK, 21,
0996          0, 0),
0997 };
0998
0999 static const struct samsung_cmu_info busmc_cmu_info __initconst = {
1000     .mux_clks       = busmc_mux_clks,
1001     .nr_mux_clks        = ARRAY_SIZE(busmc_mux_clks),
1002     .div_clks       = busmc_div_clks,
1003     .nr_div_clks        = ARRAY_SIZE(busmc_div_clks),
1004     .gate_clks      = busmc_gate_clks,
1005     .nr_gate_clks       = ARRAY_SIZE(busmc_gate_clks),
1006     .nr_clk_ids     = BUSMC_NR_CLK,
1007     .clk_regs       = busmc_clk_regs,
1008     .nr_clk_regs        = ARRAY_SIZE(busmc_clk_regs),
1009     .clk_name       = "dout_clkcmu_busmc_bus",
1010 };
1011
1012 /* ---- CMU_CORE ----------------------------------------------------------- */
1013
1014 /* Register Offset definitions for CMU_CORE (0x1b030000) */
1015 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER               0x0600
1016 #define CLK_CON_MUX_MUX_CORE_CMUREF                 0x1000
1017 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP                   0x1800
1018 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK          0x2000
1019 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK         0x2004
1020 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK   0x2008
1021
1022 static const unsigned long core_clk_regs[] __initconst = {
1023     PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
1024     CLK_CON_MUX_MUX_CORE_CMUREF,
1025     CLK_CON_DIV_DIV_CLK_CORE_BUSP,
1026     CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK,
1027     CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK,
1028     CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK,
1029 };
1030
1031 /* List of parent clocks for Muxes in CMU_CORE */
1032 PNAME(mout_core_bus_user_p) = { "oscclk", "dout_clkcmu_core_bus" };
1033
1034 static const struct samsung_mux_clock core_mux_clks[] __initconst = {
1035     MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
1036         PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
1037 };
1038
1039 static const struct samsung_div_clock core_div_clks[] __initconst = {
1040     DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
1041         CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 3),
1042 };
1043
1044 static const struct samsung_gate_clock core_gate_clks[] __initconst = {
1045     GATE(CLK_GOUT_CORE_CCI_CLK, "gout_core_cci_clk", "mout_core_bus_user",
1046          CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK, 21,
1047          CLK_IS_CRITICAL, 0),
1048     GATE(CLK_GOUT_CORE_CCI_PCLK, "gout_core_cci_pclk", "dout_core_busp",
1049          CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK, 21,
1050          CLK_IS_CRITICAL, 0),
1051     GATE(CLK_GOUT_CORE_CMU_CORE_PCLK, "gout_core_cmu_core_pclk",
1052          "dout_core_busp",
1053          CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, 21,
1054          CLK_IS_CRITICAL, 0),
1055 };
1056
1057 static const struct samsung_cmu_info core_cmu_info __initconst = {
1058     .mux_clks       = core_mux_clks,
1059     .nr_mux_clks        = ARRAY_SIZE(core_mux_clks),
1060     .div_clks       = core_div_clks,
1061     .nr_div_clks        = ARRAY_SIZE(core_div_clks),
1062     .gate_clks      = core_gate_clks,
1063     .nr_gate_clks       = ARRAY_SIZE(core_gate_clks),
1064     .nr_clk_ids     = CORE_NR_CLK,
1065     .clk_regs       = core_clk_regs,
1066     .nr_clk_regs        = ARRAY_SIZE(core_clk_regs),
1067     .clk_name       = "dout_clkcmu_core_bus",
1068 };
1069
1070 /* ---- CMU_FSYS2 ---------------------------------------------------------- */
1071
1072 /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
1073 #define PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER  0x0600
1074 #define PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER 0x0620
1075 #define PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER 0x0610
1076 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK   0x2098
1077 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO 0x209c
1078 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK   0x20a4
1079 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO 0x20a8
1080
1081 static const unsigned long fsys2_clk_regs[] __initconst = {
1082     PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER,
1083     PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER,
1084     PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER,
1085     CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK,
1086     CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO,
1087     CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK,
1088     CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO,
1089 };
1090
1091 /* List of parent clocks for Muxes in CMU_FSYS2 */
1092 PNAME(mout_fsys2_bus_user_p) = { "oscclk", "dout_clkcmu_fsys2_bus" };
1093 PNAME(mout_fsys2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_fsys2_ufs_embd" };
1094 PNAME(mout_fsys2_ethernet_user_p) = { "oscclk", "dout_clkcmu_fsys2_ethernet" };
1095
1096 static const struct samsung_mux_clock fsys2_mux_clks[] __initconst = {
1097     MUX(CLK_MOUT_FSYS2_BUS_USER, "mout_fsys2_bus_user",
1098         mout_fsys2_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER, 4, 1),
1099     MUX(CLK_MOUT_FSYS2_UFS_EMBD_USER, "mout_fsys2_ufs_embd_user",
1100         mout_fsys2_ufs_embd_user_p,
1101         PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER, 4, 1),
1102     MUX(CLK_MOUT_FSYS2_ETHERNET_USER, "mout_fsys2_ethernet_user",
1103         mout_fsys2_ethernet_user_p,
1104         PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER, 4, 1),
1105 };
1106
1107 static const struct samsung_gate_clock fsys2_gate_clks[] __initconst = {
1108     GATE(CLK_GOUT_FSYS2_UFS_EMBD0_ACLK, "gout_fsys2_ufs_embd0_aclk",
1109          "mout_fsys2_ufs_embd_user",
1110          CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK, 21,
1111          0, 0),
1112     GATE(CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO, "gout_fsys2_ufs_embd0_unipro",
1113          "mout_fsys2_ufs_embd_user",
1114          CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO,
1115          21, 0, 0),
1116     GATE(CLK_GOUT_FSYS2_UFS_EMBD1_ACLK, "gout_fsys2_ufs_embd1_aclk",
1117          "mout_fsys2_ufs_embd_user",
1118          CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK, 21,
1119          0, 0),
1120     GATE(CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO, "gout_fsys2_ufs_embd1_unipro",
1121          "mout_fsys2_ufs_embd_user",
1122          CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO,
1123          21, 0, 0),
1124 };
1125
1126 static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
1127     .mux_clks       = fsys2_mux_clks,
1128     .nr_mux_clks        = ARRAY_SIZE(fsys2_mux_clks),
1129     .gate_clks      = fsys2_gate_clks,
1130     .nr_gate_clks       = ARRAY_SIZE(fsys2_gate_clks),
1131     .nr_clk_ids     = FSYS2_NR_CLK,
1132     .clk_regs       = fsys2_clk_regs,
1133     .nr_clk_regs        = ARRAY_SIZE(fsys2_clk_regs),
1134     .clk_name       = "dout_clkcmu_fsys2_bus",
1135 };
1136
1137 /* ---- CMU_PERIC0 --------------------------------------------------------- */
1138
1139 /* Register Offset definitions for CMU_PERIC0 (0x10200000) */
1140 #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
1141 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER  0x0610
1142 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI    0x1000
1143 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI    0x1004
1144 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI    0x1008
1145 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI    0x100c
1146 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI    0x1010
1147 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI    0x1014
1148 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C  0x1018
1149 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI    0x1800
1150 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI    0x1804
1151 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI    0x1808
1152 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI    0x180c
1153 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI    0x1810
1154 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI    0x1814
1155 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C  0x1818
1156 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0   0x2014
1157 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1   0x2018
1158 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2   0x2024
1159 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3   0x2028
1160 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4   0x202c
1161 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5   0x2030
1162 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6   0x2034
1163 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7   0x2038
1164 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8   0x203c
1165 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9   0x2040
1166 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10  0x201c
1167 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11  0x2020
1168 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0    0x2044
1169 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1    0x2048
1170 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2    0x2058
1171 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3    0x205c
1172 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4    0x2060
1173 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7    0x206c
1174 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5    0x2064
1175 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6    0x2068
1176 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8    0x2070
1177 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9    0x2074
1178 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10   0x204c
1179 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11   0x2050
1180
1181 static const unsigned long peric0_clk_regs[] __initconst = {
1182     PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
1183     PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER,
1184     CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI,
1185     CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI,
1186     CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI,
1187     CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI,
1188     CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI,
1189     CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI,
1190     CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C,
1191     CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1192     CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1193     CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1194     CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1195     CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1196     CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1197     CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
1198     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
1199     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
1200     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
1201     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
1202     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
1203     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
1204     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
1205     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
1206     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
1207     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
1208     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
1209     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
1210     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
1211     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
1212     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
1213     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
1214     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
1215     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
1216     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
1217     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
1218     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
1219     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
1220     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
1221     CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
1222 };
1223
1224 /* List of parent clocks for Muxes in CMU_PERIC0 */
1225 PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_clkcmu_peric0_bus" };
1226 PNAME(mout_peric0_ip_user_p) = { "oscclk", "dout_clkcmu_peric0_ip" };
1227 PNAME(mout_peric0_usi_p) = { "oscclk", "mout_peric0_ip_user" };
1228
1229 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
1230     MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
1231         mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1),
1232     MUX(CLK_MOUT_PERIC0_IP_USER, "mout_peric0_ip_user",
1233         mout_peric0_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 4, 1),
1234     /* USI00 ~ USI05 */
1235     MUX(CLK_MOUT_PERIC0_USI00_USI, "mout_peric0_usi00_usi",
1236         mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
1237     MUX(CLK_MOUT_PERIC0_USI01_USI, "mout_peric0_usi01_usi",
1238         mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
1239     MUX(CLK_MOUT_PERIC0_USI02_USI, "mout_peric0_usi02_usi",
1240         mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
1241     MUX(CLK_MOUT_PERIC0_USI03_USI, "mout_peric0_usi03_usi",
1242         mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
1243     MUX(CLK_MOUT_PERIC0_USI04_USI, "mout_peric0_usi04_usi",
1244         mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
1245     MUX(CLK_MOUT_PERIC0_USI05_USI, "mout_peric0_usi05_usi",
1246         mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
1247     /* USI_I2C */
1248     MUX(CLK_MOUT_PERIC0_USI_I2C, "mout_peric0_usi_i2c",
1249         mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
1250 };
1251
1252 static const struct samsung_div_clock peric0_div_clks[] __initconst = {
1253     /* USI00 ~ USI05 */
1254     DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
1255         "mout_peric0_usi00_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1256         0, 4),
1257     DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
1258         "mout_peric0_usi01_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1259         0, 4),
1260     DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
1261         "mout_peric0_usi02_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1262         0, 4),
1263     DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
1264         "mout_peric0_usi03_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1265         0, 4),
1266     DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
1267         "mout_peric0_usi04_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1268         0, 4),
1269     DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
1270         "mout_peric0_usi05_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1271         0, 4),
1272     /* USI_I2C */
1273     DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",
1274         "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
1275 };
1276
1277 static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
1278     /* IPCLK */
1279     GATE(CLK_GOUT_PERIC0_IPCLK_0, "gout_peric0_ipclk_0",
1280          "dout_peric0_usi00_usi",
1281          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
1282          21, 0, 0),
1283     GATE(CLK_GOUT_PERIC0_IPCLK_1, "gout_peric0_ipclk_1",
1284          "dout_peric0_usi_i2c",
1285          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
1286          21, 0, 0),
1287     GATE(CLK_GOUT_PERIC0_IPCLK_2, "gout_peric0_ipclk_2",
1288          "dout_peric0_usi01_usi",
1289          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
1290          21, 0, 0),
1291     GATE(CLK_GOUT_PERIC0_IPCLK_3, "gout_peric0_ipclk_3",
1292          "dout_peric0_usi_i2c",
1293          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
1294          21, 0, 0),
1295     GATE(CLK_GOUT_PERIC0_IPCLK_4, "gout_peric0_ipclk_4",
1296          "dout_peric0_usi02_usi",
1297          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
1298          21, 0, 0),
1299     GATE(CLK_GOUT_PERIC0_IPCLK_5, "gout_peric0_ipclk_5",
1300          "dout_peric0_usi_i2c",
1301          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
1302          21, 0, 0),
1303     GATE(CLK_GOUT_PERIC0_IPCLK_6, "gout_peric0_ipclk_6",
1304          "dout_peric0_usi03_usi",
1305          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
1306          21, 0, 0),
1307     GATE(CLK_GOUT_PERIC0_IPCLK_7, "gout_peric0_ipclk_7",
1308          "dout_peric0_usi_i2c",
1309          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
1310          21, 0, 0),
1311     GATE(CLK_GOUT_PERIC0_IPCLK_8, "gout_peric0_ipclk_8",
1312          "dout_peric0_usi04_usi",
1313          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
1314          21, 0, 0),
1315     GATE(CLK_GOUT_PERIC0_IPCLK_9, "gout_peric0_ipclk_9",
1316          "dout_peric0_usi_i2c",
1317          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
1318          21, 0, 0),
1319     GATE(CLK_GOUT_PERIC0_IPCLK_10, "gout_peric0_ipclk_10",
1320          "dout_peric0_usi05_usi",
1321          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
1322          21, 0, 0),
1323     GATE(CLK_GOUT_PERIC0_IPCLK_11, "gout_peric0_ipclk_11",
1324          "dout_peric0_usi_i2c",
1325          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
1326          21, 0, 0),
1327
1328     /* PCLK */
1329     GATE(CLK_GOUT_PERIC0_PCLK_0, "gout_peric0_pclk_0",
1330          "mout_peric0_bus_user",
1331          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
1332          21, 0, 0),
1333     GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2",
1334          "mout_peric0_bus_user",
1335          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
1336          21, 0, 0),
1337     GATE(CLK_GOUT_PERIC0_PCLK_3, "gout_peric0_pclk_3",
1338          "mout_peric0_bus_user",
1339          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
1340          21, 0, 0),
1341     GATE(CLK_GOUT_PERIC0_PCLK_4, "gout_peric0_pclk_4",
1342          "mout_peric0_bus_user",
1343          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
1344          21, 0, 0),
1345     GATE(CLK_GOUT_PERIC0_PCLK_5, "gout_peric0_pclk_5",
1346          "mout_peric0_bus_user",
1347          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
1348          21, 0, 0),
1349     GATE(CLK_GOUT_PERIC0_PCLK_6, "gout_peric0_pclk_6",
1350          "mout_peric0_bus_user",
1351          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
1352          21, 0, 0),
1353     GATE(CLK_GOUT_PERIC0_PCLK_7, "gout_peric0_pclk_7",
1354          "mout_peric0_bus_user",
1355          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
1356          21, 0, 0),
1357     GATE(CLK_GOUT_PERIC0_PCLK_8, "gout_peric0_pclk_8",
1358          "mout_peric0_bus_user",
1359          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
1360          21, 0, 0),
1361     GATE(CLK_GOUT_PERIC0_PCLK_9, "gout_peric0_pclk_9",
1362          "mout_peric0_bus_user",
1363          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
1364          21, 0, 0),
1365     GATE(CLK_GOUT_PERIC0_PCLK_10, "gout_peric0_pclk_10",
1366          "mout_peric0_bus_user",
1367          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
1368          21, 0, 0),
1369     GATE(CLK_GOUT_PERIC0_PCLK_11, "gout_peric0_pclk_11",
1370          "mout_peric0_bus_user",
1371          CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
1372          21, 0, 0),
1373 };
1374
1375 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
1376     .mux_clks       = peric0_mux_clks,
1377     .nr_mux_clks        = ARRAY_SIZE(peric0_mux_clks),
1378     .div_clks       = peric0_div_clks,
1379     .nr_div_clks        = ARRAY_SIZE(peric0_div_clks),
1380     .gate_clks      = peric0_gate_clks,
1381     .nr_gate_clks       = ARRAY_SIZE(peric0_gate_clks),
1382     .nr_clk_ids     = PERIC0_NR_CLK,
1383     .clk_regs       = peric0_clk_regs,
1384     .nr_clk_regs        = ARRAY_SIZE(peric0_clk_regs),
1385     .clk_name       = "dout_clkcmu_peric0_bus",
1386 };
1387
1388 /* ---- CMU_PERIC1 --------------------------------------------------------- */
1389
1390 /* Register Offset definitions for CMU_PERIC1 (0x10800000) */
1391 #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
1392 #define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER  0x0610
1393 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI    0x1000
1394 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI    0x1004
1395 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI    0x1008
1396 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI    0x100c
1397 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI    0x1010
1398 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI    0x1014
1399 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C  0x1018
1400 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI    0x1800
1401 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI    0x1804
1402 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI    0x1808
1403 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI    0x180c
1404 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI    0x1810
1405 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI    0x1814
1406 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C  0x1818
1407 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0   0x2014
1408 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1   0x2018
1409 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2   0x2024
1410 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3   0x2028
1411 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4   0x202c
1412 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5   0x2030
1413 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6   0x2034
1414 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7   0x2038
1415 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8   0x203c
1416 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9   0x2040
1417 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10  0x201c
1418 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11  0x2020
1419 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0    0x2044
1420 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1    0x2048
1421 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2    0x2058
1422 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3    0x205c
1423 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4    0x2060
1424 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7    0x206c
1425 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5    0x2064
1426 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6    0x2068
1427 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8    0x2070
1428 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9    0x2074
1429 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10   0x204c
1430 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11   0x2050
1431
1432 static const unsigned long peric1_clk_regs[] __initconst = {
1433     PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
1434     PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,
1435     CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI,
1436     CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI,
1437     CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI,
1438     CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI,
1439     CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI,
1440     CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,
1441     CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,
1442     CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
1443     CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
1444     CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
1445     CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1446     CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1447     CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1448     CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
1449     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0,
1450     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
1451     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
1452     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
1453     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
1454     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
1455     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
1456     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7,
1457     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
1458     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9,
1459     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
1460     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
1461     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
1462     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
1463     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
1464     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
1465     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
1466     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
1467     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
1468     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
1469     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
1470     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
1471     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
1472     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
1473 };
1474
1475 /* List of parent clocks for Muxes in CMU_PERIC1 */
1476 PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_clkcmu_peric1_bus" };
1477 PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" };
1478 PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" };
1479
1480 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
1481     MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
1482         mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1),
1483     MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user",
1484         mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1),
1485     /* USI06 ~ USI11 */
1486     MUX(CLK_MOUT_PERIC1_USI06_USI, "mout_peric1_usi06_usi",
1487         mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI, 0, 1),
1488     MUX(CLK_MOUT_PERIC1_USI07_USI, "mout_peric1_usi07_usi",
1489         mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI, 0, 1),
1490     MUX(CLK_MOUT_PERIC1_USI08_USI, "mout_peric1_usi08_usi",
1491         mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI, 0, 1),
1492     MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi",
1493         mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
1494     MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi",
1495         mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
1496     MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi",
1497         mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
1498     /* USI_I2C */
1499     MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c",
1500         mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
1501 };
1502
1503 static const struct samsung_div_clock peric1_div_clks[] __initconst = {
1504     /* USI06 ~ USI11 */
1505     DIV(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi",
1506         "mout_peric1_usi06_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
1507         0, 4),
1508     DIV(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi",
1509         "mout_peric1_usi07_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
1510         0, 4),
1511     DIV(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi",
1512         "mout_peric1_usi08_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
1513         0, 4),
1514     DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
1515         "mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1516         0, 4),
1517     DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
1518         "mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1519         0, 4),
1520     DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
1521         "mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1522         0, 4),
1523     /* USI_I2C */
1524     DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
1525         "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
1526 };
1527
1528 static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
1529     /* IPCLK */
1530     GATE(CLK_GOUT_PERIC1_IPCLK_0, "gout_peric1_ipclk_0",
1531          "dout_peric1_usi06_usi",
1532          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0,
1533          21, 0, 0),
1534     GATE(CLK_GOUT_PERIC1_IPCLK_1, "gout_peric1_ipclk_1",
1535          "dout_peric1_usi_i2c",
1536          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
1537          21, 0, 0),
1538     GATE(CLK_GOUT_PERIC1_IPCLK_2, "gout_peric1_ipclk_2",
1539          "dout_peric1_usi07_usi",
1540          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
1541          21, 0, 0),
1542     GATE(CLK_GOUT_PERIC1_IPCLK_3, "gout_peric1_ipclk_3",
1543          "dout_peric1_usi_i2c",
1544          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
1545          21, 0, 0),
1546     GATE(CLK_GOUT_PERIC1_IPCLK_4, "gout_peric1_ipclk_4",
1547          "dout_peric1_usi08_usi",
1548          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
1549          21, 0, 0),
1550     GATE(CLK_GOUT_PERIC1_IPCLK_5, "gout_peric1_ipclk_5",
1551          "dout_peric1_usi_i2c",
1552          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
1553          21, 0, 0),
1554     GATE(CLK_GOUT_PERIC1_IPCLK_6, "gout_peric1_ipclk_6",
1555          "dout_peric1_usi09_usi",
1556          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
1557          21, 0, 0),
1558     GATE(CLK_GOUT_PERIC1_IPCLK_7, "gout_peric1_ipclk_7",
1559          "dout_peric1_usi_i2c",
1560          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7,
1561          21, 0, 0),
1562     GATE(CLK_GOUT_PERIC1_IPCLK_8, "gout_peric1_ipclk_8",
1563          "dout_peric1_usi10_usi",
1564          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
1565          21, 0, 0),
1566     GATE(CLK_GOUT_PERIC1_IPCLK_9, "gout_peric1_ipclk_9",
1567          "dout_peric1_usi_i2c",
1568          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9,
1569          21, 0, 0),
1570     GATE(CLK_GOUT_PERIC1_IPCLK_10, "gout_peric1_ipclk_10",
1571          "dout_peric1_usi11_usi",
1572          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
1573          21, 0, 0),
1574     GATE(CLK_GOUT_PERIC1_IPCLK_11, "gout_peric1_ipclk_11",
1575          "dout_peric1_usi_i2c",
1576          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
1577          21, 0, 0),
1578
1579     /* PCLK */
1580     GATE(CLK_GOUT_PERIC1_PCLK_0, "gout_peric1_pclk_0",
1581          "mout_peric1_bus_user",
1582          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
1583          21, 0, 0),
1584     GATE(CLK_GOUT_PERIC1_PCLK_2, "gout_peric1_pclk_2",
1585          "mout_peric1_bus_user",
1586          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
1587          21, 0, 0),
1588     GATE(CLK_GOUT_PERIC1_PCLK_3, "gout_peric1_pclk_3",
1589          "mout_peric1_bus_user",
1590          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
1591          21, 0, 0),
1592     GATE(CLK_GOUT_PERIC1_PCLK_4, "gout_peric1_pclk_4",
1593          "mout_peric1_bus_user",
1594          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
1595          21, 0, 0),
1596     GATE(CLK_GOUT_PERIC1_PCLK_5, "gout_peric1_pclk_5",
1597          "mout_peric1_bus_user",
1598          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
1599          21, 0, 0),
1600     GATE(CLK_GOUT_PERIC1_PCLK_6, "gout_peric1_pclk_6",
1601          "mout_peric1_bus_user",
1602          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
1603          21, 0, 0),
1604     GATE(CLK_GOUT_PERIC1_PCLK_7, "gout_peric1_pclk_7",
1605          "mout_peric1_bus_user",
1606          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
1607          21, 0, 0),
1608     GATE(CLK_GOUT_PERIC1_PCLK_8, "gout_peric1_pclk_8",
1609          "mout_peric1_bus_user",
1610          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
1611          21, 0, 0),
1612     GATE(CLK_GOUT_PERIC1_PCLK_9, "gout_peric1_pclk_9",
1613          "mout_peric1_bus_user",
1614          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
1615          21, 0, 0),
1616     GATE(CLK_GOUT_PERIC1_PCLK_10, "gout_peric1_pclk_10",
1617          "mout_peric1_bus_user",
1618          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
1619          21, 0, 0),
1620     GATE(CLK_GOUT_PERIC1_PCLK_11, "gout_peric1_pclk_11",
1621          "mout_peric1_bus_user",
1622          CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
1623          21, 0, 0),
1624 };
1625
1626 static const struct samsung_cmu_info peric1_cmu_info __initconst = {
1627     .mux_clks       = peric1_mux_clks,
1628     .nr_mux_clks        = ARRAY_SIZE(peric1_mux_clks),
1629     .div_clks       = peric1_div_clks,
1630     .nr_div_clks        = ARRAY_SIZE(peric1_div_clks),
1631     .gate_clks      = peric1_gate_clks,
1632     .nr_gate_clks       = ARRAY_SIZE(peric1_gate_clks),
1633     .nr_clk_ids     = PERIC1_NR_CLK,
1634     .clk_regs       = peric1_clk_regs,
1635     .nr_clk_regs        = ARRAY_SIZE(peric1_clk_regs),
1636     .clk_name       = "dout_clkcmu_peric1_bus",
1637 };
1638
1639 /* ---- CMU_PERIS ---------------------------------------------------------- */
1640
1641 /* Register Offset definitions for CMU_PERIS (0x10020000) */
1642 #define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER  0x0600
1643 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK  0x2058
1644 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK  0x205c
1645 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK  0x2060
1646
1647 static const unsigned long peris_clk_regs[] __initconst = {
1648     PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
1649     CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
1650     CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
1651     CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
1652 };
1653
1654 /* List of parent clocks for Muxes in CMU_PERIS */
1655 PNAME(mout_peris_bus_user_p) = { "oscclk", "dout_clkcmu_peris_bus" };
1656
1657 static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
1658     MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user",
1659         mout_peris_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER, 4, 1),
1660 };
1661
1662 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
1663     GATE(CLK_GOUT_SYSREG_PERIS_PCLK, "gout_sysreg_peris_pclk",
1664          "mout_peris_bus_user",
1665          CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
1666          21, CLK_IGNORE_UNUSED, 0),
1667     GATE(CLK_GOUT_WDT_CLUSTER0, "gout_wdt_cluster0", "mout_peris_bus_user",
1668          CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
1669          21, 0, 0),
1670     GATE(CLK_GOUT_WDT_CLUSTER1, "gout_wdt_cluster1", "mout_peris_bus_user",
1671          CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
1672          21, 0, 0),
1673 };
1674
1675 static const struct samsung_cmu_info peris_cmu_info __initconst = {
1676     .mux_clks       = peris_mux_clks,
1677     .nr_mux_clks        = ARRAY_SIZE(peris_mux_clks),
1678     .gate_clks      = peris_gate_clks,
1679     .nr_gate_clks       = ARRAY_SIZE(peris_gate_clks),
1680     .nr_clk_ids     = PERIS_NR_CLK,
1681     .clk_regs       = peris_clk_regs,
1682     .nr_clk_regs        = ARRAY_SIZE(peris_clk_regs),
1683     .clk_name       = "dout_clkcmu_peris_bus",
1684 };
1685
1686 static int __init exynosautov9_cmu_probe(struct platform_device *pdev)
1687 {
1688     const struct samsung_cmu_info *info;
1689     struct device *dev = &pdev->dev;
1690
1691     info = of_device_get_match_data(dev);
1692     exynos_arm64_register_cmu(dev, dev->of_node, info);
1693
1694     return 0;
1695 }
1696
1697 static const struct of_device_id exynosautov9_cmu_of_match[] = {
1698     {
1699         .compatible = "samsung,exynosautov9-cmu-busmc",
1700         .data = &busmc_cmu_info,
1701     }, {
1702         .compatible = "samsung,exynosautov9-cmu-core",
1703         .data = &core_cmu_info,
1704     }, {
1705         .compatible = "samsung,exynosautov9-cmu-fsys2",
1706         .data = &fsys2_cmu_info,
1707     }, {
1708         .compatible = "samsung,exynosautov9-cmu-peric0",
1709         .data = &peric0_cmu_info,
1710     }, {
1711         .compatible = "samsung,exynosautov9-cmu-peric1",
1712         .data = &peric1_cmu_info,
1713     }, {
1714         .compatible = "samsung,exynosautov9-cmu-peris",
1715         .data = &peris_cmu_info,
1716     }, {
1717     },
1718 };
1719
1720 static struct platform_driver exynosautov9_cmu_driver __refdata = {
1721     .driver = {
1722         .name = "exynosautov9-cmu",
1723         .of_match_table = exynosautov9_cmu_of_match,
1724         .suppress_bind_attrs = true,
1725     },
1726     .probe = exynosautov9_cmu_probe,
1727 };
1728
1729 static int __init exynosautov9_cmu_init(void)
1730 {
1731     return platform_driver_register(&exynosautov9_cmu_driver);
1732 }
1733 core_initcall(exynosautov9_cmu_init);