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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2021 Linaro Ltd.
0004  * Author: Sam Protsenko <semen.protsenko@linaro.org>
0005  *
0006  * Common Clock Framework support for Exynos850 SoC.
0007  */
0008 
0009 #include <linux/clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/of.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 
0015 #include <dt-bindings/clock/exynos850.h>
0016 
0017 #include "clk.h"
0018 #include "clk-exynos-arm64.h"
0019 
0020 /* ---- CMU_TOP ------------------------------------------------------------- */
0021 
0022 /* Register Offset definitions for CMU_TOP (0x120e0000) */
0023 #define PLL_LOCKTIME_PLL_MMC            0x0000
0024 #define PLL_LOCKTIME_PLL_SHARED0        0x0004
0025 #define PLL_LOCKTIME_PLL_SHARED1        0x0008
0026 #define PLL_CON0_PLL_MMC            0x0100
0027 #define PLL_CON3_PLL_MMC            0x010c
0028 #define PLL_CON0_PLL_SHARED0            0x0140
0029 #define PLL_CON3_PLL_SHARED0            0x014c
0030 #define PLL_CON0_PLL_SHARED1            0x0180
0031 #define PLL_CON3_PLL_SHARED1            0x018c
0032 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS      0x1000
0033 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS     0x1014
0034 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI     0x1018
0035 #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD    0x101c
0036 #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS     0x1020
0037 #define CLK_CON_MUX_MUX_CLKCMU_DPU      0x1034
0038 #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS      0x103c
0039 #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
0040 #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
0041 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS     0x1070
0042 #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP      0x1074
0043 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART    0x1078
0044 #define CLK_CON_DIV_CLKCMU_APM_BUS      0x180c
0045 #define CLK_CON_DIV_CLKCMU_CORE_BUS     0x1820
0046 #define CLK_CON_DIV_CLKCMU_CORE_CCI     0x1824
0047 #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD    0x1828
0048 #define CLK_CON_DIV_CLKCMU_CORE_SSS     0x182c
0049 #define CLK_CON_DIV_CLKCMU_DPU          0x1840
0050 #define CLK_CON_DIV_CLKCMU_HSI_BUS      0x1848
0051 #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD     0x184c
0052 #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD     0x1850
0053 #define CLK_CON_DIV_CLKCMU_PERI_BUS     0x187c
0054 #define CLK_CON_DIV_CLKCMU_PERI_IP      0x1880
0055 #define CLK_CON_DIV_CLKCMU_PERI_UART        0x1884
0056 #define CLK_CON_DIV_PLL_SHARED0_DIV2        0x188c
0057 #define CLK_CON_DIV_PLL_SHARED0_DIV3        0x1890
0058 #define CLK_CON_DIV_PLL_SHARED0_DIV4        0x1894
0059 #define CLK_CON_DIV_PLL_SHARED1_DIV2        0x1898
0060 #define CLK_CON_DIV_PLL_SHARED1_DIV3        0x189c
0061 #define CLK_CON_DIV_PLL_SHARED1_DIV4        0x18a0
0062 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS     0x2008
0063 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS    0x201c
0064 #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI    0x2020
0065 #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD   0x2024
0066 #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS    0x2028
0067 #define CLK_CON_GAT_GATE_CLKCMU_DPU     0x203c
0068 #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS     0x2044
0069 #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD    0x2048
0070 #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD    0x204c
0071 #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS    0x2080
0072 #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP     0x2084
0073 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART   0x2088
0074 
0075 static const unsigned long top_clk_regs[] __initconst = {
0076     PLL_LOCKTIME_PLL_MMC,
0077     PLL_LOCKTIME_PLL_SHARED0,
0078     PLL_LOCKTIME_PLL_SHARED1,
0079     PLL_CON0_PLL_MMC,
0080     PLL_CON3_PLL_MMC,
0081     PLL_CON0_PLL_SHARED0,
0082     PLL_CON3_PLL_SHARED0,
0083     PLL_CON0_PLL_SHARED1,
0084     PLL_CON3_PLL_SHARED1,
0085     CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
0086     CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
0087     CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
0088     CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
0089     CLK_CON_MUX_MUX_CLKCMU_CORE_SSS,
0090     CLK_CON_MUX_MUX_CLKCMU_DPU,
0091     CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
0092     CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD,
0093     CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD,
0094     CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
0095     CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
0096     CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
0097     CLK_CON_DIV_CLKCMU_APM_BUS,
0098     CLK_CON_DIV_CLKCMU_CORE_BUS,
0099     CLK_CON_DIV_CLKCMU_CORE_CCI,
0100     CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
0101     CLK_CON_DIV_CLKCMU_CORE_SSS,
0102     CLK_CON_DIV_CLKCMU_DPU,
0103     CLK_CON_DIV_CLKCMU_HSI_BUS,
0104     CLK_CON_DIV_CLKCMU_HSI_MMC_CARD,
0105     CLK_CON_DIV_CLKCMU_HSI_USB20DRD,
0106     CLK_CON_DIV_CLKCMU_PERI_BUS,
0107     CLK_CON_DIV_CLKCMU_PERI_IP,
0108     CLK_CON_DIV_CLKCMU_PERI_UART,
0109     CLK_CON_DIV_PLL_SHARED0_DIV2,
0110     CLK_CON_DIV_PLL_SHARED0_DIV3,
0111     CLK_CON_DIV_PLL_SHARED0_DIV4,
0112     CLK_CON_DIV_PLL_SHARED1_DIV2,
0113     CLK_CON_DIV_PLL_SHARED1_DIV3,
0114     CLK_CON_DIV_PLL_SHARED1_DIV4,
0115     CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
0116     CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
0117     CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
0118     CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
0119     CLK_CON_GAT_GATE_CLKCMU_CORE_SSS,
0120     CLK_CON_GAT_GATE_CLKCMU_DPU,
0121     CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
0122     CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD,
0123     CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD,
0124     CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
0125     CLK_CON_GAT_GATE_CLKCMU_PERI_IP,
0126     CLK_CON_GAT_GATE_CLKCMU_PERI_UART,
0127 };
0128 
0129 /*
0130  * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set
0131  * for those PLLs by default, so set_rate operation would fail.
0132  */
0133 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
0134     /* CMU_TOP_PURECLKCOMP */
0135     PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
0136         PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
0137         NULL),
0138     PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
0139         PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
0140         NULL),
0141     PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
0142         PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
0143 };
0144 
0145 /* List of parent clocks for Muxes in CMU_TOP */
0146 PNAME(mout_shared0_pll_p)   = { "oscclk", "fout_shared0_pll" };
0147 PNAME(mout_shared1_pll_p)   = { "oscclk", "fout_shared1_pll" };
0148 PNAME(mout_mmc_pll_p)       = { "oscclk", "fout_mmc_pll" };
0149 /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
0150 PNAME(mout_clkcmu_apm_bus_p)    = { "dout_shared0_div4", "pll_shared1_div4" };
0151 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
0152 PNAME(mout_core_bus_p)      = { "dout_shared1_div2", "dout_shared0_div3",
0153                     "dout_shared1_div3", "dout_shared0_div4" };
0154 PNAME(mout_core_cci_p)      = { "dout_shared0_div2", "dout_shared1_div2",
0155                     "dout_shared0_div3", "dout_shared1_div3" };
0156 PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
0157                     "dout_shared1_div2", "dout_shared0_div3",
0158                     "dout_shared1_div3", "mout_mmc_pll",
0159                     "oscclk", "oscclk" };
0160 PNAME(mout_core_sss_p)      = { "dout_shared0_div3", "dout_shared1_div3",
0161                     "dout_shared0_div4", "dout_shared1_div4" };
0162 /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */
0163 PNAME(mout_hsi_bus_p)       = { "dout_shared0_div2", "dout_shared1_div2" };
0164 PNAME(mout_hsi_mmc_card_p)  = { "oscclk", "dout_shared0_div2",
0165                     "dout_shared1_div2", "dout_shared0_div3",
0166                     "dout_shared1_div3", "mout_mmc_pll",
0167                     "oscclk", "oscclk" };
0168 PNAME(mout_hsi_usb20drd_p)  = { "oscclk", "dout_shared0_div4",
0169                     "dout_shared1_div4", "oscclk" };
0170 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
0171 PNAME(mout_peri_bus_p)      = { "dout_shared0_div4", "dout_shared1_div4" };
0172 PNAME(mout_peri_uart_p)     = { "oscclk", "dout_shared0_div4",
0173                     "dout_shared1_div4", "oscclk" };
0174 PNAME(mout_peri_ip_p)       = { "oscclk", "dout_shared0_div4",
0175                     "dout_shared1_div4", "oscclk" };
0176 
0177 /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
0178 PNAME(mout_dpu_p)       = { "dout_shared0_div3", "dout_shared1_div3",
0179                     "dout_shared0_div4", "dout_shared1_div4" };
0180 
0181 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
0182     /* CMU_TOP_PURECLKCOMP */
0183     MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
0184         PLL_CON0_PLL_SHARED0, 4, 1),
0185     MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
0186         PLL_CON0_PLL_SHARED1, 4, 1),
0187     MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
0188         PLL_CON0_PLL_MMC, 4, 1),
0189 
0190     /* APM */
0191     MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
0192         mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
0193 
0194     /* CORE */
0195     MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
0196         CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
0197     MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
0198         CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
0199     MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p,
0200         CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3),
0201     MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
0202         CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
0203 
0204     /* DPU */
0205     MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
0206         CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
0207 
0208     /* HSI */
0209     MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p,
0210         CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1),
0211     MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p,
0212         CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3),
0213     MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p,
0214         CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
0215 
0216     /* PERI */
0217     MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
0218         CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
0219     MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p,
0220         CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
0221     MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p,
0222         CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
0223 };
0224 
0225 static const struct samsung_div_clock top_div_clks[] __initconst = {
0226     /* CMU_TOP_PURECLKCOMP */
0227     DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
0228         CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
0229     DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
0230         CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
0231     DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
0232         CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
0233     DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
0234         CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
0235     DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
0236         CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
0237     DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
0238         CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
0239 
0240     /* APM */
0241     DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus",
0242         "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
0243 
0244     /* CORE */
0245     DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
0246         CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
0247     DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
0248         CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4),
0249     DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd",
0250         CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9),
0251     DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss",
0252         CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
0253 
0254     /* DPU */
0255     DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu",
0256         CLK_CON_DIV_CLKCMU_DPU, 0, 4),
0257 
0258     /* HSI */
0259     DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus",
0260         CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4),
0261     DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card",
0262         CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9),
0263     DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd",
0264         CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
0265 
0266     /* PERI */
0267     DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
0268         CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
0269     DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart",
0270         CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
0271     DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip",
0272         CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
0273 };
0274 
0275 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
0276     /* CORE */
0277     GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
0278          CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
0279     GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
0280          CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
0281     GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd",
0282          CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0),
0283     GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss",
0284          CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0),
0285 
0286     /* APM */
0287     GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus",
0288          "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
0289 
0290     /* DPU */
0291     GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
0292          CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
0293 
0294     /* HSI */
0295     GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus",
0296          CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0),
0297     GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card",
0298          CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0),
0299     GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd",
0300          CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
0301 
0302     /* PERI */
0303     GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
0304          CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
0305     GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart",
0306          CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0),
0307     GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip",
0308          CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0),
0309 };
0310 
0311 static const struct samsung_cmu_info top_cmu_info __initconst = {
0312     .pll_clks       = top_pll_clks,
0313     .nr_pll_clks        = ARRAY_SIZE(top_pll_clks),
0314     .mux_clks       = top_mux_clks,
0315     .nr_mux_clks        = ARRAY_SIZE(top_mux_clks),
0316     .div_clks       = top_div_clks,
0317     .nr_div_clks        = ARRAY_SIZE(top_div_clks),
0318     .gate_clks      = top_gate_clks,
0319     .nr_gate_clks       = ARRAY_SIZE(top_gate_clks),
0320     .nr_clk_ids     = TOP_NR_CLK,
0321     .clk_regs       = top_clk_regs,
0322     .nr_clk_regs        = ARRAY_SIZE(top_clk_regs),
0323 };
0324 
0325 static void __init exynos850_cmu_top_init(struct device_node *np)
0326 {
0327     exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
0328 }
0329 
0330 /* Register CMU_TOP early, as it's a dependency for other early domains */
0331 CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top",
0332            exynos850_cmu_top_init);
0333 
0334 /* ---- CMU_APM ------------------------------------------------------------- */
0335 
0336 /* Register Offset definitions for CMU_APM (0x11800000) */
0337 #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER        0x0600
0338 #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER       0x0610
0339 #define PLL_CON0_MUX_CLK_RCO_APM_USER           0x0620
0340 #define PLL_CON0_MUX_DLL_USER               0x0630
0341 #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS         0x1000
0342 #define CLK_CON_MUX_MUX_CLK_APM_BUS         0x1004
0343 #define CLK_CON_MUX_MUX_CLK_APM_I3C         0x1008
0344 #define CLK_CON_DIV_CLKCMU_CHUB_BUS         0x1800
0345 #define CLK_CON_DIV_DIV_CLK_APM_BUS         0x1804
0346 #define CLK_CON_DIV_DIV_CLK_APM_I3C         0x1808
0347 #define CLK_CON_GAT_CLKCMU_CMGP_BUS         0x2000
0348 #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS        0x2014
0349 #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK  0x2018
0350 #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK   0x2020
0351 #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK     0x2024
0352 #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK     0x2028
0353 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK    0x2034
0354 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK    0x2038
0355 #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK        0x20bc
0356 #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK        0x20c0
0357 
0358 static const unsigned long apm_clk_regs[] __initconst = {
0359     PLL_CON0_MUX_CLKCMU_APM_BUS_USER,
0360     PLL_CON0_MUX_CLK_RCO_APM_I3C_USER,
0361     PLL_CON0_MUX_CLK_RCO_APM_USER,
0362     PLL_CON0_MUX_DLL_USER,
0363     CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS,
0364     CLK_CON_MUX_MUX_CLK_APM_BUS,
0365     CLK_CON_MUX_MUX_CLK_APM_I3C,
0366     CLK_CON_DIV_CLKCMU_CHUB_BUS,
0367     CLK_CON_DIV_DIV_CLK_APM_BUS,
0368     CLK_CON_DIV_DIV_CLK_APM_I3C,
0369     CLK_CON_GAT_CLKCMU_CMGP_BUS,
0370     CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS,
0371     CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
0372     CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
0373     CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK,
0374     CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK,
0375     CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK,
0376     CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK,
0377     CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK,
0378     CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK,
0379 };
0380 
0381 /* List of parent clocks for Muxes in CMU_APM */
0382 PNAME(mout_apm_bus_user_p)  = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" };
0383 PNAME(mout_rco_apm_i3c_user_p)  = { "oscclk_rco_apm", "clk_rco_i3c_pmic" };
0384 PNAME(mout_rco_apm_user_p)  = { "oscclk_rco_apm", "clk_rco_apm__alv" };
0385 PNAME(mout_dll_user_p)      = { "oscclk_rco_apm", "clk_dll_dco" };
0386 PNAME(mout_clkcmu_chub_bus_p)   = { "mout_apm_bus_user", "mout_dll_user" };
0387 PNAME(mout_apm_bus_p)       = { "mout_rco_apm_user", "mout_apm_bus_user",
0388                     "mout_dll_user", "oscclk_rco_apm" };
0389 PNAME(mout_apm_i3c_p)       = { "dout_apm_i3c", "mout_rco_apm_i3c_user" };
0390 
0391 static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
0392     FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000),
0393     FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000),
0394     FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000),
0395     FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000),
0396 };
0397 
0398 static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
0399     MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p,
0400         PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1),
0401     MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user",
0402         mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1),
0403     MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p,
0404         PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1),
0405     MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p,
0406         PLL_CON0_MUX_DLL_USER, 4, 1),
0407     MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus",
0408         mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1),
0409     MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p,
0410         CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2),
0411     MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p,
0412         CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1),
0413 };
0414 
0415 static const struct samsung_div_clock apm_div_clks[] __initconst = {
0416     DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus",
0417         "gout_clkcmu_chub_bus",
0418         CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3),
0419     DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus",
0420         CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3),
0421     DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus",
0422         CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3),
0423 };
0424 
0425 static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
0426     GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus",
0427          CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0),
0428     GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus",
0429          "mout_clkcmu_chub_bus",
0430          CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0),
0431     GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus",
0432          CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0),
0433     GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus",
0434          CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0),
0435     GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus",
0436          CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0),
0437     GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c",
0438          CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0),
0439     GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus",
0440          CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
0441     /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
0442     GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus",
0443          CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED,
0444          0),
0445     GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus",
0446          CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0),
0447     GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus",
0448          CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),
0449 };
0450 
0451 static const struct samsung_cmu_info apm_cmu_info __initconst = {
0452     .mux_clks       = apm_mux_clks,
0453     .nr_mux_clks        = ARRAY_SIZE(apm_mux_clks),
0454     .div_clks       = apm_div_clks,
0455     .nr_div_clks        = ARRAY_SIZE(apm_div_clks),
0456     .gate_clks      = apm_gate_clks,
0457     .nr_gate_clks       = ARRAY_SIZE(apm_gate_clks),
0458     .fixed_clks     = apm_fixed_clks,
0459     .nr_fixed_clks      = ARRAY_SIZE(apm_fixed_clks),
0460     .nr_clk_ids     = APM_NR_CLK,
0461     .clk_regs       = apm_clk_regs,
0462     .nr_clk_regs        = ARRAY_SIZE(apm_clk_regs),
0463     .clk_name       = "dout_clkcmu_apm_bus",
0464 };
0465 
0466 /* ---- CMU_CMGP ------------------------------------------------------------ */
0467 
0468 /* Register Offset definitions for CMU_CMGP (0x11c00000) */
0469 #define CLK_CON_MUX_CLK_CMGP_ADC        0x1000
0470 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0  0x1004
0471 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1  0x1008
0472 #define CLK_CON_DIV_DIV_CLK_CMGP_ADC        0x1800
0473 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0  0x1804
0474 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1  0x1808
0475 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0   0x200c
0476 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1   0x2010
0477 #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK     0x2018
0478 #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK  0x2040
0479 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK   0x2044
0480 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK    0x2048
0481 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK   0x204c
0482 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK    0x2050
0483 
0484 static const unsigned long cmgp_clk_regs[] __initconst = {
0485     CLK_CON_MUX_CLK_CMGP_ADC,
0486     CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0,
0487     CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1,
0488     CLK_CON_DIV_DIV_CLK_CMGP_ADC,
0489     CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0,
0490     CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1,
0491     CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0,
0492     CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1,
0493     CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK,
0494     CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK,
0495     CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK,
0496     CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK,
0497     CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK,
0498     CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK,
0499 };
0500 
0501 /* List of parent clocks for Muxes in CMU_CMGP */
0502 PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
0503 PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
0504 PNAME(mout_cmgp_adc_p)  = { "oscclk", "dout_cmgp_adc" };
0505 
0506 static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = {
0507     FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000),
0508 };
0509 
0510 static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = {
0511     MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p,
0512         CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
0513     MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
0514         CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1),
0515     MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
0516         CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1),
0517 };
0518 
0519 static const struct samsung_div_clock cmgp_div_clks[] __initconst = {
0520     DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus",
0521         CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
0522     DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
0523         CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5),
0524     DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
0525         CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5),
0526 };
0527 
0528 static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
0529     GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk",
0530          "gout_clkcmu_cmgp_bus",
0531          CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0),
0532     GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk",
0533          "gout_clkcmu_cmgp_bus",
0534          CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0),
0535     /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
0536     GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk",
0537          "gout_clkcmu_cmgp_bus",
0538          CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0),
0539     GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0",
0540          CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0),
0541     GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk",
0542          "gout_clkcmu_cmgp_bus",
0543          CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
0544     GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1",
0545          CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0),
0546     GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk",
0547          "gout_clkcmu_cmgp_bus",
0548          CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
0549     GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk",
0550          "gout_clkcmu_cmgp_bus",
0551          CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0),
0552 };
0553 
0554 static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
0555     .mux_clks       = cmgp_mux_clks,
0556     .nr_mux_clks        = ARRAY_SIZE(cmgp_mux_clks),
0557     .div_clks       = cmgp_div_clks,
0558     .nr_div_clks        = ARRAY_SIZE(cmgp_div_clks),
0559     .gate_clks      = cmgp_gate_clks,
0560     .nr_gate_clks       = ARRAY_SIZE(cmgp_gate_clks),
0561     .fixed_clks     = cmgp_fixed_clks,
0562     .nr_fixed_clks      = ARRAY_SIZE(cmgp_fixed_clks),
0563     .nr_clk_ids     = CMGP_NR_CLK,
0564     .clk_regs       = cmgp_clk_regs,
0565     .nr_clk_regs        = ARRAY_SIZE(cmgp_clk_regs),
0566     .clk_name       = "gout_clkcmu_cmgp_bus",
0567 };
0568 
0569 /* ---- CMU_HSI ------------------------------------------------------------- */
0570 
0571 /* Register Offset definitions for CMU_HSI (0x13400000) */
0572 #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER            0x0600
0573 #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER           0x0610
0574 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER           0x0620
0575 #define CLK_CON_MUX_MUX_CLK_HSI_RTC             0x1000
0576 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV     0x2008
0577 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50       0x200c
0578 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26        0x2010
0579 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK          0x2018
0580 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK            0x2024
0581 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN           0x2028
0582 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK            0x2038
0583 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20   0x203c
0584 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY     0x2040
0585 
0586 static const unsigned long hsi_clk_regs[] __initconst = {
0587     PLL_CON0_MUX_CLKCMU_HSI_BUS_USER,
0588     PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
0589     PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
0590     CLK_CON_MUX_MUX_CLK_HSI_RTC,
0591     CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV,
0592     CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50,
0593     CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26,
0594     CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK,
0595     CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK,
0596     CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN,
0597     CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK,
0598     CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20,
0599     CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY,
0600 };
0601 
0602 /* List of parent clocks for Muxes in CMU_PERI */
0603 PNAME(mout_hsi_bus_user_p)  = { "oscclk", "dout_hsi_bus" };
0604 PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" };
0605 PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" };
0606 PNAME(mout_hsi_rtc_p)       = { "rtcclk", "oscclk" };
0607 
0608 static const struct samsung_mux_clock hsi_mux_clks[] __initconst = {
0609     MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p,
0610         PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1),
0611     MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user",
0612           mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
0613           4, 1, CLK_SET_RATE_PARENT, 0),
0614     MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user",
0615         mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
0616         4, 1),
0617     MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p,
0618         CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1),
0619 };
0620 
0621 static const struct samsung_gate_clock hsi_gate_clks[] __initconst = {
0622     GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc",
0623          CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0),
0624     GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user",
0625          CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0),
0626     GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk",
0627          CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0),
0628     /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
0629     GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user",
0630          CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
0631     GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user",
0632          CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0),
0633     GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
0634          "mout_hsi_mmc_card_user",
0635          CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0),
0636     GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk",
0637          "mout_hsi_bus_user",
0638          CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0),
0639     GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user",
0640          CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0),
0641     GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early",
0642          "mout_hsi_bus_user",
0643          CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0),
0644 };
0645 
0646 static const struct samsung_cmu_info hsi_cmu_info __initconst = {
0647     .mux_clks       = hsi_mux_clks,
0648     .nr_mux_clks        = ARRAY_SIZE(hsi_mux_clks),
0649     .gate_clks      = hsi_gate_clks,
0650     .nr_gate_clks       = ARRAY_SIZE(hsi_gate_clks),
0651     .nr_clk_ids     = HSI_NR_CLK,
0652     .clk_regs       = hsi_clk_regs,
0653     .nr_clk_regs        = ARRAY_SIZE(hsi_clk_regs),
0654     .clk_name       = "dout_hsi_bus",
0655 };
0656 
0657 /* ---- CMU_PERI ------------------------------------------------------------ */
0658 
0659 /* Register Offset definitions for CMU_PERI (0x10030000) */
0660 #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER   0x0600
0661 #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610
0662 #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER   0x0620
0663 #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER  0x0630
0664 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0    0x1800
0665 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1    0x1804
0666 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2    0x1808
0667 #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0      0x180c
0668 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0   0x200c
0669 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1   0x2010
0670 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2   0x2014
0671 #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK    0x2020
0672 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024
0673 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK  0x2028
0674 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c
0675 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK  0x2030
0676 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034
0677 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK  0x2038
0678 #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK    0x203c
0679 #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK    0x2040
0680 #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK    0x2044
0681 #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK    0x2048
0682 #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK    0x204c
0683 #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK    0x2050
0684 #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK    0x2054
0685 #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK      0x205c
0686 #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK    0x2064
0687 #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK   0x209c
0688 #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK    0x20a0
0689 #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK  0x20a4
0690 #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK    0x20a8
0691 #define CLK_CON_GAT_GOUT_PERI_UART_PCLK     0x20ac
0692 #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK    0x20b0
0693 #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK    0x20b4
0694 
0695 static const unsigned long peri_clk_regs[] __initconst = {
0696     PLL_CON0_MUX_CLKCMU_PERI_BUS_USER,
0697     PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER,
0698     PLL_CON0_MUX_CLKCMU_PERI_SPI_USER,
0699     PLL_CON0_MUX_CLKCMU_PERI_UART_USER,
0700     CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0,
0701     CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1,
0702     CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2,
0703     CLK_CON_DIV_DIV_CLK_PERI_SPI_0,
0704     CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0,
0705     CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1,
0706     CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2,
0707     CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK,
0708     CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK,
0709     CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
0710     CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK,
0711     CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK,
0712     CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK,
0713     CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK,
0714     CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK,
0715     CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK,
0716     CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK,
0717     CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK,
0718     CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK,
0719     CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK,
0720     CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK,
0721     CLK_CON_GAT_GOUT_PERI_MCT_PCLK,
0722     CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK,
0723     CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK,
0724     CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK,
0725     CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK,
0726     CLK_CON_GAT_GOUT_PERI_UART_IPCLK,
0727     CLK_CON_GAT_GOUT_PERI_UART_PCLK,
0728     CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK,
0729     CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK,
0730 };
0731 
0732 /* List of parent clocks for Muxes in CMU_PERI */
0733 PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" };
0734 PNAME(mout_peri_uart_user_p)    = { "oscclk", "dout_peri_uart" };
0735 PNAME(mout_peri_hsi2c_user_p)   = { "oscclk", "dout_peri_ip" };
0736 PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" };
0737 
0738 static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
0739     MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p,
0740         PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
0741     MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user",
0742         mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1),
0743     MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user",
0744         mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1),
0745     MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p,
0746         PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1),
0747 };
0748 
0749 static const struct samsung_div_clock peri_div_clks[] __initconst = {
0750     DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0",
0751         CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5),
0752     DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1",
0753         CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5),
0754     DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2",
0755         CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5),
0756     DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user",
0757         CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5),
0758 };
0759 
0760 static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
0761     GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user",
0762          CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0),
0763     GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user",
0764          CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0),
0765     GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user",
0766          CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0),
0767     GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0",
0768          CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0),
0769     GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user",
0770          CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
0771     GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1",
0772          CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0),
0773     GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user",
0774          CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
0775     GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2",
0776          CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0),
0777     GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user",
0778          CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
0779     GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user",
0780          CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
0781     GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user",
0782          CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
0783     GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user",
0784          CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
0785     GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user",
0786          CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
0787     GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user",
0788          CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
0789     GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user",
0790          CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
0791     GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user",
0792          CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
0793     GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user",
0794          CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
0795     GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk",
0796          "mout_peri_bus_user",
0797          CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
0798     GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0",
0799          CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0),
0800     GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
0801          CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
0802     GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",
0803          "mout_peri_bus_user",
0804          CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
0805     GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user",
0806          CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0),
0807     GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user",
0808          CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0),
0809     GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
0810          CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0),
0811     GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
0812          CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0),
0813     /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
0814     GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk",
0815          "mout_peri_bus_user",
0816          CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
0817 };
0818 
0819 static const struct samsung_cmu_info peri_cmu_info __initconst = {
0820     .mux_clks       = peri_mux_clks,
0821     .nr_mux_clks        = ARRAY_SIZE(peri_mux_clks),
0822     .div_clks       = peri_div_clks,
0823     .nr_div_clks        = ARRAY_SIZE(peri_div_clks),
0824     .gate_clks      = peri_gate_clks,
0825     .nr_gate_clks       = ARRAY_SIZE(peri_gate_clks),
0826     .nr_clk_ids     = PERI_NR_CLK,
0827     .clk_regs       = peri_clk_regs,
0828     .nr_clk_regs        = ARRAY_SIZE(peri_clk_regs),
0829     .clk_name       = "dout_peri_bus",
0830 };
0831 
0832 static void __init exynos850_cmu_peri_init(struct device_node *np)
0833 {
0834     exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
0835 }
0836 
0837 /* Register CMU_PERI early, as it's needed for MCT timer */
0838 CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri",
0839            exynos850_cmu_peri_init);
0840 
0841 /* ---- CMU_CORE ------------------------------------------------------------ */
0842 
0843 /* Register Offset definitions for CMU_CORE (0x12000000) */
0844 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER   0x0600
0845 #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER   0x0610
0846 #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER  0x0620
0847 #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER   0x0630
0848 #define CLK_CON_MUX_MUX_CLK_CORE_GIC        0x1000
0849 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP       0x1800
0850 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK  0x2038
0851 #define CLK_CON_GAT_GOUT_CORE_GIC_CLK       0x2040
0852 #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK    0x2044
0853 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK   0x20e8
0854 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN  0x20ec
0855 #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK    0x2128
0856 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK    0x212c
0857 #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK  0x2130
0858 
0859 static const unsigned long core_clk_regs[] __initconst = {
0860     PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
0861     PLL_CON0_MUX_CLKCMU_CORE_CCI_USER,
0862     PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
0863     PLL_CON0_MUX_CLKCMU_CORE_SSS_USER,
0864     CLK_CON_MUX_MUX_CLK_CORE_GIC,
0865     CLK_CON_DIV_DIV_CLK_CORE_BUSP,
0866     CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
0867     CLK_CON_GAT_GOUT_CORE_GIC_CLK,
0868     CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK,
0869     CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK,
0870     CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
0871     CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK,
0872     CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK,
0873     CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK,
0874 };
0875 
0876 /* List of parent clocks for Muxes in CMU_CORE */
0877 PNAME(mout_core_bus_user_p)     = { "oscclk", "dout_core_bus" };
0878 PNAME(mout_core_cci_user_p)     = { "oscclk", "dout_core_cci" };
0879 PNAME(mout_core_mmc_embd_user_p)    = { "oscclk", "dout_core_mmc_embd" };
0880 PNAME(mout_core_sss_user_p)     = { "oscclk", "dout_core_sss" };
0881 PNAME(mout_core_gic_p)          = { "dout_core_busp", "oscclk" };
0882 
0883 static const struct samsung_mux_clock core_mux_clks[] __initconst = {
0884     MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
0885         PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
0886     MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p,
0887         PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1),
0888     MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user",
0889           mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
0890           4, 1, CLK_SET_RATE_PARENT, 0),
0891     MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p,
0892         PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1),
0893     MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p,
0894         CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
0895 };
0896 
0897 static const struct samsung_div_clock core_div_clks[] __initconst = {
0898     DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
0899         CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
0900 };
0901 
0902 static const struct samsung_gate_clock core_gate_clks[] __initconst = {
0903     /* CCI (interconnect) clock must be always running */
0904     GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
0905          CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
0906     /* GIC (interrupt controller) clock must be always running */
0907     GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic",
0908          CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0),
0909     GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp",
0910          CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0),
0911     GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
0912          "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
0913          21, CLK_SET_RATE_PARENT, 0),
0914     GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user",
0915          CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0),
0916     GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp",
0917          CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0),
0918     /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
0919     GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp",
0920          CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0),
0921     GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk",
0922          "dout_core_busp",
0923          CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0),
0924 };
0925 
0926 static const struct samsung_cmu_info core_cmu_info __initconst = {
0927     .mux_clks       = core_mux_clks,
0928     .nr_mux_clks        = ARRAY_SIZE(core_mux_clks),
0929     .div_clks       = core_div_clks,
0930     .nr_div_clks        = ARRAY_SIZE(core_div_clks),
0931     .gate_clks      = core_gate_clks,
0932     .nr_gate_clks       = ARRAY_SIZE(core_gate_clks),
0933     .nr_clk_ids     = CORE_NR_CLK,
0934     .clk_regs       = core_clk_regs,
0935     .nr_clk_regs        = ARRAY_SIZE(core_clk_regs),
0936     .clk_name       = "dout_core_bus",
0937 };
0938 
0939 /* ---- CMU_DPU ------------------------------------------------------------- */
0940 
0941 /* Register Offset definitions for CMU_DPU (0x13000000) */
0942 #define PLL_CON0_MUX_CLKCMU_DPU_USER        0x0600
0943 #define CLK_CON_DIV_DIV_CLK_DPU_BUSP        0x1800
0944 #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK    0x2004
0945 #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0    0x2010
0946 #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA       0x2014
0947 #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP       0x2018
0948 #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK      0x2028
0949 #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK      0x202c
0950 #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK       0x2038
0951 #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK    0x203c
0952 
0953 static const unsigned long dpu_clk_regs[] __initconst = {
0954     PLL_CON0_MUX_CLKCMU_DPU_USER,
0955     CLK_CON_DIV_DIV_CLK_DPU_BUSP,
0956     CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK,
0957     CLK_CON_GAT_GOUT_DPU_ACLK_DECON0,
0958     CLK_CON_GAT_GOUT_DPU_ACLK_DMA,
0959     CLK_CON_GAT_GOUT_DPU_ACLK_DPP,
0960     CLK_CON_GAT_GOUT_DPU_PPMU_ACLK,
0961     CLK_CON_GAT_GOUT_DPU_PPMU_PCLK,
0962     CLK_CON_GAT_GOUT_DPU_SMMU_CLK,
0963     CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK,
0964 };
0965 
0966 /* List of parent clocks for Muxes in CMU_CORE */
0967 PNAME(mout_dpu_user_p)      = { "oscclk", "dout_dpu" };
0968 
0969 static const struct samsung_mux_clock dpu_mux_clks[] __initconst = {
0970     MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p,
0971         PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1),
0972 };
0973 
0974 static const struct samsung_div_clock dpu_div_clks[] __initconst = {
0975     DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user",
0976         CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3),
0977 };
0978 
0979 static const struct samsung_gate_clock dpu_gate_clks[] __initconst = {
0980     /* TODO: Should be enabled in DSIM driver */
0981     GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk",
0982          "dout_dpu_busp",
0983          CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
0984     GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user",
0985          CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0),
0986     GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user",
0987          CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0),
0988     GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user",
0989          CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0),
0990     GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user",
0991          CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0),
0992     GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp",
0993          CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0),
0994     GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user",
0995          CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0),
0996     GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp",
0997          CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0),
0998 };
0999 
1000 static const struct samsung_cmu_info dpu_cmu_info __initconst = {
1001     .mux_clks       = dpu_mux_clks,
1002     .nr_mux_clks        = ARRAY_SIZE(dpu_mux_clks),
1003     .div_clks       = dpu_div_clks,
1004     .nr_div_clks        = ARRAY_SIZE(dpu_div_clks),
1005     .gate_clks      = dpu_gate_clks,
1006     .nr_gate_clks       = ARRAY_SIZE(dpu_gate_clks),
1007     .nr_clk_ids     = DPU_NR_CLK,
1008     .clk_regs       = dpu_clk_regs,
1009     .nr_clk_regs        = ARRAY_SIZE(dpu_clk_regs),
1010     .clk_name       = "dout_dpu",
1011 };
1012 
1013 /* ---- platform_driver ----------------------------------------------------- */
1014 
1015 static int __init exynos850_cmu_probe(struct platform_device *pdev)
1016 {
1017     const struct samsung_cmu_info *info;
1018     struct device *dev = &pdev->dev;
1019 
1020     info = of_device_get_match_data(dev);
1021     exynos_arm64_register_cmu(dev, dev->of_node, info);
1022 
1023     return 0;
1024 }
1025 
1026 static const struct of_device_id exynos850_cmu_of_match[] = {
1027     {
1028         .compatible = "samsung,exynos850-cmu-apm",
1029         .data = &apm_cmu_info,
1030     }, {
1031         .compatible = "samsung,exynos850-cmu-cmgp",
1032         .data = &cmgp_cmu_info,
1033     }, {
1034         .compatible = "samsung,exynos850-cmu-hsi",
1035         .data = &hsi_cmu_info,
1036     }, {
1037         .compatible = "samsung,exynos850-cmu-core",
1038         .data = &core_cmu_info,
1039     }, {
1040         .compatible = "samsung,exynos850-cmu-dpu",
1041         .data = &dpu_cmu_info,
1042     }, {
1043     },
1044 };
1045 
1046 static struct platform_driver exynos850_cmu_driver __refdata = {
1047     .driver = {
1048         .name = "exynos850-cmu",
1049         .of_match_table = exynos850_cmu_of_match,
1050         .suppress_bind_attrs = true,
1051     },
1052     .probe = exynos850_cmu_probe,
1053 };
1054 
1055 static int __init exynos850_cmu_init(void)
1056 {
1057     return platform_driver_register(&exynos850_cmu_driver);
1058 }
1059 core_initcall(exynos850_cmu_init);
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