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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
0004  * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
0005 */
0006 
0007 #include <linux/clk-provider.h>
0008 #include <linux/of.h>
0009 
0010 #include "clk.h"
0011 #include <dt-bindings/clock/exynos7-clk.h>
0012 
0013 /* Register Offset definitions for CMU_TOPC (0x10570000) */
0014 #define CC_PLL_LOCK     0x0000
0015 #define BUS0_PLL_LOCK       0x0004
0016 #define BUS1_DPLL_LOCK      0x0008
0017 #define MFC_PLL_LOCK        0x000C
0018 #define AUD_PLL_LOCK        0x0010
0019 #define CC_PLL_CON0     0x0100
0020 #define BUS0_PLL_CON0       0x0110
0021 #define BUS1_DPLL_CON0      0x0120
0022 #define MFC_PLL_CON0        0x0130
0023 #define AUD_PLL_CON0        0x0140
0024 #define MUX_SEL_TOPC0       0x0200
0025 #define MUX_SEL_TOPC1       0x0204
0026 #define MUX_SEL_TOPC2       0x0208
0027 #define MUX_SEL_TOPC3       0x020C
0028 #define DIV_TOPC0       0x0600
0029 #define DIV_TOPC1       0x0604
0030 #define DIV_TOPC3       0x060C
0031 #define ENABLE_ACLK_TOPC0   0x0800
0032 #define ENABLE_ACLK_TOPC1   0x0804
0033 #define ENABLE_SCLK_TOPC1   0x0A04
0034 
0035 static const struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initconst = {
0036     FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
0037     FFACTOR(0, "ffac_topc_bus0_pll_div4",
0038         "ffac_topc_bus0_pll_div2", 1, 2, 0),
0039     FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0),
0040     FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0),
0041     FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0),
0042 };
0043 
0044 /* List of parent clocks for Muxes in CMU_TOPC */
0045 PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
0046 PNAME(mout_topc_bus0_pll_ctrl_p)    = { "fin_pll", "fout_bus0_pll" };
0047 PNAME(mout_topc_bus1_pll_ctrl_p)    = { "fin_pll", "fout_bus1_pll" };
0048 PNAME(mout_topc_cc_pll_ctrl_p)  = { "fin_pll", "fout_cc_pll" };
0049 PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
0050 
0051 PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half",
0052     "mout_topc_bus1_pll_half", "mout_topc_cc_pll_half",
0053     "mout_topc_mfc_pll_half" };
0054 
0055 PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll",
0056     "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
0057 PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll",
0058     "ffac_topc_bus1_pll_div2"};
0059 PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll",
0060     "ffac_topc_cc_pll_div2"};
0061 PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll",
0062     "ffac_topc_mfc_pll_div2"};
0063 
0064 
0065 PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll",
0066     "ffac_topc_bus0_pll_div2"};
0067 
0068 static const unsigned long topc_clk_regs[] __initconst = {
0069     CC_PLL_LOCK,
0070     BUS0_PLL_LOCK,
0071     BUS1_DPLL_LOCK,
0072     MFC_PLL_LOCK,
0073     AUD_PLL_LOCK,
0074     CC_PLL_CON0,
0075     BUS0_PLL_CON0,
0076     BUS1_DPLL_CON0,
0077     MFC_PLL_CON0,
0078     AUD_PLL_CON0,
0079     MUX_SEL_TOPC0,
0080     MUX_SEL_TOPC1,
0081     MUX_SEL_TOPC2,
0082     MUX_SEL_TOPC3,
0083     DIV_TOPC0,
0084     DIV_TOPC1,
0085     DIV_TOPC3,
0086 };
0087 
0088 static const struct samsung_mux_clock topc_mux_clks[] __initconst = {
0089     MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
0090         MUX_SEL_TOPC0, 0, 1),
0091     MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
0092         MUX_SEL_TOPC0, 4, 1),
0093     MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
0094         MUX_SEL_TOPC0, 8, 1),
0095     MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
0096         MUX_SEL_TOPC0, 12, 1),
0097     MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
0098         MUX_SEL_TOPC0, 16, 2),
0099     MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
0100         MUX_SEL_TOPC0, 20, 1),
0101     MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
0102         MUX_SEL_TOPC0, 24, 1),
0103     MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
0104         MUX_SEL_TOPC0, 28, 1),
0105 
0106     MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
0107         MUX_SEL_TOPC1, 0, 1),
0108     MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
0109         MUX_SEL_TOPC1, 16, 1),
0110 
0111     MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
0112 
0113     MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
0114     MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
0115 };
0116 
0117 static const struct samsung_div_clock topc_div_clks[] __initconst = {
0118     DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
0119         DIV_TOPC0, 4, 4),
0120 
0121     DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532",
0122         DIV_TOPC1, 20, 4),
0123     DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
0124         DIV_TOPC1, 24, 4),
0125 
0126     DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out",
0127         DIV_TOPC3, 0, 4),
0128     DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll",
0129         DIV_TOPC3, 8, 4),
0130     DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll",
0131         DIV_TOPC3, 12, 4),
0132     DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll",
0133         DIV_TOPC3, 16, 4),
0134     DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll",
0135         DIV_TOPC3, 28, 4),
0136 };
0137 
0138 static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = {
0139     PLL_36XX_RATE(24 * MHZ, 491519897, 20, 1, 0, 31457),
0140     {},
0141 };
0142 
0143 static const struct samsung_gate_clock topc_gate_clks[] __initconst = {
0144     GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
0145         ENABLE_ACLK_TOPC0, 4, CLK_IS_CRITICAL, 0),
0146 
0147     GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
0148         ENABLE_ACLK_TOPC1, 20, 0, 0),
0149 
0150     GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66",
0151         ENABLE_ACLK_TOPC1, 24, 0, 0),
0152 
0153     GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
0154         ENABLE_SCLK_TOPC1, 20, 0, 0),
0155     GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
0156         ENABLE_SCLK_TOPC1, 17, 0, 0),
0157     GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
0158         ENABLE_SCLK_TOPC1, 16, 0, 0),
0159     GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
0160         ENABLE_SCLK_TOPC1, 13, 0, 0),
0161     GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
0162         ENABLE_SCLK_TOPC1, 12, 0, 0),
0163     GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll",
0164         ENABLE_SCLK_TOPC1, 5, 0, 0),
0165     GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll",
0166         ENABLE_SCLK_TOPC1, 4, 0, 0),
0167     GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll",
0168         ENABLE_SCLK_TOPC1, 1, 0, 0),
0169     GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
0170         ENABLE_SCLK_TOPC1, 0, 0, 0),
0171 };
0172 
0173 static const struct samsung_pll_clock topc_pll_clks[] __initconst = {
0174     PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
0175         BUS0_PLL_CON0, NULL),
0176     PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
0177         CC_PLL_CON0, NULL),
0178     PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
0179         BUS1_DPLL_CON0, NULL),
0180     PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
0181         MFC_PLL_CON0, NULL),
0182     PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
0183         AUD_PLL_CON0, pll1460x_24mhz_tbl),
0184 };
0185 
0186 static const struct samsung_cmu_info topc_cmu_info __initconst = {
0187     .pll_clks       = topc_pll_clks,
0188     .nr_pll_clks        = ARRAY_SIZE(topc_pll_clks),
0189     .mux_clks       = topc_mux_clks,
0190     .nr_mux_clks        = ARRAY_SIZE(topc_mux_clks),
0191     .div_clks       = topc_div_clks,
0192     .nr_div_clks        = ARRAY_SIZE(topc_div_clks),
0193     .gate_clks      = topc_gate_clks,
0194     .nr_gate_clks       = ARRAY_SIZE(topc_gate_clks),
0195     .fixed_factor_clks  = topc_fixed_factor_clks,
0196     .nr_fixed_factor_clks   = ARRAY_SIZE(topc_fixed_factor_clks),
0197     .nr_clk_ids     = TOPC_NR_CLK,
0198     .clk_regs       = topc_clk_regs,
0199     .nr_clk_regs        = ARRAY_SIZE(topc_clk_regs),
0200 };
0201 
0202 static void __init exynos7_clk_topc_init(struct device_node *np)
0203 {
0204     samsung_cmu_register_one(np, &topc_cmu_info);
0205 }
0206 
0207 CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
0208     exynos7_clk_topc_init);
0209 
0210 /* Register Offset definitions for CMU_TOP0 (0x105D0000) */
0211 #define MUX_SEL_TOP00           0x0200
0212 #define MUX_SEL_TOP01           0x0204
0213 #define MUX_SEL_TOP03           0x020C
0214 #define MUX_SEL_TOP0_PERIC0     0x0230
0215 #define MUX_SEL_TOP0_PERIC1     0x0234
0216 #define MUX_SEL_TOP0_PERIC2     0x0238
0217 #define MUX_SEL_TOP0_PERIC3     0x023C
0218 #define DIV_TOP03           0x060C
0219 #define DIV_TOP0_PERIC0         0x0630
0220 #define DIV_TOP0_PERIC1         0x0634
0221 #define DIV_TOP0_PERIC2         0x0638
0222 #define DIV_TOP0_PERIC3         0x063C
0223 #define ENABLE_ACLK_TOP03       0x080C
0224 #define ENABLE_SCLK_TOP0_PERIC0     0x0A30
0225 #define ENABLE_SCLK_TOP0_PERIC1     0x0A34
0226 #define ENABLE_SCLK_TOP0_PERIC2     0x0A38
0227 #define ENABLE_SCLK_TOP0_PERIC3     0x0A3C
0228 
0229 /* List of parent clocks for Muxes in CMU_TOP0 */
0230 PNAME(mout_top0_bus0_pll_user_p)    = { "fin_pll", "sclk_bus0_pll_a" };
0231 PNAME(mout_top0_bus1_pll_user_p)    = { "fin_pll", "sclk_bus1_pll_a" };
0232 PNAME(mout_top0_cc_pll_user_p)  = { "fin_pll", "sclk_cc_pll_a" };
0233 PNAME(mout_top0_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_a" };
0234 PNAME(mout_top0_aud_pll_user_p) = { "fin_pll", "sclk_aud_pll" };
0235 
0236 PNAME(mout_top0_bus0_pll_half_p) = {"mout_top0_bus0_pll_user",
0237     "ffac_top0_bus0_pll_div2"};
0238 PNAME(mout_top0_bus1_pll_half_p) = {"mout_top0_bus1_pll_user",
0239     "ffac_top0_bus1_pll_div2"};
0240 PNAME(mout_top0_cc_pll_half_p) = {"mout_top0_cc_pll_user",
0241     "ffac_top0_cc_pll_div2"};
0242 PNAME(mout_top0_mfc_pll_half_p) = {"mout_top0_mfc_pll_user",
0243     "ffac_top0_mfc_pll_div2"};
0244 
0245 PNAME(mout_top0_group1) = {"mout_top0_bus0_pll_half",
0246     "mout_top0_bus1_pll_half", "mout_top0_cc_pll_half",
0247     "mout_top0_mfc_pll_half"};
0248 PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
0249     "ioclk_audiocdclk1", "ioclk_spdif_extclk",
0250     "mout_top0_aud_pll_user", "mout_top0_bus0_pll_half",
0251     "mout_top0_bus1_pll_half"};
0252 PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user",
0253     "mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"};
0254 
0255 static const unsigned long top0_clk_regs[] __initconst = {
0256     MUX_SEL_TOP00,
0257     MUX_SEL_TOP01,
0258     MUX_SEL_TOP03,
0259     MUX_SEL_TOP0_PERIC0,
0260     MUX_SEL_TOP0_PERIC1,
0261     MUX_SEL_TOP0_PERIC2,
0262     MUX_SEL_TOP0_PERIC3,
0263     DIV_TOP03,
0264     DIV_TOP0_PERIC0,
0265     DIV_TOP0_PERIC1,
0266     DIV_TOP0_PERIC2,
0267     DIV_TOP0_PERIC3,
0268     ENABLE_SCLK_TOP0_PERIC0,
0269     ENABLE_SCLK_TOP0_PERIC1,
0270     ENABLE_SCLK_TOP0_PERIC2,
0271     ENABLE_SCLK_TOP0_PERIC3,
0272 };
0273 
0274 static const struct samsung_mux_clock top0_mux_clks[] __initconst = {
0275     MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p,
0276         MUX_SEL_TOP00, 0, 1),
0277     MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p,
0278         MUX_SEL_TOP00, 4, 1),
0279     MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p,
0280         MUX_SEL_TOP00, 8, 1),
0281     MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p,
0282         MUX_SEL_TOP00, 12, 1),
0283     MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p,
0284         MUX_SEL_TOP00, 16, 1),
0285 
0286     MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p,
0287         MUX_SEL_TOP01, 4, 1),
0288     MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p,
0289         MUX_SEL_TOP01, 8, 1),
0290     MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p,
0291         MUX_SEL_TOP01, 12, 1),
0292     MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p,
0293         MUX_SEL_TOP01, 16, 1),
0294 
0295     MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
0296     MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
0297 
0298     MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
0299     MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
0300     MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
0301 
0302     MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
0303     MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
0304 
0305     MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
0306     MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
0307     MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
0308     MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
0309     MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
0310     MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
0311     MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
0312 };
0313 
0314 static const struct samsung_div_clock top0_div_clks[] __initconst = {
0315     DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
0316         DIV_TOP03, 12, 6),
0317     DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
0318         DIV_TOP03, 20, 6),
0319 
0320     DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
0321     DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
0322     DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
0323 
0324     DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
0325     DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
0326 
0327     DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
0328     DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
0329 
0330     DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
0331     DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
0332     DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
0333     DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
0334     DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
0335 };
0336 
0337 static const struct samsung_gate_clock top0_gate_clks[] __initconst = {
0338     GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
0339         ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
0340     GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66",
0341         ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0),
0342 
0343     GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
0344         ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
0345     GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
0346         ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
0347     GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
0348         ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
0349 
0350     GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
0351         ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
0352     GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
0353         ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
0354 
0355     GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
0356         ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
0357     GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
0358         ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
0359     GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
0360         ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
0361     GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
0362         ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
0363     GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
0364         ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
0365     GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
0366         ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
0367     GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
0368         ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
0369 };
0370 
0371 static const struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initconst = {
0372     FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user",
0373         1, 2, 0),
0374     FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user",
0375         1, 2, 0),
0376     FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0),
0377     FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0),
0378 };
0379 
0380 static const struct samsung_cmu_info top0_cmu_info __initconst = {
0381     .mux_clks       = top0_mux_clks,
0382     .nr_mux_clks        = ARRAY_SIZE(top0_mux_clks),
0383     .div_clks       = top0_div_clks,
0384     .nr_div_clks        = ARRAY_SIZE(top0_div_clks),
0385     .gate_clks      = top0_gate_clks,
0386     .nr_gate_clks       = ARRAY_SIZE(top0_gate_clks),
0387     .fixed_factor_clks  = top0_fixed_factor_clks,
0388     .nr_fixed_factor_clks   = ARRAY_SIZE(top0_fixed_factor_clks),
0389     .nr_clk_ids     = TOP0_NR_CLK,
0390     .clk_regs       = top0_clk_regs,
0391     .nr_clk_regs        = ARRAY_SIZE(top0_clk_regs),
0392 };
0393 
0394 static void __init exynos7_clk_top0_init(struct device_node *np)
0395 {
0396     samsung_cmu_register_one(np, &top0_cmu_info);
0397 }
0398 
0399 CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
0400     exynos7_clk_top0_init);
0401 
0402 /* Register Offset definitions for CMU_TOP1 (0x105E0000) */
0403 #define MUX_SEL_TOP10           0x0200
0404 #define MUX_SEL_TOP11           0x0204
0405 #define MUX_SEL_TOP13           0x020C
0406 #define MUX_SEL_TOP1_FSYS0      0x0224
0407 #define MUX_SEL_TOP1_FSYS1      0x0228
0408 #define MUX_SEL_TOP1_FSYS11     0x022C
0409 #define DIV_TOP13           0x060C
0410 #define DIV_TOP1_FSYS0          0x0624
0411 #define DIV_TOP1_FSYS1          0x0628
0412 #define DIV_TOP1_FSYS11         0x062C
0413 #define ENABLE_ACLK_TOP13       0x080C
0414 #define ENABLE_SCLK_TOP1_FSYS0      0x0A24
0415 #define ENABLE_SCLK_TOP1_FSYS1      0x0A28
0416 #define ENABLE_SCLK_TOP1_FSYS11     0x0A2C
0417 
0418 /* List of parent clocks for Muxes in CMU_TOP1 */
0419 PNAME(mout_top1_bus0_pll_user_p)    = { "fin_pll", "sclk_bus0_pll_b" };
0420 PNAME(mout_top1_bus1_pll_user_p)    = { "fin_pll", "sclk_bus1_pll_b" };
0421 PNAME(mout_top1_cc_pll_user_p)  = { "fin_pll", "sclk_cc_pll_b" };
0422 PNAME(mout_top1_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_b" };
0423 
0424 PNAME(mout_top1_bus0_pll_half_p) = {"mout_top1_bus0_pll_user",
0425     "ffac_top1_bus0_pll_div2"};
0426 PNAME(mout_top1_bus1_pll_half_p) = {"mout_top1_bus1_pll_user",
0427     "ffac_top1_bus1_pll_div2"};
0428 PNAME(mout_top1_cc_pll_half_p) = {"mout_top1_cc_pll_user",
0429     "ffac_top1_cc_pll_div2"};
0430 PNAME(mout_top1_mfc_pll_half_p) = {"mout_top1_mfc_pll_user",
0431     "ffac_top1_mfc_pll_div2"};
0432 
0433 PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half",
0434     "mout_top1_bus1_pll_half", "mout_top1_cc_pll_half",
0435     "mout_top1_mfc_pll_half"};
0436 
0437 static const unsigned long top1_clk_regs[] __initconst = {
0438     MUX_SEL_TOP10,
0439     MUX_SEL_TOP11,
0440     MUX_SEL_TOP13,
0441     MUX_SEL_TOP1_FSYS0,
0442     MUX_SEL_TOP1_FSYS1,
0443     MUX_SEL_TOP1_FSYS11,
0444     DIV_TOP13,
0445     DIV_TOP1_FSYS0,
0446     DIV_TOP1_FSYS1,
0447     DIV_TOP1_FSYS11,
0448     ENABLE_ACLK_TOP13,
0449     ENABLE_SCLK_TOP1_FSYS0,
0450     ENABLE_SCLK_TOP1_FSYS1,
0451     ENABLE_SCLK_TOP1_FSYS11,
0452 };
0453 
0454 static const struct samsung_mux_clock top1_mux_clks[] __initconst = {
0455     MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p,
0456         MUX_SEL_TOP10, 4, 1),
0457     MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p,
0458         MUX_SEL_TOP10, 8, 1),
0459     MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p,
0460         MUX_SEL_TOP10, 12, 1),
0461     MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p,
0462         MUX_SEL_TOP10, 16, 1),
0463 
0464     MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p,
0465         MUX_SEL_TOP11, 4, 1),
0466     MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p,
0467         MUX_SEL_TOP11, 8, 1),
0468     MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p,
0469         MUX_SEL_TOP11, 12, 1),
0470     MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p,
0471         MUX_SEL_TOP11, 16, 1),
0472 
0473     MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
0474     MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
0475 
0476     MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
0477         MUX_SEL_TOP1_FSYS0, 0, 2),
0478     MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
0479     MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
0480         MUX_SEL_TOP1_FSYS0, 28, 2),
0481 
0482     MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
0483         MUX_SEL_TOP1_FSYS1, 0, 2),
0484     MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
0485         MUX_SEL_TOP1_FSYS1, 16, 2),
0486 
0487     MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
0488     MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
0489     MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1,
0490         MUX_SEL_TOP1_FSYS11, 24, 2),
0491 };
0492 
0493 static const struct samsung_div_clock top1_div_clks[] __initconst = {
0494     DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
0495         DIV_TOP13, 24, 4),
0496     DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
0497         DIV_TOP13, 28, 4),
0498 
0499     DIV(DOUT_SCLK_PHY_FSYS1, "dout_sclk_phy_fsys1",
0500         "mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6),
0501 
0502     DIV(DOUT_SCLK_UFSUNIPRO20, "dout_sclk_ufsunipro20",
0503         "mout_sclk_ufsunipro20",
0504         DIV_TOP1_FSYS1, 16, 6),
0505 
0506     DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
0507         DIV_TOP1_FSYS0, 16, 10),
0508     DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
0509         DIV_TOP1_FSYS0, 28, 4),
0510 
0511     DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
0512         DIV_TOP1_FSYS11, 0, 10),
0513     DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
0514         DIV_TOP1_FSYS11, 12, 10),
0515 
0516     DIV(DOUT_SCLK_PHY_FSYS1_26M, "dout_sclk_phy_fsys1_26m",
0517         "mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6),
0518 };
0519 
0520 static const struct samsung_gate_clock top1_gate_clks[] __initconst = {
0521     GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
0522         ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),
0523     GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
0524         ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
0525 
0526     GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsys1",
0527         ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0),
0528 
0529     GATE(CLK_SCLK_UFSUNIPRO20, "sclk_ufsunipro20", "dout_sclk_ufsunipro20",
0530         ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0),
0531 
0532     GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
0533         ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
0534     GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
0535         ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
0536 
0537     GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200",
0538         ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT |
0539         CLK_IS_CRITICAL, 0),
0540     /*
0541      * This clock is required for the CMU_FSYS1 registers access, keep it
0542      * enabled permanently until proper runtime PM support is added.
0543      */
0544     GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
0545         ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT |
0546         CLK_IS_CRITICAL, 0),
0547 
0548     GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m",
0549         "dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11,
0550         24, CLK_SET_RATE_PARENT, 0),
0551 };
0552 
0553 static const struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initconst = {
0554     FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user",
0555         1, 2, 0),
0556     FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user",
0557         1, 2, 0),
0558     FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0),
0559     FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0),
0560 };
0561 
0562 static const struct samsung_cmu_info top1_cmu_info __initconst = {
0563     .mux_clks       = top1_mux_clks,
0564     .nr_mux_clks        = ARRAY_SIZE(top1_mux_clks),
0565     .div_clks       = top1_div_clks,
0566     .nr_div_clks        = ARRAY_SIZE(top1_div_clks),
0567     .gate_clks      = top1_gate_clks,
0568     .nr_gate_clks       = ARRAY_SIZE(top1_gate_clks),
0569     .fixed_factor_clks  = top1_fixed_factor_clks,
0570     .nr_fixed_factor_clks   = ARRAY_SIZE(top1_fixed_factor_clks),
0571     .nr_clk_ids     = TOP1_NR_CLK,
0572     .clk_regs       = top1_clk_regs,
0573     .nr_clk_regs        = ARRAY_SIZE(top1_clk_regs),
0574 };
0575 
0576 static void __init exynos7_clk_top1_init(struct device_node *np)
0577 {
0578     samsung_cmu_register_one(np, &top1_cmu_info);
0579 }
0580 
0581 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
0582     exynos7_clk_top1_init);
0583 
0584 /* Register Offset definitions for CMU_CCORE (0x105B0000) */
0585 #define MUX_SEL_CCORE           0x0200
0586 #define DIV_CCORE           0x0600
0587 #define ENABLE_ACLK_CCORE0      0x0800
0588 #define ENABLE_ACLK_CCORE1      0x0804
0589 #define ENABLE_PCLK_CCORE       0x0900
0590 
0591 /*
0592  * List of parent clocks for Muxes in CMU_CCORE
0593  */
0594 PNAME(mout_aclk_ccore_133_user_p)   = { "fin_pll", "aclk_ccore_133" };
0595 
0596 static const unsigned long ccore_clk_regs[] __initconst = {
0597     MUX_SEL_CCORE,
0598     ENABLE_PCLK_CCORE,
0599 };
0600 
0601 static const struct samsung_mux_clock ccore_mux_clks[] __initconst = {
0602     MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
0603         MUX_SEL_CCORE, 1, 1),
0604 };
0605 
0606 static const struct samsung_gate_clock ccore_gate_clks[] __initconst = {
0607     GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
0608         ENABLE_PCLK_CCORE, 8, 0, 0),
0609 };
0610 
0611 static const struct samsung_cmu_info ccore_cmu_info __initconst = {
0612     .mux_clks       = ccore_mux_clks,
0613     .nr_mux_clks        = ARRAY_SIZE(ccore_mux_clks),
0614     .gate_clks      = ccore_gate_clks,
0615     .nr_gate_clks       = ARRAY_SIZE(ccore_gate_clks),
0616     .nr_clk_ids     = CCORE_NR_CLK,
0617     .clk_regs       = ccore_clk_regs,
0618     .nr_clk_regs        = ARRAY_SIZE(ccore_clk_regs),
0619 };
0620 
0621 static void __init exynos7_clk_ccore_init(struct device_node *np)
0622 {
0623     samsung_cmu_register_one(np, &ccore_cmu_info);
0624 }
0625 
0626 CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
0627     exynos7_clk_ccore_init);
0628 
0629 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
0630 #define MUX_SEL_PERIC0          0x0200
0631 #define ENABLE_PCLK_PERIC0      0x0900
0632 #define ENABLE_SCLK_PERIC0      0x0A00
0633 
0634 /* List of parent clocks for Muxes in CMU_PERIC0 */
0635 PNAME(mout_aclk_peric0_66_user_p)   = { "fin_pll", "aclk_peric0_66" };
0636 PNAME(mout_sclk_uart0_user_p)   = { "fin_pll", "sclk_uart0" };
0637 
0638 static const unsigned long peric0_clk_regs[] __initconst = {
0639     MUX_SEL_PERIC0,
0640     ENABLE_PCLK_PERIC0,
0641     ENABLE_SCLK_PERIC0,
0642 };
0643 
0644 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
0645     MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p,
0646         MUX_SEL_PERIC0, 0, 1),
0647     MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p,
0648         MUX_SEL_PERIC0, 16, 1),
0649 };
0650 
0651 static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
0652     GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
0653         ENABLE_PCLK_PERIC0, 8, 0, 0),
0654     GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
0655         ENABLE_PCLK_PERIC0, 9, 0, 0),
0656     GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
0657         ENABLE_PCLK_PERIC0, 10, 0, 0),
0658     GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
0659         ENABLE_PCLK_PERIC0, 11, 0, 0),
0660     GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
0661         ENABLE_PCLK_PERIC0, 12, 0, 0),
0662     GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
0663         ENABLE_PCLK_PERIC0, 13, 0, 0),
0664     GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
0665         ENABLE_PCLK_PERIC0, 14, 0, 0),
0666     GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
0667         ENABLE_PCLK_PERIC0, 16, 0, 0),
0668     GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
0669         ENABLE_PCLK_PERIC0, 20, 0, 0),
0670     GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
0671         ENABLE_PCLK_PERIC0, 21, 0, 0),
0672 
0673     GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
0674         ENABLE_SCLK_PERIC0, 16, 0, 0),
0675     GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
0676 };
0677 
0678 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
0679     .mux_clks       = peric0_mux_clks,
0680     .nr_mux_clks        = ARRAY_SIZE(peric0_mux_clks),
0681     .gate_clks      = peric0_gate_clks,
0682     .nr_gate_clks       = ARRAY_SIZE(peric0_gate_clks),
0683     .nr_clk_ids     = PERIC0_NR_CLK,
0684     .clk_regs       = peric0_clk_regs,
0685     .nr_clk_regs        = ARRAY_SIZE(peric0_clk_regs),
0686 };
0687 
0688 static void __init exynos7_clk_peric0_init(struct device_node *np)
0689 {
0690     samsung_cmu_register_one(np, &peric0_cmu_info);
0691 }
0692 
0693 /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
0694 #define MUX_SEL_PERIC10         0x0200
0695 #define MUX_SEL_PERIC11         0x0204
0696 #define MUX_SEL_PERIC12         0x0208
0697 #define ENABLE_PCLK_PERIC1      0x0900
0698 #define ENABLE_SCLK_PERIC10     0x0A00
0699 
0700 CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
0701     exynos7_clk_peric0_init);
0702 
0703 /* List of parent clocks for Muxes in CMU_PERIC1 */
0704 PNAME(mout_aclk_peric1_66_user_p)   = { "fin_pll", "aclk_peric1_66" };
0705 PNAME(mout_sclk_uart1_user_p)   = { "fin_pll", "sclk_uart1" };
0706 PNAME(mout_sclk_uart2_user_p)   = { "fin_pll", "sclk_uart2" };
0707 PNAME(mout_sclk_uart3_user_p)   = { "fin_pll", "sclk_uart3" };
0708 PNAME(mout_sclk_spi0_user_p)        = { "fin_pll", "sclk_spi0" };
0709 PNAME(mout_sclk_spi1_user_p)        = { "fin_pll", "sclk_spi1" };
0710 PNAME(mout_sclk_spi2_user_p)        = { "fin_pll", "sclk_spi2" };
0711 PNAME(mout_sclk_spi3_user_p)        = { "fin_pll", "sclk_spi3" };
0712 PNAME(mout_sclk_spi4_user_p)        = { "fin_pll", "sclk_spi4" };
0713 
0714 static const unsigned long peric1_clk_regs[] __initconst = {
0715     MUX_SEL_PERIC10,
0716     MUX_SEL_PERIC11,
0717     MUX_SEL_PERIC12,
0718     ENABLE_PCLK_PERIC1,
0719     ENABLE_SCLK_PERIC10,
0720 };
0721 
0722 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
0723     MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p,
0724         MUX_SEL_PERIC10, 0, 1),
0725 
0726     MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p,
0727         MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
0728     MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p,
0729         MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
0730     MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p,
0731         MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
0732     MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p,
0733         MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
0734     MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p,
0735         MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
0736     MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p,
0737         MUX_SEL_PERIC11, 20, 1),
0738     MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p,
0739         MUX_SEL_PERIC11, 24, 1),
0740     MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p,
0741         MUX_SEL_PERIC11, 28, 1),
0742 };
0743 
0744 static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
0745     GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
0746         ENABLE_PCLK_PERIC1, 4, 0, 0),
0747     GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
0748         ENABLE_PCLK_PERIC1, 5, 0, 0),
0749     GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
0750         ENABLE_PCLK_PERIC1, 6, 0, 0),
0751     GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
0752         ENABLE_PCLK_PERIC1, 7, 0, 0),
0753     GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
0754         ENABLE_PCLK_PERIC1, 8, 0, 0),
0755     GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
0756         ENABLE_PCLK_PERIC1, 9, 0, 0),
0757     GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
0758         ENABLE_PCLK_PERIC1, 10, 0, 0),
0759     GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
0760         ENABLE_PCLK_PERIC1, 11, 0, 0),
0761     GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
0762         ENABLE_PCLK_PERIC1, 12, 0, 0),
0763     GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
0764         ENABLE_PCLK_PERIC1, 13, 0, 0),
0765     GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
0766         ENABLE_PCLK_PERIC1, 14, 0, 0),
0767     GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
0768         ENABLE_PCLK_PERIC1, 15, 0, 0),
0769     GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
0770         ENABLE_PCLK_PERIC1, 16, 0, 0),
0771     GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user",
0772         ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
0773     GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user",
0774         ENABLE_PCLK_PERIC1, 18, 0, 0),
0775     GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user",
0776         ENABLE_PCLK_PERIC1, 19, 0, 0),
0777 
0778     GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
0779         ENABLE_SCLK_PERIC10, 9, 0, 0),
0780     GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
0781         ENABLE_SCLK_PERIC10, 10, 0, 0),
0782     GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
0783         ENABLE_SCLK_PERIC10, 11, 0, 0),
0784     GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
0785         ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
0786     GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
0787         ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
0788     GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
0789         ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
0790     GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
0791         ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
0792     GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
0793         ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
0794     GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
0795         ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0),
0796     GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1",
0797         ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0),
0798     GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif",
0799         ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0),
0800 };
0801 
0802 static const struct samsung_cmu_info peric1_cmu_info __initconst = {
0803     .mux_clks       = peric1_mux_clks,
0804     .nr_mux_clks        = ARRAY_SIZE(peric1_mux_clks),
0805     .gate_clks      = peric1_gate_clks,
0806     .nr_gate_clks       = ARRAY_SIZE(peric1_gate_clks),
0807     .nr_clk_ids     = PERIC1_NR_CLK,
0808     .clk_regs       = peric1_clk_regs,
0809     .nr_clk_regs        = ARRAY_SIZE(peric1_clk_regs),
0810 };
0811 
0812 static void __init exynos7_clk_peric1_init(struct device_node *np)
0813 {
0814     samsung_cmu_register_one(np, &peric1_cmu_info);
0815 }
0816 
0817 CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
0818     exynos7_clk_peric1_init);
0819 
0820 /* Register Offset definitions for CMU_PERIS (0x10040000) */
0821 #define MUX_SEL_PERIS           0x0200
0822 #define ENABLE_PCLK_PERIS       0x0900
0823 #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
0824 #define ENABLE_SCLK_PERIS       0x0A00
0825 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
0826 
0827 /* List of parent clocks for Muxes in CMU_PERIS */
0828 PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" };
0829 
0830 static const unsigned long peris_clk_regs[] __initconst = {
0831     MUX_SEL_PERIS,
0832     ENABLE_PCLK_PERIS,
0833     ENABLE_PCLK_PERIS_SECURE_CHIPID,
0834     ENABLE_SCLK_PERIS,
0835     ENABLE_SCLK_PERIS_SECURE_CHIPID,
0836 };
0837 
0838 static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
0839     MUX(0, "mout_aclk_peris_66_user",
0840         mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1),
0841 };
0842 
0843 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
0844     GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
0845         ENABLE_PCLK_PERIS, 6, 0, 0),
0846     GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
0847         ENABLE_PCLK_PERIS, 10, 0, 0),
0848 
0849     GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
0850         ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
0851     GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
0852         ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
0853 
0854     GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
0855 };
0856 
0857 static const struct samsung_cmu_info peris_cmu_info __initconst = {
0858     .mux_clks       = peris_mux_clks,
0859     .nr_mux_clks        = ARRAY_SIZE(peris_mux_clks),
0860     .gate_clks      = peris_gate_clks,
0861     .nr_gate_clks       = ARRAY_SIZE(peris_gate_clks),
0862     .nr_clk_ids     = PERIS_NR_CLK,
0863     .clk_regs       = peris_clk_regs,
0864     .nr_clk_regs        = ARRAY_SIZE(peris_clk_regs),
0865 };
0866 
0867 static void __init exynos7_clk_peris_init(struct device_node *np)
0868 {
0869     samsung_cmu_register_one(np, &peris_cmu_info);
0870 }
0871 
0872 CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
0873     exynos7_clk_peris_init);
0874 
0875 /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
0876 #define MUX_SEL_FSYS00          0x0200
0877 #define MUX_SEL_FSYS01          0x0204
0878 #define MUX_SEL_FSYS02          0x0208
0879 #define ENABLE_ACLK_FSYS00      0x0800
0880 #define ENABLE_ACLK_FSYS01      0x0804
0881 #define ENABLE_SCLK_FSYS01      0x0A04
0882 #define ENABLE_SCLK_FSYS02      0x0A08
0883 #define ENABLE_SCLK_FSYS04      0x0A10
0884 
0885 /*
0886  * List of parent clocks for Muxes in CMU_FSYS0
0887  */
0888 PNAME(mout_aclk_fsys0_200_user_p)   = { "fin_pll", "aclk_fsys0_200" };
0889 PNAME(mout_sclk_mmc2_user_p)        = { "fin_pll", "sclk_mmc2" };
0890 
0891 PNAME(mout_sclk_usbdrd300_user_p)   = { "fin_pll", "sclk_usbdrd300" };
0892 PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p)   = { "fin_pll",
0893                 "phyclk_usbdrd300_udrd30_phyclock" };
0894 PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p)    = { "fin_pll",
0895                 "phyclk_usbdrd300_udrd30_pipe_pclk" };
0896 
0897 /* fixed rate clocks used in the FSYS0 block */
0898 static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initconst = {
0899     FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000),
0900     FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000),
0901 };
0902 
0903 static const unsigned long fsys0_clk_regs[] __initconst = {
0904     MUX_SEL_FSYS00,
0905     MUX_SEL_FSYS01,
0906     MUX_SEL_FSYS02,
0907     ENABLE_ACLK_FSYS00,
0908     ENABLE_ACLK_FSYS01,
0909     ENABLE_SCLK_FSYS01,
0910     ENABLE_SCLK_FSYS02,
0911     ENABLE_SCLK_FSYS04,
0912 };
0913 
0914 static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
0915     MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p,
0916         MUX_SEL_FSYS00, 24, 1),
0917 
0918     MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p,
0919         MUX_SEL_FSYS01, 24, 1),
0920     MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p,
0921         MUX_SEL_FSYS01, 28, 1),
0922 
0923     MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
0924         mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p,
0925         MUX_SEL_FSYS02, 24, 1),
0926     MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
0927         mout_phyclk_usbdrd300_udrd30_phyclk_user_p,
0928         MUX_SEL_FSYS02, 28, 1),
0929 };
0930 
0931 static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
0932     GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
0933             ENABLE_ACLK_FSYS00, 3, 0, 0),
0934     GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
0935             ENABLE_ACLK_FSYS00, 4, 0, 0),
0936     GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
0937         "mout_aclk_fsys0_200_user",
0938         ENABLE_ACLK_FSYS00, 19, 0, 0),
0939 
0940     GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
0941         ENABLE_ACLK_FSYS01, 29, 0, 0),
0942     GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
0943         ENABLE_ACLK_FSYS01, 31, 0, 0),
0944 
0945     GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk",
0946         "mout_sclk_usbdrd300_user",
0947         ENABLE_SCLK_FSYS01, 4, 0, 0),
0948     GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll",
0949         ENABLE_SCLK_FSYS01, 8, 0, 0),
0950 
0951     GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
0952         "phyclk_usbdrd300_udrd30_pipe_pclk_user",
0953         "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
0954         ENABLE_SCLK_FSYS02, 24, 0, 0),
0955     GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
0956         "phyclk_usbdrd300_udrd30_phyclk_user",
0957         "mout_phyclk_usbdrd300_udrd30_phyclk_user",
0958         ENABLE_SCLK_FSYS02, 28, 0, 0),
0959 
0960     GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy",
0961         "fin_pll",
0962         ENABLE_SCLK_FSYS04, 28, 0, 0),
0963 };
0964 
0965 static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
0966     .fixed_clks     = fixed_rate_clks_fsys0,
0967     .nr_fixed_clks      = ARRAY_SIZE(fixed_rate_clks_fsys0),
0968     .mux_clks       = fsys0_mux_clks,
0969     .nr_mux_clks        = ARRAY_SIZE(fsys0_mux_clks),
0970     .gate_clks      = fsys0_gate_clks,
0971     .nr_gate_clks       = ARRAY_SIZE(fsys0_gate_clks),
0972     .nr_clk_ids     = FSYS0_NR_CLK,
0973     .clk_regs       = fsys0_clk_regs,
0974     .nr_clk_regs        = ARRAY_SIZE(fsys0_clk_regs),
0975 };
0976 
0977 static void __init exynos7_clk_fsys0_init(struct device_node *np)
0978 {
0979     samsung_cmu_register_one(np, &fsys0_cmu_info);
0980 }
0981 
0982 CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
0983     exynos7_clk_fsys0_init);
0984 
0985 /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
0986 #define MUX_SEL_FSYS10          0x0200
0987 #define MUX_SEL_FSYS11          0x0204
0988 #define MUX_SEL_FSYS12          0x0208
0989 #define DIV_FSYS1           0x0600
0990 #define ENABLE_ACLK_FSYS1       0x0800
0991 #define ENABLE_PCLK_FSYS1               0x0900
0992 #define ENABLE_SCLK_FSYS11              0x0A04
0993 #define ENABLE_SCLK_FSYS12              0x0A08
0994 #define ENABLE_SCLK_FSYS13              0x0A0C
0995 
0996 /*
0997  * List of parent clocks for Muxes in CMU_FSYS1
0998  */
0999 PNAME(mout_aclk_fsys1_200_user_p)   = { "fin_pll", "aclk_fsys1_200" };
1000 PNAME(mout_fsys1_group_p)   = { "fin_pll", "fin_pll_26m",
1001                 "sclk_phy_fsys1_26m" };
1002 PNAME(mout_sclk_mmc0_user_p)        = { "fin_pll", "sclk_mmc0" };
1003 PNAME(mout_sclk_mmc1_user_p)        = { "fin_pll", "sclk_mmc1" };
1004 PNAME(mout_sclk_ufsunipro20_user_p)  = { "fin_pll", "sclk_ufsunipro20" };
1005 PNAME(mout_phyclk_ufs20_tx0_user_p) = { "fin_pll", "phyclk_ufs20_tx0_symbol" };
1006 PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" };
1007 PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" };
1008 
1009 /* fixed rate clocks used in the FSYS1 block */
1010 static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initconst = {
1011     FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL,
1012             0, 300000000),
1013     FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL,
1014             0, 300000000),
1015     FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol", NULL,
1016             0, 300000000),
1017 };
1018 
1019 static const unsigned long fsys1_clk_regs[] __initconst = {
1020     MUX_SEL_FSYS10,
1021     MUX_SEL_FSYS11,
1022     MUX_SEL_FSYS12,
1023     DIV_FSYS1,
1024     ENABLE_ACLK_FSYS1,
1025     ENABLE_PCLK_FSYS1,
1026     ENABLE_SCLK_FSYS11,
1027     ENABLE_SCLK_FSYS12,
1028     ENABLE_SCLK_FSYS13,
1029 };
1030 
1031 static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
1032     MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1",
1033         mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2),
1034     MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p,
1035          MUX_SEL_FSYS10, 20, 2),
1036     MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p,
1037         MUX_SEL_FSYS10, 28, 1),
1038 
1039     MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p,
1040         MUX_SEL_FSYS11, 24, 1),
1041     MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p,
1042         MUX_SEL_FSYS11, 28, 1),
1043     MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p,
1044         MUX_SEL_FSYS11, 20, 1),
1045 
1046     MUX(0, "mout_phyclk_ufs20_rx1_symbol_user",
1047         mout_phyclk_ufs20_rx1_user_p, MUX_SEL_FSYS12, 16, 1),
1048     MUX(0, "mout_phyclk_ufs20_rx0_symbol_user",
1049         mout_phyclk_ufs20_rx0_user_p, MUX_SEL_FSYS12, 24, 1),
1050     MUX(0, "mout_phyclk_ufs20_tx0_symbol_user",
1051         mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1),
1052 };
1053 
1054 static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
1055     DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user",
1056         DIV_FSYS1, 0, 2),
1057 };
1058 
1059 static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
1060     GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user",
1061         "mout_sclk_ufsunipro20_user",
1062         ENABLE_SCLK_FSYS11, 20, 0, 0),
1063 
1064     GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
1065         ENABLE_ACLK_FSYS1, 29, 0, 0),
1066     GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
1067         ENABLE_ACLK_FSYS1, 30, 0, 0),
1068 
1069     GATE(ACLK_UFS20_LINK, "aclk_ufs20_link", "dout_pclk_fsys1",
1070         ENABLE_ACLK_FSYS1, 31, 0, 0),
1071     GATE(PCLK_GPIO_FSYS1, "pclk_gpio_fsys1", "mout_aclk_fsys1_200_user",
1072         ENABLE_PCLK_FSYS1, 30, 0, 0),
1073 
1074     GATE(PHYCLK_UFS20_RX1_SYMBOL_USER, "phyclk_ufs20_rx1_symbol_user",
1075         "mout_phyclk_ufs20_rx1_symbol_user",
1076         ENABLE_SCLK_FSYS12, 16, 0, 0),
1077     GATE(PHYCLK_UFS20_RX0_SYMBOL_USER, "phyclk_ufs20_rx0_symbol_user",
1078         "mout_phyclk_ufs20_rx0_symbol_user",
1079         ENABLE_SCLK_FSYS12, 24, 0, 0),
1080     GATE(PHYCLK_UFS20_TX0_SYMBOL_USER, "phyclk_ufs20_tx0_symbol_user",
1081         "mout_phyclk_ufs20_tx0_symbol_user",
1082         ENABLE_SCLK_FSYS12, 28, 0, 0),
1083 
1084     GATE(OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY,
1085         "oscclk_phy_clkout_embedded_combo_phy",
1086         "fin_pll",
1087         ENABLE_SCLK_FSYS12, 4, CLK_IGNORE_UNUSED, 0),
1088 
1089     GATE(SCLK_COMBO_PHY_EMBEDDED_26M, "sclk_combo_phy_embedded_26m",
1090         "mout_fsys1_phyclk_sel1",
1091         ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0),
1092 };
1093 
1094 static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
1095     .fixed_clks     = fixed_rate_clks_fsys1,
1096     .nr_fixed_clks      = ARRAY_SIZE(fixed_rate_clks_fsys1),
1097     .mux_clks       = fsys1_mux_clks,
1098     .nr_mux_clks        = ARRAY_SIZE(fsys1_mux_clks),
1099     .div_clks       = fsys1_div_clks,
1100     .nr_div_clks        = ARRAY_SIZE(fsys1_div_clks),
1101     .gate_clks      = fsys1_gate_clks,
1102     .nr_gate_clks       = ARRAY_SIZE(fsys1_gate_clks),
1103     .nr_clk_ids     = FSYS1_NR_CLK,
1104     .clk_regs       = fsys1_clk_regs,
1105     .nr_clk_regs        = ARRAY_SIZE(fsys1_clk_regs),
1106 };
1107 
1108 static void __init exynos7_clk_fsys1_init(struct device_node *np)
1109 {
1110     samsung_cmu_register_one(np, &fsys1_cmu_info);
1111 }
1112 
1113 CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
1114     exynos7_clk_fsys1_init);
1115 
1116 #define MUX_SEL_MSCL            0x0200
1117 #define DIV_MSCL            0x0600
1118 #define ENABLE_ACLK_MSCL        0x0800
1119 #define ENABLE_PCLK_MSCL        0x0900
1120 
1121 /* List of parent clocks for Muxes in CMU_MSCL */
1122 PNAME(mout_aclk_mscl_532_user_p)    = { "fin_pll", "aclk_mscl_532" };
1123 
1124 static const unsigned long mscl_clk_regs[] __initconst = {
1125     MUX_SEL_MSCL,
1126     DIV_MSCL,
1127     ENABLE_ACLK_MSCL,
1128     ENABLE_PCLK_MSCL,
1129 };
1130 
1131 static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
1132     MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532",
1133         mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
1134 };
1135 static const struct samsung_div_clock mscl_div_clks[] __initconst = {
1136     DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532",
1137             DIV_MSCL, 0, 3),
1138 };
1139 static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
1140 
1141     GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532",
1142             ENABLE_ACLK_MSCL, 31, 0, 0),
1143     GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532",
1144             ENABLE_ACLK_MSCL, 30, 0, 0),
1145     GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532",
1146             ENABLE_ACLK_MSCL, 29, 0, 0),
1147     GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532",
1148             ENABLE_ACLK_MSCL, 28, 0, 0),
1149     GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0",
1150             "usermux_aclk_mscl_532",
1151             ENABLE_ACLK_MSCL, 27, 0, 0),
1152     GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1",
1153             "usermux_aclk_mscl_532",
1154             ENABLE_ACLK_MSCL, 26, 0, 0),
1155     GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532",
1156             ENABLE_ACLK_MSCL, 25, 0, 0),
1157     GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532",
1158             ENABLE_ACLK_MSCL, 24, 0, 0),
1159     GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge",
1160             "usermux_aclk_mscl_532",
1161             ENABLE_ACLK_MSCL, 23, 0, 0),
1162     GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532",
1163             ENABLE_ACLK_MSCL, 22, 0, 0),
1164     GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532",
1165             ENABLE_ACLK_MSCL, 21, 0, 0),
1166     GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532",
1167             ENABLE_ACLK_MSCL, 20, 0, 0),
1168     GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532",
1169             ENABLE_ACLK_MSCL, 19, 0, 0),
1170     GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532",
1171             ENABLE_ACLK_MSCL, 18, 0, 0),
1172     GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532",
1173             ENABLE_ACLK_MSCL, 17, 0, 0),
1174     GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532",
1175             ENABLE_ACLK_MSCL, 16, 0, 0),
1176     GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p",
1177             "usermux_aclk_mscl_532",
1178             ENABLE_ACLK_MSCL, 15, 0, 0),
1179     GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p",
1180             "usermux_aclk_mscl_532",
1181             ENABLE_ACLK_MSCL, 14, 0, 0),
1182 
1183     GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl",
1184             ENABLE_PCLK_MSCL, 31, 0, 0),
1185     GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl",
1186             ENABLE_PCLK_MSCL, 30, 0, 0),
1187     GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl",
1188             ENABLE_PCLK_MSCL, 29, 0, 0),
1189     GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl",
1190             ENABLE_PCLK_MSCL, 28, 0, 0),
1191     GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl",
1192             ENABLE_PCLK_MSCL, 27, 0, 0),
1193     GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl",
1194             ENABLE_PCLK_MSCL, 26, 0, 0),
1195     GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl",
1196             ENABLE_PCLK_MSCL, 25, 0, 0),
1197     GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl",
1198             ENABLE_PCLK_MSCL, 24, 0, 0),
1199     GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl",
1200             ENABLE_PCLK_MSCL, 23, 0, 0),
1201     GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl",
1202             ENABLE_PCLK_MSCL, 22, 0, 0),
1203     GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl",
1204             ENABLE_PCLK_MSCL, 21, 0, 0),
1205     GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl",
1206             ENABLE_PCLK_MSCL, 20, 0, 0),
1207 };
1208 
1209 static const struct samsung_cmu_info mscl_cmu_info __initconst = {
1210     .mux_clks       = mscl_mux_clks,
1211     .nr_mux_clks        = ARRAY_SIZE(mscl_mux_clks),
1212     .div_clks       = mscl_div_clks,
1213     .nr_div_clks        = ARRAY_SIZE(mscl_div_clks),
1214     .gate_clks      = mscl_gate_clks,
1215     .nr_gate_clks       = ARRAY_SIZE(mscl_gate_clks),
1216     .nr_clk_ids     = MSCL_NR_CLK,
1217     .clk_regs       = mscl_clk_regs,
1218     .nr_clk_regs        = ARRAY_SIZE(mscl_clk_regs),
1219 };
1220 
1221 static void __init exynos7_clk_mscl_init(struct device_node *np)
1222 {
1223     samsung_cmu_register_one(np, &mscl_cmu_info);
1224 }
1225 
1226 CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl",
1227         exynos7_clk_mscl_init);
1228 
1229 /* Register Offset definitions for CMU_AUD (0x114C0000) */
1230 #define MUX_SEL_AUD         0x0200
1231 #define DIV_AUD0            0x0600
1232 #define DIV_AUD1            0x0604
1233 #define ENABLE_ACLK_AUD         0x0800
1234 #define ENABLE_PCLK_AUD         0x0900
1235 #define ENABLE_SCLK_AUD         0x0A00
1236 
1237 /*
1238  * List of parent clocks for Muxes in CMU_AUD
1239  */
1240 PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };
1241 PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" };
1242 
1243 static const unsigned long aud_clk_regs[] __initconst = {
1244     MUX_SEL_AUD,
1245     DIV_AUD0,
1246     DIV_AUD1,
1247     ENABLE_ACLK_AUD,
1248     ENABLE_PCLK_AUD,
1249     ENABLE_SCLK_AUD,
1250 };
1251 
1252 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
1253     MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
1254     MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
1255     MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
1256 };
1257 
1258 static const struct samsung_div_clock aud_div_clks[] __initconst = {
1259     DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
1260     DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
1261     DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
1262 
1263     DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4),
1264     DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8),
1265     DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4),
1266     DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5),
1267     DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
1268 };
1269 
1270 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
1271     GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
1272             ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1273     GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
1274             ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0),
1275     GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0),
1276     GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
1277             ENABLE_SCLK_AUD, 30, 0, 0),
1278 
1279     GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
1280     GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
1281     GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
1282     GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
1283     GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
1284     GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
1285     GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud",
1286             ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
1287     GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud",
1288             ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1289     GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
1290     GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),
1291 
1292     GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0),
1293     GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud",
1294              ENABLE_ACLK_AUD, 28, 0, 0),
1295     GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),
1296 };
1297 
1298 static const struct samsung_cmu_info aud_cmu_info __initconst = {
1299     .mux_clks       = aud_mux_clks,
1300     .nr_mux_clks        = ARRAY_SIZE(aud_mux_clks),
1301     .div_clks       = aud_div_clks,
1302     .nr_div_clks        = ARRAY_SIZE(aud_div_clks),
1303     .gate_clks      = aud_gate_clks,
1304     .nr_gate_clks       = ARRAY_SIZE(aud_gate_clks),
1305     .nr_clk_ids     = AUD_NR_CLK,
1306     .clk_regs       = aud_clk_regs,
1307     .nr_clk_regs        = ARRAY_SIZE(aud_clk_regs),
1308 };
1309 
1310 static void __init exynos7_clk_aud_init(struct device_node *np)
1311 {
1312     samsung_cmu_register_one(np, &aud_cmu_info);
1313 }
1314 
1315 CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud",
1316         exynos7_clk_aud_init);
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