clk/samsung/clk-exynos5433.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
0004  * Author: Chanwoo Choi <cw00.choi@samsung.com>
0005  *
0006  * Common Clock Framework support for Exynos5433 SoC.
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013 #include <linux/of_device.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/slab.h>
0017
0018 #include <dt-bindings/clock/exynos5433.h>
0019
0020 #include "clk.h"
0021 #include "clk-cpu.h"
0022 #include "clk-pll.h"
0023
0024 /*
0025  * Register offset definitions for CMU_TOP
0026  */
0027 #define ISP_PLL_LOCK            0x0000
0028 #define AUD_PLL_LOCK            0x0004
0029 #define ISP_PLL_CON0            0x0100
0030 #define ISP_PLL_CON1            0x0104
0031 #define ISP_PLL_FREQ_DET        0x0108
0032 #define AUD_PLL_CON0            0x0110
0033 #define AUD_PLL_CON1            0x0114
0034 #define AUD_PLL_CON2            0x0118
0035 #define AUD_PLL_FREQ_DET        0x011c
0036 #define MUX_SEL_TOP0            0x0200
0037 #define MUX_SEL_TOP1            0x0204
0038 #define MUX_SEL_TOP2            0x0208
0039 #define MUX_SEL_TOP3            0x020c
0040 #define MUX_SEL_TOP4            0x0210
0041 #define MUX_SEL_TOP_MSCL        0x0220
0042 #define MUX_SEL_TOP_CAM1        0x0224
0043 #define MUX_SEL_TOP_DISP        0x0228
0044 #define MUX_SEL_TOP_FSYS0       0x0230
0045 #define MUX_SEL_TOP_FSYS1       0x0234
0046 #define MUX_SEL_TOP_PERIC0      0x0238
0047 #define MUX_SEL_TOP_PERIC1      0x023c
0048 #define MUX_ENABLE_TOP0         0x0300
0049 #define MUX_ENABLE_TOP1         0x0304
0050 #define MUX_ENABLE_TOP2         0x0308
0051 #define MUX_ENABLE_TOP3         0x030c
0052 #define MUX_ENABLE_TOP4         0x0310
0053 #define MUX_ENABLE_TOP_MSCL     0x0320
0054 #define MUX_ENABLE_TOP_CAM1     0x0324
0055 #define MUX_ENABLE_TOP_DISP     0x0328
0056 #define MUX_ENABLE_TOP_FSYS0        0x0330
0057 #define MUX_ENABLE_TOP_FSYS1        0x0334
0058 #define MUX_ENABLE_TOP_PERIC0       0x0338
0059 #define MUX_ENABLE_TOP_PERIC1       0x033c
0060 #define MUX_STAT_TOP0           0x0400
0061 #define MUX_STAT_TOP1           0x0404
0062 #define MUX_STAT_TOP2           0x0408
0063 #define MUX_STAT_TOP3           0x040c
0064 #define MUX_STAT_TOP4           0x0410
0065 #define MUX_STAT_TOP_MSCL       0x0420
0066 #define MUX_STAT_TOP_CAM1       0x0424
0067 #define MUX_STAT_TOP_FSYS0      0x0430
0068 #define MUX_STAT_TOP_FSYS1      0x0434
0069 #define MUX_STAT_TOP_PERIC0     0x0438
0070 #define MUX_STAT_TOP_PERIC1     0x043c
0071 #define DIV_TOP0            0x0600
0072 #define DIV_TOP1            0x0604
0073 #define DIV_TOP2            0x0608
0074 #define DIV_TOP3            0x060c
0075 #define DIV_TOP4            0x0610
0076 #define DIV_TOP_MSCL            0x0618
0077 #define DIV_TOP_CAM10           0x061c
0078 #define DIV_TOP_CAM11           0x0620
0079 #define DIV_TOP_FSYS0           0x062c
0080 #define DIV_TOP_FSYS1           0x0630
0081 #define DIV_TOP_FSYS2           0x0634
0082 #define DIV_TOP_PERIC0          0x0638
0083 #define DIV_TOP_PERIC1          0x063c
0084 #define DIV_TOP_PERIC2          0x0640
0085 #define DIV_TOP_PERIC3          0x0644
0086 #define DIV_TOP_PERIC4          0x0648
0087 #define DIV_TOP_PLL_FREQ_DET        0x064c
0088 #define DIV_STAT_TOP0           0x0700
0089 #define DIV_STAT_TOP1           0x0704
0090 #define DIV_STAT_TOP2           0x0708
0091 #define DIV_STAT_TOP3           0x070c
0092 #define DIV_STAT_TOP4           0x0710
0093 #define DIV_STAT_TOP_MSCL       0x0718
0094 #define DIV_STAT_TOP_CAM10      0x071c
0095 #define DIV_STAT_TOP_CAM11      0x0720
0096 #define DIV_STAT_TOP_FSYS0      0x072c
0097 #define DIV_STAT_TOP_FSYS1      0x0730
0098 #define DIV_STAT_TOP_FSYS2      0x0734
0099 #define DIV_STAT_TOP_PERIC0     0x0738
0100 #define DIV_STAT_TOP_PERIC1     0x073c
0101 #define DIV_STAT_TOP_PERIC2     0x0740
0102 #define DIV_STAT_TOP_PERIC3     0x0744
0103 #define DIV_STAT_TOP_PLL_FREQ_DET   0x074c
0104 #define ENABLE_ACLK_TOP         0x0800
0105 #define ENABLE_SCLK_TOP         0x0a00
0106 #define ENABLE_SCLK_TOP_MSCL        0x0a04
0107 #define ENABLE_SCLK_TOP_CAM1        0x0a08
0108 #define ENABLE_SCLK_TOP_DISP        0x0a0c
0109 #define ENABLE_SCLK_TOP_FSYS        0x0a10
0110 #define ENABLE_SCLK_TOP_PERIC       0x0a14
0111 #define ENABLE_IP_TOP           0x0b00
0112 #define ENABLE_CMU_TOP          0x0c00
0113 #define ENABLE_CMU_TOP_DIV_STAT     0x0c04
0114
0115 static const unsigned long top_clk_regs[] __initconst = {
0116     ISP_PLL_LOCK,
0117     AUD_PLL_LOCK,
0118     ISP_PLL_CON0,
0119     ISP_PLL_CON1,
0120     ISP_PLL_FREQ_DET,
0121     AUD_PLL_CON0,
0122     AUD_PLL_CON1,
0123     AUD_PLL_CON2,
0124     AUD_PLL_FREQ_DET,
0125     MUX_SEL_TOP0,
0126     MUX_SEL_TOP1,
0127     MUX_SEL_TOP2,
0128     MUX_SEL_TOP3,
0129     MUX_SEL_TOP4,
0130     MUX_SEL_TOP_MSCL,
0131     MUX_SEL_TOP_CAM1,
0132     MUX_SEL_TOP_DISP,
0133     MUX_SEL_TOP_FSYS0,
0134     MUX_SEL_TOP_FSYS1,
0135     MUX_SEL_TOP_PERIC0,
0136     MUX_SEL_TOP_PERIC1,
0137     MUX_ENABLE_TOP0,
0138     MUX_ENABLE_TOP1,
0139     MUX_ENABLE_TOP2,
0140     MUX_ENABLE_TOP3,
0141     MUX_ENABLE_TOP4,
0142     MUX_ENABLE_TOP_MSCL,
0143     MUX_ENABLE_TOP_CAM1,
0144     MUX_ENABLE_TOP_DISP,
0145     MUX_ENABLE_TOP_FSYS0,
0146     MUX_ENABLE_TOP_FSYS1,
0147     MUX_ENABLE_TOP_PERIC0,
0148     MUX_ENABLE_TOP_PERIC1,
0149     DIV_TOP0,
0150     DIV_TOP1,
0151     DIV_TOP2,
0152     DIV_TOP3,
0153     DIV_TOP4,
0154     DIV_TOP_MSCL,
0155     DIV_TOP_CAM10,
0156     DIV_TOP_CAM11,
0157     DIV_TOP_FSYS0,
0158     DIV_TOP_FSYS1,
0159     DIV_TOP_FSYS2,
0160     DIV_TOP_PERIC0,
0161     DIV_TOP_PERIC1,
0162     DIV_TOP_PERIC2,
0163     DIV_TOP_PERIC3,
0164     DIV_TOP_PERIC4,
0165     DIV_TOP_PLL_FREQ_DET,
0166     ENABLE_ACLK_TOP,
0167     ENABLE_SCLK_TOP,
0168     ENABLE_SCLK_TOP_MSCL,
0169     ENABLE_SCLK_TOP_CAM1,
0170     ENABLE_SCLK_TOP_DISP,
0171     ENABLE_SCLK_TOP_FSYS,
0172     ENABLE_SCLK_TOP_PERIC,
0173     ENABLE_IP_TOP,
0174     ENABLE_CMU_TOP,
0175     ENABLE_CMU_TOP_DIV_STAT,
0176 };
0177
0178 static const struct samsung_clk_reg_dump top_suspend_regs[] = {
0179     /* force all aclk clocks enabled */
0180     { ENABLE_ACLK_TOP, 0x67ecffed },
0181     /* force all sclk_uart clocks enabled */
0182     { ENABLE_SCLK_TOP_PERIC, 0x38 },
0183     /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
0184     { ISP_PLL_CON0, 0x85cc0502 },
0185     /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
0186     { AUD_PLL_CON0, 0x84830202 },
0187 };
0188
0189 /* list of all parent clock list */
0190 PNAME(mout_aud_pll_p)       = { "oscclk", "fout_aud_pll", };
0191 PNAME(mout_isp_pll_p)       = { "oscclk", "fout_isp_pll", };
0192 PNAME(mout_aud_pll_user_p)  = { "oscclk", "mout_aud_pll", };
0193 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
0194 PNAME(mout_mfc_pll_user_p)  = { "oscclk", "sclk_mfc_pll", };
0195 PNAME(mout_bus_pll_user_p)  = { "oscclk", "sclk_bus_pll", };
0196 PNAME(mout_bus_pll_user_t_p)    = { "oscclk", "mout_bus_pll_user", };
0197 PNAME(mout_mphy_pll_user_t_p)   = { "oscclk", "mout_mphy_pll_user", };
0198
0199 PNAME(mout_bus_mfc_pll_user_p)  = { "mout_bus_pll_user", "mout_mfc_pll_user",};
0200 PNAME(mout_mfc_bus_pll_user_p)  = { "mout_mfc_pll_user", "mout_bus_pll_user",};
0201 PNAME(mout_aclk_cam1_552_b_p)   = { "mout_aclk_cam1_552_a",
0202                     "mout_mfc_pll_user", };
0203 PNAME(mout_aclk_cam1_552_a_p)   = { "mout_isp_pll", "mout_bus_pll_user", };
0204
0205 PNAME(mout_aclk_mfc_400_c_p)    = { "mout_aclk_mfc_400_b",
0206                     "mout_mphy_pll_user", };
0207 PNAME(mout_aclk_mfc_400_b_p)    = { "mout_aclk_mfc_400_a",
0208                     "mout_bus_pll_user", };
0209 PNAME(mout_aclk_mfc_400_a_p)    = { "mout_mfc_pll_user", "mout_isp_pll", };
0210
0211 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
0212                     "mout_mphy_pll_user", };
0213 PNAME(mout_aclk_mscl_b_p)   = { "mout_aclk_mscl_400_a",
0214                     "mout_mphy_pll_user", };
0215 PNAME(mout_aclk_g2d_400_b_p)    = { "mout_aclk_g2d_400_a",
0216                     "mout_mphy_pll_user", };
0217
0218 PNAME(mout_sclk_jpeg_c_p)   = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
0219 PNAME(mout_sclk_jpeg_b_p)   = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
0220
0221 PNAME(mout_sclk_mmc2_b_p)   = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
0222 PNAME(mout_sclk_mmc1_b_p)   = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
0223 PNAME(mout_sclk_mmc0_d_p)   = { "mout_sclk_mmc0_c", "mout_isp_pll", };
0224 PNAME(mout_sclk_mmc0_c_p)   = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
0225 PNAME(mout_sclk_mmc0_b_p)   = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
0226
0227 PNAME(mout_sclk_spdif_p)    = { "sclk_audio0", "sclk_audio1",
0228                     "oscclk", "ioclk_spdif_extclk", };
0229 PNAME(mout_sclk_audio1_p)   = { "ioclk_audiocdclk1", "oscclk",
0230                     "mout_aud_pll_user_t",};
0231 PNAME(mout_sclk_audio0_p)   = { "ioclk_audiocdclk0", "oscclk",
0232                     "mout_aud_pll_user_t",};
0233
0234 PNAME(mout_sclk_hdmi_spdif_p)   = { "sclk_audio1", "ioclk_spdif_extclk", };
0235
0236 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
0237     FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
0238 };
0239
0240 static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {
0241     /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
0242     FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
0243     FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
0244     /* Xi2s1SDI input clock for SPDIF */
0245     FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000),
0246     /* XspiCLK[4:0] input clock for SPI */
0247     FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000),
0248     FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000),
0249     FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000),
0250     FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000),
0251     FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000),
0252     /* Xi2s1SCLK input clock for I2S1_BCLK */
0253     FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
0254 };
0255
0256 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
0257     /* MUX_SEL_TOP0 */
0258     MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
0259             4, 1),
0260     MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
0261             0, 1),
0262
0263     /* MUX_SEL_TOP1 */
0264     MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
0265             mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
0266     MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
0267             MUX_SEL_TOP1, 8, 1),
0268     MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
0269             MUX_SEL_TOP1, 4, 1),
0270     MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
0271             MUX_SEL_TOP1, 0, 1),
0272
0273     /* MUX_SEL_TOP2 */
0274     MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
0275             mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
0276     MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
0277             mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
0278     MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
0279             mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
0280     MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
0281             mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
0282     MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
0283             mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
0284     MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
0285             mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
0286
0287     /* MUX_SEL_TOP3 */
0288     MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
0289             mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
0290     MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
0291             mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
0292     MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
0293             mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
0294     MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
0295             mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
0296     MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
0297             mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
0298     MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
0299             mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
0300
0301     /* MUX_SEL_TOP4 */
0302     MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
0303             mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
0304     MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
0305             mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
0306     MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
0307             mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
0308
0309     /* MUX_SEL_TOP_MSCL */
0310     MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
0311             MUX_SEL_TOP_MSCL, 8, 1),
0312     MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
0313             MUX_SEL_TOP_MSCL, 4, 1),
0314     MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
0315             MUX_SEL_TOP_MSCL, 0, 1),
0316
0317     /* MUX_SEL_TOP_CAM1 */
0318     MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
0319             mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
0320     MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
0321             mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
0322     MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
0323             mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
0324     MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
0325             mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
0326     MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
0327             mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
0328     MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
0329             mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
0330
0331     /* MUX_SEL_TOP_FSYS0 */
0332     MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
0333             MUX_SEL_TOP_FSYS0, 28, 1),
0334     MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
0335             MUX_SEL_TOP_FSYS0, 24, 1),
0336     MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
0337             MUX_SEL_TOP_FSYS0, 20, 1),
0338     MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
0339             MUX_SEL_TOP_FSYS0, 16, 1),
0340     MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
0341             MUX_SEL_TOP_FSYS0, 12, 1),
0342     MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
0343             MUX_SEL_TOP_FSYS0, 8, 1),
0344     MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
0345             MUX_SEL_TOP_FSYS0, 4, 1),
0346     MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
0347             MUX_SEL_TOP_FSYS0, 0, 1),
0348
0349     /* MUX_SEL_TOP_FSYS1 */
0350     MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
0351             MUX_SEL_TOP_FSYS1, 12, 1),
0352     MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
0353             mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
0354     MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
0355             mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
0356     MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
0357             mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
0358
0359     /* MUX_SEL_TOP_PERIC0 */
0360     MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
0361             MUX_SEL_TOP_PERIC0, 28, 1),
0362     MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
0363             MUX_SEL_TOP_PERIC0, 24, 1),
0364     MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
0365             MUX_SEL_TOP_PERIC0, 20, 1),
0366     MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
0367             MUX_SEL_TOP_PERIC0, 16, 1),
0368     MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
0369             MUX_SEL_TOP_PERIC0, 12, 1),
0370     MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
0371             MUX_SEL_TOP_PERIC0, 8, 1),
0372     MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
0373             MUX_SEL_TOP_PERIC0, 4, 1),
0374     MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
0375             MUX_SEL_TOP_PERIC0, 0, 1),
0376
0377     /* MUX_SEL_TOP_PERIC1 */
0378     MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
0379             MUX_SEL_TOP_PERIC1, 16, 1),
0380     MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
0381             MUX_SEL_TOP_PERIC1, 12, 2),
0382     MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
0383             MUX_SEL_TOP_PERIC1, 4, 2),
0384     MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
0385             MUX_SEL_TOP_PERIC1, 0, 2),
0386
0387     /* MUX_SEL_TOP_DISP */
0388     MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
0389             mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
0390 };
0391
0392 static const struct samsung_div_clock top_div_clks[] __initconst = {
0393     /* DIV_TOP0 */
0394     DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
0395             DIV_TOP0, 28, 3),
0396     DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
0397             DIV_TOP0, 24, 3),
0398     DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
0399             DIV_TOP0, 20, 3),
0400     DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
0401             DIV_TOP0, 16, 3),
0402     DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
0403             DIV_TOP0, 12, 3),
0404     DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
0405             DIV_TOP0, 8, 3),
0406     DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
0407             "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
0408     DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
0409             "mout_aclk_isp_400", DIV_TOP0, 0, 4),
0410
0411     /* DIV_TOP1 */
0412     DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
0413             DIV_TOP1, 28, 3),
0414     DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
0415             DIV_TOP1, 24, 3),
0416     DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
0417             DIV_TOP1, 20, 3),
0418     DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
0419             DIV_TOP1, 12, 3),
0420     DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
0421             DIV_TOP1, 8, 3),
0422     DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
0423             DIV_TOP1, 0, 3),
0424
0425     /* DIV_TOP2 */
0426     DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
0427             DIV_TOP2, 4, 3),
0428     DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
0429             DIV_TOP2, 0, 3),
0430
0431     /* DIV_TOP3 */
0432     DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
0433             "mout_bus_pll_user", DIV_TOP3, 24, 3),
0434     DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
0435             "mout_bus_pll_user", DIV_TOP3, 20, 3),
0436     DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
0437             "mout_bus_pll_user", DIV_TOP3, 16, 3),
0438     DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
0439             "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
0440     DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
0441             "mout_bus_pll_user", DIV_TOP3, 8, 3),
0442     DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
0443             "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
0444     DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
0445             "mout_bus_pll_user", DIV_TOP3, 0, 3),
0446
0447     /* DIV_TOP4 */
0448     DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
0449             DIV_TOP4, 8, 3),
0450     DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
0451             DIV_TOP4, 4, 3),
0452     DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
0453             DIV_TOP4, 0, 3),
0454
0455     /* DIV_TOP_MSCL */
0456     DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
0457             DIV_TOP_MSCL, 0, 4),
0458
0459     /* DIV_TOP_CAM10 */
0460     DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
0461             DIV_TOP_CAM10, 24, 5),
0462     DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
0463             "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
0464     DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
0465             "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
0466     DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
0467             "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
0468     DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
0469             "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
0470
0471     /* DIV_TOP_CAM11 */
0472     DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
0473             "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
0474     DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
0475             "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
0476     DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
0477             "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
0478     DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
0479             "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
0480     DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
0481             "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4),
0482     DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
0483             "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4),
0484
0485     /* DIV_TOP_FSYS0 */
0486     DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
0487             DIV_TOP_FSYS0, 16, 8),
0488     DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
0489             DIV_TOP_FSYS0, 12, 4),
0490     DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
0491             DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
0492     DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
0493             DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
0494
0495     /* DIV_TOP_FSYS1 */
0496     DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
0497             DIV_TOP_FSYS1, 4, 8),
0498     DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
0499             DIV_TOP_FSYS1, 0, 4),
0500
0501     /* DIV_TOP_FSYS2 */
0502     DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
0503             DIV_TOP_FSYS2, 12, 3),
0504     DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
0505             "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
0506     DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
0507             "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
0508     DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
0509             DIV_TOP_FSYS2, 0, 4),
0510
0511     /* DIV_TOP_PERIC0 */
0512     DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
0513             DIV_TOP_PERIC0, 16, 8),
0514     DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
0515             DIV_TOP_PERIC0, 12, 4),
0516     DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
0517             DIV_TOP_PERIC0, 4, 8),
0518     DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
0519             DIV_TOP_PERIC0, 0, 4),
0520
0521     /* DIV_TOP_PERIC1 */
0522     DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
0523             DIV_TOP_PERIC1, 4, 8),
0524     DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
0525             DIV_TOP_PERIC1, 0, 4),
0526
0527     /* DIV_TOP_PERIC2 */
0528     DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
0529             DIV_TOP_PERIC2, 8, 4),
0530     DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
0531             DIV_TOP_PERIC2, 4, 4),
0532     DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
0533             DIV_TOP_PERIC2, 0, 4),
0534
0535     /* DIV_TOP_PERIC3 */
0536     DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
0537             DIV_TOP_PERIC3, 16, 6),
0538     DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
0539             DIV_TOP_PERIC3, 8, 8),
0540     DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
0541             DIV_TOP_PERIC3, 4, 4),
0542     DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
0543             DIV_TOP_PERIC3, 0, 4),
0544
0545     /* DIV_TOP_PERIC4 */
0546     DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
0547             DIV_TOP_PERIC4, 16, 8),
0548     DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
0549             DIV_TOP_PERIC4, 12, 4),
0550     DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
0551             DIV_TOP_PERIC4, 4, 8),
0552     DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
0553             DIV_TOP_PERIC4, 0, 4),
0554 };
0555
0556 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
0557     /* ENABLE_ACLK_TOP */
0558     GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
0559             ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),
0560     GATE(CLK_ACLK_IMEM_SSSX_266, "aclk_imem_sssx_266",
0561             "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
0562             29, CLK_IGNORE_UNUSED, 0),
0563     GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
0564             ENABLE_ACLK_TOP, 26,
0565             CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
0566     GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
0567             ENABLE_ACLK_TOP, 25,
0568             CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
0569     GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_200",
0570             ENABLE_ACLK_TOP, 24,
0571             CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
0572     GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_266",
0573             ENABLE_ACLK_TOP, 23,
0574             CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
0575     GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
0576             ENABLE_ACLK_TOP, 22,
0577             CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
0578     GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
0579             ENABLE_ACLK_TOP, 21,
0580             CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
0581     GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
0582             ENABLE_ACLK_TOP, 19,
0583             CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
0584     GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
0585             ENABLE_ACLK_TOP, 18,
0586             CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
0587     GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
0588             ENABLE_ACLK_TOP, 15,
0589             CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
0590     GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
0591             ENABLE_ACLK_TOP, 14,
0592             CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
0593     GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
0594             ENABLE_ACLK_TOP, 13,
0595             CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
0596     GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
0597             ENABLE_ACLK_TOP, 12,
0598             CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
0599     GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
0600             ENABLE_ACLK_TOP, 11,
0601             CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
0602     GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
0603             ENABLE_ACLK_TOP, 10,
0604             CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
0605     GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
0606             ENABLE_ACLK_TOP, 9,
0607             CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
0608     GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
0609             ENABLE_ACLK_TOP, 8,
0610             CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
0611     GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
0612             ENABLE_ACLK_TOP, 7,
0613             CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
0614     GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
0615             ENABLE_ACLK_TOP, 6,
0616             CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
0617     GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
0618             ENABLE_ACLK_TOP, 5,
0619             CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
0620     GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
0621             ENABLE_ACLK_TOP, 3,
0622             CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
0623     GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
0624             ENABLE_ACLK_TOP, 2,
0625             CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
0626     GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
0627             ENABLE_ACLK_TOP, 0,
0628             CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
0629
0630     /* ENABLE_SCLK_TOP_MSCL */
0631     GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
0632             ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0),
0633
0634     /* ENABLE_SCLK_TOP_CAM1 */
0635     GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
0636             ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
0637     GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
0638             ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
0639     GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
0640             ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
0641     GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
0642             ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
0643     GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
0644             ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
0645     GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
0646             ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
0647     GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
0648             ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
0649
0650     /* ENABLE_SCLK_TOP_DISP */
0651     GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
0652             "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
0653             CLK_IGNORE_UNUSED, 0),
0654
0655     /* ENABLE_SCLK_TOP_FSYS */
0656     GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
0657             ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
0658     GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
0659             ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
0660     GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
0661             ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
0662     GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
0663             ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
0664     GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
0665             "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
0666             3, CLK_SET_RATE_PARENT, 0),
0667     GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
0668             "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
0669             1, CLK_SET_RATE_PARENT, 0),
0670     GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
0671             "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
0672             0, CLK_SET_RATE_PARENT, 0),
0673
0674     /* ENABLE_SCLK_TOP_PERIC */
0675     GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
0676             ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
0677     GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
0678             ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
0679     GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
0680             ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
0681     GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
0682             ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
0683     GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
0684             ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
0685     GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
0686             ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
0687             CLK_IGNORE_UNUSED, 0),
0688     GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
0689             ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
0690             CLK_IGNORE_UNUSED, 0),
0691     GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
0692             ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
0693             CLK_IGNORE_UNUSED, 0),
0694     GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
0695             ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
0696     GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
0697             ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
0698     GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
0699             ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
0700
0701     /* MUX_ENABLE_TOP_PERIC1 */
0702     GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
0703             MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
0704     GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
0705             MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
0706     GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
0707             MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
0708 };
0709
0710 /*
0711  * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
0712  * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
0713  */
0714 static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = {
0715     PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6,  0),
0716     PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5,  0),
0717     PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6,  0),
0718     PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6,  0),
0719     PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4,  0),
0720     PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6,  0),
0721     PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6,  0),
0722     PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5,  0),
0723     PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6,  0),
0724     PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6,  0),
0725     PLL_35XX_RATE(24 * MHZ, 1500000000U, 250, 4,  0),
0726     PLL_35XX_RATE(24 * MHZ, 1400000000U, 350, 6,  0),
0727     PLL_35XX_RATE(24 * MHZ, 1332000000U, 222, 4,  0),
0728     PLL_35XX_RATE(24 * MHZ, 1300000000U, 325, 6,  0),
0729     PLL_35XX_RATE(24 * MHZ, 1200000000U, 500, 5,  1),
0730     PLL_35XX_RATE(24 * MHZ, 1100000000U, 550, 6,  1),
0731     PLL_35XX_RATE(24 * MHZ, 1086000000U, 362, 4,  1),
0732     PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 6,  1),
0733     PLL_35XX_RATE(24 * MHZ, 1000000000U, 500, 6,  1),
0734     PLL_35XX_RATE(24 * MHZ, 933000000U,  311, 4,  1),
0735     PLL_35XX_RATE(24 * MHZ, 921000000U,  307, 4,  1),
0736     PLL_35XX_RATE(24 * MHZ, 900000000U,  375, 5,  1),
0737     PLL_35XX_RATE(24 * MHZ, 825000000U,  275, 4,  1),
0738     PLL_35XX_RATE(24 * MHZ, 800000000U,  400, 6,  1),
0739     PLL_35XX_RATE(24 * MHZ, 733000000U,  733, 12, 1),
0740     PLL_35XX_RATE(24 * MHZ, 700000000U,  175, 3,  1),
0741     PLL_35XX_RATE(24 * MHZ, 666000000U,  222, 4,  1),
0742     PLL_35XX_RATE(24 * MHZ, 633000000U,  211, 4,  1),
0743     PLL_35XX_RATE(24 * MHZ, 600000000U,  500, 5,  2),
0744     PLL_35XX_RATE(24 * MHZ, 552000000U,  460, 5,  2),
0745     PLL_35XX_RATE(24 * MHZ, 550000000U,  550, 6,  2),
0746     PLL_35XX_RATE(24 * MHZ, 543000000U,  362, 4,  2),
0747     PLL_35XX_RATE(24 * MHZ, 533000000U,  533, 6,  2),
0748     PLL_35XX_RATE(24 * MHZ, 500000000U,  500, 6,  2),
0749     PLL_35XX_RATE(24 * MHZ, 444000000U,  370, 5,  2),
0750     PLL_35XX_RATE(24 * MHZ, 420000000U,  350, 5,  2),
0751     PLL_35XX_RATE(24 * MHZ, 400000000U,  400, 6,  2),
0752     PLL_35XX_RATE(24 * MHZ, 350000000U,  350, 6,  2),
0753     PLL_35XX_RATE(24 * MHZ, 333000000U,  222, 4,  2),
0754     PLL_35XX_RATE(24 * MHZ, 300000000U,  500, 5,  3),
0755     PLL_35XX_RATE(24 * MHZ, 278000000U,  556, 6,  3),
0756     PLL_35XX_RATE(24 * MHZ, 266000000U,  532, 6,  3),
0757     PLL_35XX_RATE(24 * MHZ, 250000000U,  500, 6,  3),
0758     PLL_35XX_RATE(24 * MHZ, 200000000U,  400, 6,  3),
0759     PLL_35XX_RATE(24 * MHZ, 166000000U,  332, 6,  3),
0760     PLL_35XX_RATE(24 * MHZ, 160000000U,  320, 6,  3),
0761     PLL_35XX_RATE(24 * MHZ, 133000000U,  532, 6,  4),
0762     PLL_35XX_RATE(24 * MHZ, 100000000U,  400, 6,  4),
0763     { /* sentinel */ }
0764 };
0765
0766 /* AUD_PLL */
0767 static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = {
0768     PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2,      0),
0769     PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
0770     PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2,      0),
0771     PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
0772     PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148),
0773     PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2,  -6816),
0774     PLL_36XX_RATE(24 * MHZ, 294912002U,  98, 1, 3,  19923),
0775     PLL_36XX_RATE(24 * MHZ, 288000000U,  96, 1, 3,      0),
0776     PLL_36XX_RATE(24 * MHZ, 252000000U,  84, 1, 3,      0),
0777     PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
0778     { /* sentinel */ }
0779 };
0780
0781 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
0782     PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
0783         ISP_PLL_LOCK, ISP_PLL_CON0, exynos5433_pll_rates),
0784     PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
0785         AUD_PLL_LOCK, AUD_PLL_CON0, exynos5433_aud_pll_rates),
0786 };
0787
0788 static const struct samsung_cmu_info top_cmu_info __initconst = {
0789     .pll_clks       = top_pll_clks,
0790     .nr_pll_clks        = ARRAY_SIZE(top_pll_clks),
0791     .mux_clks       = top_mux_clks,
0792     .nr_mux_clks        = ARRAY_SIZE(top_mux_clks),
0793     .div_clks       = top_div_clks,
0794     .nr_div_clks        = ARRAY_SIZE(top_div_clks),
0795     .gate_clks      = top_gate_clks,
0796     .nr_gate_clks       = ARRAY_SIZE(top_gate_clks),
0797     .fixed_clks     = top_fixed_clks,
0798     .nr_fixed_clks      = ARRAY_SIZE(top_fixed_clks),
0799     .fixed_factor_clks  = top_fixed_factor_clks,
0800     .nr_fixed_factor_clks   = ARRAY_SIZE(top_fixed_factor_clks),
0801     .nr_clk_ids     = TOP_NR_CLK,
0802     .clk_regs       = top_clk_regs,
0803     .nr_clk_regs        = ARRAY_SIZE(top_clk_regs),
0804     .suspend_regs       = top_suspend_regs,
0805     .nr_suspend_regs    = ARRAY_SIZE(top_suspend_regs),
0806 };
0807
0808 static void __init exynos5433_cmu_top_init(struct device_node *np)
0809 {
0810     samsung_cmu_register_one(np, &top_cmu_info);
0811 }
0812 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
0813         exynos5433_cmu_top_init);
0814
0815 /*
0816  * Register offset definitions for CMU_CPIF
0817  */
0818 #define MPHY_PLL_LOCK       0x0000
0819 #define MPHY_PLL_CON0       0x0100
0820 #define MPHY_PLL_CON1       0x0104
0821 #define MPHY_PLL_FREQ_DET   0x010c
0822 #define MUX_SEL_CPIF0       0x0200
0823 #define DIV_CPIF        0x0600
0824 #define ENABLE_SCLK_CPIF    0x0a00
0825
0826 static const unsigned long cpif_clk_regs[] __initconst = {
0827     MPHY_PLL_LOCK,
0828     MPHY_PLL_CON0,
0829     MPHY_PLL_CON1,
0830     MPHY_PLL_FREQ_DET,
0831     MUX_SEL_CPIF0,
0832     DIV_CPIF,
0833     ENABLE_SCLK_CPIF,
0834 };
0835
0836 static const struct samsung_clk_reg_dump cpif_suspend_regs[] = {
0837     /* force all sclk clocks enabled */
0838     { ENABLE_SCLK_CPIF, 0x3ff },
0839     /* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */
0840     { MPHY_PLL_CON0, 0x81c70601 },
0841 };
0842
0843 /* list of all parent clock list */
0844 PNAME(mout_mphy_pll_p)      = { "oscclk", "fout_mphy_pll", };
0845
0846 static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {
0847     PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
0848         MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5433_pll_rates),
0849 };
0850
0851 static const struct samsung_mux_clock cpif_mux_clks[] __initconst = {
0852     /* MUX_SEL_CPIF0 */
0853     MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
0854             0, 1),
0855 };
0856
0857 static const struct samsung_div_clock cpif_div_clks[] __initconst = {
0858     /* DIV_CPIF */
0859     DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
0860             0, 6),
0861 };
0862
0863 static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {
0864     /* ENABLE_SCLK_CPIF */
0865     GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
0866             ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
0867     GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
0868             ENABLE_SCLK_CPIF, 4, 0, 0),
0869 };
0870
0871 static const struct samsung_cmu_info cpif_cmu_info __initconst = {
0872     .pll_clks       = cpif_pll_clks,
0873     .nr_pll_clks        = ARRAY_SIZE(cpif_pll_clks),
0874     .mux_clks       = cpif_mux_clks,
0875     .nr_mux_clks        = ARRAY_SIZE(cpif_mux_clks),
0876     .div_clks       = cpif_div_clks,
0877     .nr_div_clks        = ARRAY_SIZE(cpif_div_clks),
0878     .gate_clks      = cpif_gate_clks,
0879     .nr_gate_clks       = ARRAY_SIZE(cpif_gate_clks),
0880     .nr_clk_ids     = CPIF_NR_CLK,
0881     .clk_regs       = cpif_clk_regs,
0882     .nr_clk_regs        = ARRAY_SIZE(cpif_clk_regs),
0883     .suspend_regs       = cpif_suspend_regs,
0884     .nr_suspend_regs    = ARRAY_SIZE(cpif_suspend_regs),
0885 };
0886
0887 static void __init exynos5433_cmu_cpif_init(struct device_node *np)
0888 {
0889     samsung_cmu_register_one(np, &cpif_cmu_info);
0890 }
0891 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
0892         exynos5433_cmu_cpif_init);
0893
0894 /*
0895  * Register offset definitions for CMU_MIF
0896  */
0897 #define MEM0_PLL_LOCK           0x0000
0898 #define MEM1_PLL_LOCK           0x0004
0899 #define BUS_PLL_LOCK            0x0008
0900 #define MFC_PLL_LOCK            0x000c
0901 #define MEM0_PLL_CON0           0x0100
0902 #define MEM0_PLL_CON1           0x0104
0903 #define MEM0_PLL_FREQ_DET       0x010c
0904 #define MEM1_PLL_CON0           0x0110
0905 #define MEM1_PLL_CON1           0x0114
0906 #define MEM1_PLL_FREQ_DET       0x011c
0907 #define BUS_PLL_CON0            0x0120
0908 #define BUS_PLL_CON1            0x0124
0909 #define BUS_PLL_FREQ_DET        0x012c
0910 #define MFC_PLL_CON0            0x0130
0911 #define MFC_PLL_CON1            0x0134
0912 #define MFC_PLL_FREQ_DET        0x013c
0913 #define MUX_SEL_MIF0            0x0200
0914 #define MUX_SEL_MIF1            0x0204
0915 #define MUX_SEL_MIF2            0x0208
0916 #define MUX_SEL_MIF3            0x020c
0917 #define MUX_SEL_MIF4            0x0210
0918 #define MUX_SEL_MIF5            0x0214
0919 #define MUX_SEL_MIF6            0x0218
0920 #define MUX_SEL_MIF7            0x021c
0921 #define MUX_ENABLE_MIF0         0x0300
0922 #define MUX_ENABLE_MIF1         0x0304
0923 #define MUX_ENABLE_MIF2         0x0308
0924 #define MUX_ENABLE_MIF3         0x030c
0925 #define MUX_ENABLE_MIF4         0x0310
0926 #define MUX_ENABLE_MIF5         0x0314
0927 #define MUX_ENABLE_MIF6         0x0318
0928 #define MUX_ENABLE_MIF7         0x031c
0929 #define MUX_STAT_MIF0           0x0400
0930 #define MUX_STAT_MIF1           0x0404
0931 #define MUX_STAT_MIF2           0x0408
0932 #define MUX_STAT_MIF3           0x040c
0933 #define MUX_STAT_MIF4           0x0410
0934 #define MUX_STAT_MIF5           0x0414
0935 #define MUX_STAT_MIF6           0x0418
0936 #define MUX_STAT_MIF7           0x041c
0937 #define DIV_MIF1            0x0604
0938 #define DIV_MIF2            0x0608
0939 #define DIV_MIF3            0x060c
0940 #define DIV_MIF4            0x0610
0941 #define DIV_MIF5            0x0614
0942 #define DIV_MIF_PLL_FREQ_DET        0x0618
0943 #define DIV_STAT_MIF1           0x0704
0944 #define DIV_STAT_MIF2           0x0708
0945 #define DIV_STAT_MIF3           0x070c
0946 #define DIV_STAT_MIF4           0x0710
0947 #define DIV_STAT_MIF5           0x0714
0948 #define DIV_STAT_MIF_PLL_FREQ_DET   0x0718
0949 #define ENABLE_ACLK_MIF0        0x0800
0950 #define ENABLE_ACLK_MIF1        0x0804
0951 #define ENABLE_ACLK_MIF2        0x0808
0952 #define ENABLE_ACLK_MIF3        0x080c
0953 #define ENABLE_PCLK_MIF         0x0900
0954 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
0955 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
0956 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT    0x090c
0957 #define ENABLE_PCLK_MIF_SECURE_RTC  0x0910
0958 #define ENABLE_SCLK_MIF         0x0a00
0959 #define ENABLE_IP_MIF0          0x0b00
0960 #define ENABLE_IP_MIF1          0x0b04
0961 #define ENABLE_IP_MIF2          0x0b08
0962 #define ENABLE_IP_MIF3          0x0b0c
0963 #define ENABLE_IP_MIF_SECURE_DREX0_TZ   0x0b10
0964 #define ENABLE_IP_MIF_SECURE_DREX1_TZ   0x0b14
0965 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT  0x0b18
0966 #define ENABLE_IP_MIF_SECURE_RTC    0x0b1c
0967 #define CLKOUT_CMU_MIF          0x0c00
0968 #define CLKOUT_CMU_MIF_DIV_STAT     0x0c04
0969 #define DREX_FREQ_CTRL0         0x1000
0970 #define DREX_FREQ_CTRL1         0x1004
0971 #define PAUSE               0x1008
0972 #define DDRPHY_LOCK_CTRL        0x100c
0973
0974 static const unsigned long mif_clk_regs[] __initconst = {
0975     MEM0_PLL_LOCK,
0976     MEM1_PLL_LOCK,
0977     BUS_PLL_LOCK,
0978     MFC_PLL_LOCK,
0979     MEM0_PLL_CON0,
0980     MEM0_PLL_CON1,
0981     MEM0_PLL_FREQ_DET,
0982     MEM1_PLL_CON0,
0983     MEM1_PLL_CON1,
0984     MEM1_PLL_FREQ_DET,
0985     BUS_PLL_CON0,
0986     BUS_PLL_CON1,
0987     BUS_PLL_FREQ_DET,
0988     MFC_PLL_CON0,
0989     MFC_PLL_CON1,
0990     MFC_PLL_FREQ_DET,
0991     MUX_SEL_MIF0,
0992     MUX_SEL_MIF1,
0993     MUX_SEL_MIF2,
0994     MUX_SEL_MIF3,
0995     MUX_SEL_MIF4,
0996     MUX_SEL_MIF5,
0997     MUX_SEL_MIF6,
0998     MUX_SEL_MIF7,
0999     MUX_ENABLE_MIF0,
1000     MUX_ENABLE_MIF1,
1001     MUX_ENABLE_MIF2,
1002     MUX_ENABLE_MIF3,
1003     MUX_ENABLE_MIF4,
1004     MUX_ENABLE_MIF5,
1005     MUX_ENABLE_MIF6,
1006     MUX_ENABLE_MIF7,
1007     DIV_MIF1,
1008     DIV_MIF2,
1009     DIV_MIF3,
1010     DIV_MIF4,
1011     DIV_MIF5,
1012     DIV_MIF_PLL_FREQ_DET,
1013     ENABLE_ACLK_MIF0,
1014     ENABLE_ACLK_MIF1,
1015     ENABLE_ACLK_MIF2,
1016     ENABLE_ACLK_MIF3,
1017     ENABLE_PCLK_MIF,
1018     ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
1019     ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
1020     ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
1021     ENABLE_PCLK_MIF_SECURE_RTC,
1022     ENABLE_SCLK_MIF,
1023     ENABLE_IP_MIF0,
1024     ENABLE_IP_MIF1,
1025     ENABLE_IP_MIF2,
1026     ENABLE_IP_MIF3,
1027     ENABLE_IP_MIF_SECURE_DREX0_TZ,
1028     ENABLE_IP_MIF_SECURE_DREX1_TZ,
1029     ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
1030     ENABLE_IP_MIF_SECURE_RTC,
1031     CLKOUT_CMU_MIF,
1032     CLKOUT_CMU_MIF_DIV_STAT,
1033     DREX_FREQ_CTRL0,
1034     DREX_FREQ_CTRL1,
1035     PAUSE,
1036     DDRPHY_LOCK_CTRL,
1037 };
1038
1039 static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
1040     PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
1041         MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5433_pll_rates),
1042     PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
1043         MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5433_pll_rates),
1044     PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
1045         BUS_PLL_LOCK, BUS_PLL_CON0, exynos5433_pll_rates),
1046     PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
1047         MFC_PLL_LOCK, MFC_PLL_CON0, exynos5433_pll_rates),
1048 };
1049
1050 /* list of all parent clock list */
1051 PNAME(mout_mfc_pll_div2_p)  = { "mout_mfc_pll", "dout_mfc_pll", };
1052 PNAME(mout_bus_pll_div2_p)  = { "mout_bus_pll", "dout_bus_pll", };
1053 PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
1054 PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
1055 PNAME(mout_mfc_pll_p)       = { "oscclk", "fout_mfc_pll", };
1056 PNAME(mout_bus_pll_p)       = { "oscclk", "fout_bus_pll", };
1057 PNAME(mout_mem1_pll_p)      = { "oscclk", "fout_mem1_pll", };
1058 PNAME(mout_mem0_pll_p)      = { "oscclk", "fout_mem0_pll", };
1059
1060 PNAME(mout_clk2x_phy_c_p)   = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
1061 PNAME(mout_clk2x_phy_b_p)   = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
1062 PNAME(mout_clk2x_phy_a_p)   = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
1063 PNAME(mout_clkm_phy_b_p)    = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
1064
1065 PNAME(mout_aclk_mifnm_200_p)    = { "mout_mem0_pll_div2", "div_mif_pre", };
1066 PNAME(mout_aclk_mifnm_400_p)    = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
1067
1068 PNAME(mout_aclk_disp_333_b_p)   = { "mout_aclk_disp_333_a",
1069                     "mout_bus_pll_div2", };
1070 PNAME(mout_aclk_disp_333_a_p)   = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
1071
1072 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
1073                     "sclk_mphy_pll", };
1074 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
1075                     "mout_mfc_pll_div2", };
1076 PNAME(mout_sclk_decon_p)    = { "oscclk", "mout_bus_pll_div2", };
1077 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
1078                     "sclk_mphy_pll", };
1079 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
1080                     "mout_mfc_pll_div2", };
1081
1082 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
1083                        "sclk_mphy_pll", };
1084 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
1085                        "mout_mfc_pll_div2", };
1086 PNAME(mout_sclk_dsd_c_p)    = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1087 PNAME(mout_sclk_dsd_b_p)    = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1088 PNAME(mout_sclk_dsd_a_p)    = { "oscclk", "mout_mfc_pll_div2", };
1089
1090 PNAME(mout_sclk_dsim0_c_p)  = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1091 PNAME(mout_sclk_dsim0_b_p)  = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1092
1093 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
1094                        "sclk_mphy_pll", };
1095 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1096                        "mout_mfc_pll_div2", };
1097 PNAME(mout_sclk_dsim1_c_p)  = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1098 PNAME(mout_sclk_dsim1_b_p)  = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1099
1100 static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {
1101     /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1102     FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1103     FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1104     FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1105     FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1106 };
1107
1108 static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
1109     /* MUX_SEL_MIF0 */
1110     MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1111             MUX_SEL_MIF0, 28, 1),
1112     MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
1113             MUX_SEL_MIF0, 24, 1),
1114     MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
1115             MUX_SEL_MIF0, 20, 1),
1116     MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
1117             MUX_SEL_MIF0, 16, 1),
1118     MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
1119             12, 1),
1120     MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
1121             8, 1),
1122     MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
1123             4, 1),
1124     MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
1125             0, 1),
1126
1127     /* MUX_SEL_MIF1 */
1128     MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
1129             MUX_SEL_MIF1, 24, 1),
1130     MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
1131             MUX_SEL_MIF1, 20, 1),
1132     MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
1133             MUX_SEL_MIF1, 16, 1),
1134     MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
1135             MUX_SEL_MIF1, 12, 1),
1136     MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
1137             MUX_SEL_MIF1, 8, 1),
1138     MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
1139             MUX_SEL_MIF1, 4, 1),
1140
1141     /* MUX_SEL_MIF2 */
1142     MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
1143             mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
1144     MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
1145             mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1146
1147     /* MUX_SEL_MIF3 */
1148     MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
1149             mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
1150     MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
1151             mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1152
1153     /* MUX_SEL_MIF4 */
1154     MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
1155             mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1156     MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1157             mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1158     MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1159             mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1160     MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1161             mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1162     MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1163             mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1164     MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1165             mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1166
1167     /* MUX_SEL_MIF5 */
1168     MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1169             mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1170     MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1171             mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1172     MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1173             mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1174     MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1175             MUX_SEL_MIF5, 8, 1),
1176     MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1177             MUX_SEL_MIF5, 4, 1),
1178     MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1179             MUX_SEL_MIF5, 0, 1),
1180
1181     /* MUX_SEL_MIF6 */
1182     MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1183             MUX_SEL_MIF6, 8, 1),
1184     MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1185             MUX_SEL_MIF6, 4, 1),
1186     MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1187             MUX_SEL_MIF6, 0, 1),
1188
1189     /* MUX_SEL_MIF7 */
1190     MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1191             mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1192     MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1193             mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1194     MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1195             mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1196     MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1197             MUX_SEL_MIF7, 8, 1),
1198     MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1199             MUX_SEL_MIF7, 4, 1),
1200     MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1201             MUX_SEL_MIF7, 0, 1),
1202 };
1203
1204 static const struct samsung_div_clock mif_div_clks[] __initconst = {
1205     /* DIV_MIF1 */
1206     DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1207             DIV_MIF1, 16, 2),
1208     DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1209             12, 2),
1210     DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1211             8, 2),
1212     DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1213             4, 4),
1214
1215     /* DIV_MIF2 */
1216     DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1217             DIV_MIF2, 20, 3),
1218     DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1219             DIV_MIF2, 16, 4),
1220     DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1221             DIV_MIF2, 12, 4),
1222     DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1223             "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1224     DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1225             DIV_MIF2, 4, 2),
1226     DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1227             DIV_MIF2, 0, 3),
1228
1229     /* DIV_MIF3 */
1230     DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1231             DIV_MIF3, 16, 4),
1232     DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1233             DIV_MIF3, 4, 3),
1234     DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1235             DIV_MIF3, 0, 3),
1236
1237     /* DIV_MIF4 */
1238     DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1239             DIV_MIF4, 24, 4),
1240     DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1241             "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1242     DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1243             DIV_MIF4, 16, 4),
1244     DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1245             DIV_MIF4, 12, 4),
1246     DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1247             "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1248     DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1249             "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1250     DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1251             "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1252
1253     /* DIV_MIF5 */
1254     DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1255             0, 3),
1256 };
1257
1258 static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
1259     /* ENABLE_ACLK_MIF0 */
1260     GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1261             19, CLK_IGNORE_UNUSED, 0),
1262     GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1263             18, CLK_IGNORE_UNUSED, 0),
1264     GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1265             17, CLK_IGNORE_UNUSED, 0),
1266     GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1267             16, CLK_IGNORE_UNUSED, 0),
1268     GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1269             15, CLK_IGNORE_UNUSED, 0),
1270     GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1271             14, CLK_IGNORE_UNUSED, 0),
1272     GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1273             ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1274     GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1275             ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1276     GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1277             ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1278     GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1279             ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1280     GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1281             ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1282     GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1283             ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1284     GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1285             ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1286     GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1287             ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1288     GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1289             ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1290     GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1291             ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1292     GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1293             ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1294     GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1295             ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1296     GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1297             ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1298     GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1299             ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1300
1301     /* ENABLE_ACLK_MIF1 */
1302     GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1303             "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1304             CLK_IGNORE_UNUSED, 0),
1305     GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1306             "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1307             27, CLK_IGNORE_UNUSED, 0),
1308     GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1309             "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1310             26, CLK_IGNORE_UNUSED, 0),
1311     GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1312             "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1313             25, CLK_IGNORE_UNUSED, 0),
1314     GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1315             "div_aclk_drex1", ENABLE_ACLK_MIF1,
1316             24, CLK_IGNORE_UNUSED, 0),
1317     GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1318             "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1319             23, CLK_IGNORE_UNUSED, 0),
1320     GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1321             "div_aclk_drex0", ENABLE_ACLK_MIF1,
1322             22, CLK_IGNORE_UNUSED, 0),
1323     GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1324             "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1325             21, CLK_IGNORE_UNUSED, 0),
1326     GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1327             "div_aclk_drex1", ENABLE_ACLK_MIF1,
1328             20, CLK_IGNORE_UNUSED, 0),
1329     GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1330             "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1331             19, CLK_IGNORE_UNUSED, 0),
1332     GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1333             "div_aclk_drex1", ENABLE_ACLK_MIF1,
1334             18, CLK_IGNORE_UNUSED, 0),
1335     GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1336             "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1337             17, CLK_IGNORE_UNUSED, 0),
1338     GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1339             "div_aclk_drex1", ENABLE_ACLK_MIF1,
1340             16, CLK_IGNORE_UNUSED, 0),
1341     GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1342             "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1343             15, CLK_IGNORE_UNUSED, 0),
1344     GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1345             "div_aclk_drex0", ENABLE_ACLK_MIF1,
1346             14, CLK_IGNORE_UNUSED, 0),
1347     GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1348             "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1349             13, CLK_IGNORE_UNUSED, 0),
1350     GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1351             "div_aclk_drex0", ENABLE_ACLK_MIF1,
1352             12, CLK_IGNORE_UNUSED, 0),
1353     GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1354             "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1355             11, CLK_IGNORE_UNUSED, 0),
1356     GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1357             "div_aclk_drex0", ENABLE_ACLK_MIF1,
1358             10, CLK_IGNORE_UNUSED, 0),
1359     GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1360             ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1361     GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1362             ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1363     GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1364             ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1365     GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1366             ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1367     GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1368             ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1369     GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1370             ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1371     GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1372             ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1373     GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1374             ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1375     GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1376             ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1377     GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1378             0, CLK_IGNORE_UNUSED, 0),
1379
1380     /* ENABLE_ACLK_MIF2 */
1381     GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1382             ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
1383     GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1384             ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1385     GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1386             ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1387     GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1388             ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1389     GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1390             ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1391     GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1392             ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1393     GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1394             ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1395     GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1396             "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1397             CLK_IGNORE_UNUSED, 0),
1398     GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1399             "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1400             5, CLK_IGNORE_UNUSED, 0),
1401     GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1402             ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1403     GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1404             "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1405             3, CLK_IGNORE_UNUSED, 0),
1406     GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1407             "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1408
1409     /* ENABLE_ACLK_MIF3 */
1410     GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1411             ENABLE_ACLK_MIF3, 4,
1412             CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1413     GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1414             ENABLE_ACLK_MIF3, 1,
1415             CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1416     GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1417             ENABLE_ACLK_MIF3, 0,
1418             CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1419
1420     /* ENABLE_PCLK_MIF */
1421     GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1422             ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1423     GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1424             ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1425     GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1426             ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1427     GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1428             ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1429     GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1430             ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1431     GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1432             ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1433     GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1434             "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1435             CLK_IGNORE_UNUSED, 0),
1436     GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1437             ENABLE_PCLK_MIF, 19, 0, 0),
1438     GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1439             ENABLE_PCLK_MIF, 18, 0, 0),
1440     GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1441             "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1442     GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1443             "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1444     GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1445             "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1446     GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1447             "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1448     GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1449             "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1450     GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1451             "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1452     GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1453             ENABLE_PCLK_MIF, 11, 0, 0),
1454     GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1455             ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1456     GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1457             ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1458     GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1459             ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1460     GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1461             ENABLE_PCLK_MIF, 7, 0, 0),
1462     GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1463             ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1464     GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1465             ENABLE_PCLK_MIF, 5, 0, 0),
1466     GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1467             ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1468     GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1469             ENABLE_PCLK_MIF, 2, 0, 0),
1470     GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1471             ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1472
1473     /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1474     GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1475             ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
1476             CLK_IGNORE_UNUSED, 0),
1477
1478     /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1479     GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1480             ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
1481             CLK_IGNORE_UNUSED, 0),
1482
1483     /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1484     GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1485             ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
1486
1487     /* ENABLE_PCLK_MIF_SECURE_RTC */
1488     GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1489             ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1490
1491     /* ENABLE_SCLK_MIF */
1492     GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1493             ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1494     GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1495             "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1496             14, CLK_IGNORE_UNUSED, 0),
1497     GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1498             ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1499     GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1500             ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1501     GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1502             "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1503             7, CLK_IGNORE_UNUSED, 0),
1504     GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1505             "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1506             6, CLK_IGNORE_UNUSED, 0),
1507     GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1508             "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1509             5, CLK_IGNORE_UNUSED, 0),
1510     GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1511             ENABLE_SCLK_MIF, 4,
1512             CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1513     GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1514             ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1515     GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1516             ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1517     GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1518             ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1519     GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1520             ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1521 };
1522
1523 static const struct samsung_cmu_info mif_cmu_info __initconst = {
1524     .pll_clks       = mif_pll_clks,
1525     .nr_pll_clks        = ARRAY_SIZE(mif_pll_clks),
1526     .mux_clks       = mif_mux_clks,
1527     .nr_mux_clks        = ARRAY_SIZE(mif_mux_clks),
1528     .div_clks       = mif_div_clks,
1529     .nr_div_clks        = ARRAY_SIZE(mif_div_clks),
1530     .gate_clks      = mif_gate_clks,
1531     .nr_gate_clks       = ARRAY_SIZE(mif_gate_clks),
1532     .fixed_factor_clks  = mif_fixed_factor_clks,
1533     .nr_fixed_factor_clks   = ARRAY_SIZE(mif_fixed_factor_clks),
1534     .nr_clk_ids     = MIF_NR_CLK,
1535     .clk_regs       = mif_clk_regs,
1536     .nr_clk_regs        = ARRAY_SIZE(mif_clk_regs),
1537 };
1538
1539 static void __init exynos5433_cmu_mif_init(struct device_node *np)
1540 {
1541     samsung_cmu_register_one(np, &mif_cmu_info);
1542 }
1543 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1544         exynos5433_cmu_mif_init);
1545
1546 /*
1547  * Register offset definitions for CMU_PERIC
1548  */
1549 #define DIV_PERIC           0x0600
1550 #define DIV_STAT_PERIC          0x0700
1551 #define ENABLE_ACLK_PERIC       0x0800
1552 #define ENABLE_PCLK_PERIC0      0x0900
1553 #define ENABLE_PCLK_PERIC1      0x0904
1554 #define ENABLE_SCLK_PERIC       0x0A00
1555 #define ENABLE_IP_PERIC0        0x0B00
1556 #define ENABLE_IP_PERIC1        0x0B04
1557 #define ENABLE_IP_PERIC2        0x0B08
1558
1559 static const unsigned long peric_clk_regs[] __initconst = {
1560     DIV_PERIC,
1561     ENABLE_ACLK_PERIC,
1562     ENABLE_PCLK_PERIC0,
1563     ENABLE_PCLK_PERIC1,
1564     ENABLE_SCLK_PERIC,
1565     ENABLE_IP_PERIC0,
1566     ENABLE_IP_PERIC1,
1567     ENABLE_IP_PERIC2,
1568 };
1569
1570 static const struct samsung_clk_reg_dump peric_suspend_regs[] = {
1571     /* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */
1572     { ENABLE_PCLK_PERIC0, 0xe00ff000 },
1573     /* sclk: uart2-0 */
1574     { ENABLE_SCLK_PERIC, 0x7 },
1575 };
1576
1577 static const struct samsung_div_clock peric_div_clks[] __initconst = {
1578     /* DIV_PERIC */
1579     DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1580     DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1581 };
1582
1583 static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
1584     /* ENABLE_ACLK_PERIC */
1585     GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1586             ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1587     GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1588             ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1589     GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1590             ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1591     GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1592             ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1593
1594     /* ENABLE_PCLK_PERIC0 */
1595     GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1596             31, CLK_SET_RATE_PARENT, 0),
1597     GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1598             ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1599     GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1600             ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1601     GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1602             28, CLK_SET_RATE_PARENT, 0),
1603     GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1604             26, CLK_SET_RATE_PARENT, 0),
1605     GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1606             25, CLK_SET_RATE_PARENT, 0),
1607     GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1608             24, CLK_SET_RATE_PARENT, 0),
1609     GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1610             23, CLK_SET_RATE_PARENT, 0),
1611     GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1612             22, CLK_SET_RATE_PARENT, 0),
1613     GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1614             21, CLK_SET_RATE_PARENT, 0),
1615     GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1616             20, CLK_SET_RATE_PARENT, 0),
1617     GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1618             ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1619     GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1620             ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1621     GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1622             ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1623     GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1624             ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1625     GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1626             ENABLE_PCLK_PERIC0, 15,
1627             CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1628     GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1629             14, CLK_SET_RATE_PARENT, 0),
1630     GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1631             13, CLK_SET_RATE_PARENT, 0),
1632     GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1633             12, CLK_SET_RATE_PARENT, 0),
1634     GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1635             ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1636     GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1637             ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1638     GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1639             ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1640     GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1641             ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1642     GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1643             7, CLK_SET_RATE_PARENT, 0),
1644     GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1645             6, CLK_SET_RATE_PARENT, 0),
1646     GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1647             5, CLK_SET_RATE_PARENT, 0),
1648     GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1649             4, CLK_SET_RATE_PARENT, 0),
1650     GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1651             3, CLK_SET_RATE_PARENT, 0),
1652     GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1653             2, CLK_SET_RATE_PARENT, 0),
1654     GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1655             1, CLK_SET_RATE_PARENT, 0),
1656     GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1657             0, CLK_SET_RATE_PARENT, 0),
1658
1659     /* ENABLE_PCLK_PERIC1 */
1660     GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1661             9, CLK_SET_RATE_PARENT, 0),
1662     GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1663             8, CLK_SET_RATE_PARENT, 0),
1664     GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1665             ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1666     GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1667             ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1668     GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1669             ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1670     GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1671             ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1672     GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1673             ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1674     GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1675             ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1676     GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1677             ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1678     GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1679             ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1680
1681     /* ENABLE_SCLK_PERIC */
1682     GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1683             ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1684     GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1685             ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1686     GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1687             19, CLK_SET_RATE_PARENT, 0),
1688     GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1689             18, CLK_SET_RATE_PARENT, 0),
1690     GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1691             17, 0, 0),
1692     GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1693             16, 0, 0),
1694     GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1695     GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1696             ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1697     GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1698             ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
1699     GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1700             ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1701     GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1702             "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1703             CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1704     GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1705             ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1706     GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1707             ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1708     GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1709             ENABLE_SCLK_PERIC, 6,
1710             CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1711     GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1712             5, CLK_SET_RATE_PARENT, 0),
1713     GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1714             4, CLK_SET_RATE_PARENT, 0),
1715     GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1716             3, CLK_SET_RATE_PARENT, 0),
1717     GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1718             ENABLE_SCLK_PERIC, 2,
1719             CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1720     GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1721             ENABLE_SCLK_PERIC, 1,
1722             CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1723     GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1724             ENABLE_SCLK_PERIC, 0,
1725             CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1726 };
1727
1728 static const struct samsung_cmu_info peric_cmu_info __initconst = {
1729     .div_clks       = peric_div_clks,
1730     .nr_div_clks        = ARRAY_SIZE(peric_div_clks),
1731     .gate_clks      = peric_gate_clks,
1732     .nr_gate_clks       = ARRAY_SIZE(peric_gate_clks),
1733     .nr_clk_ids     = PERIC_NR_CLK,
1734     .clk_regs       = peric_clk_regs,
1735     .nr_clk_regs        = ARRAY_SIZE(peric_clk_regs),
1736     .suspend_regs       = peric_suspend_regs,
1737     .nr_suspend_regs    = ARRAY_SIZE(peric_suspend_regs),
1738 };
1739
1740 static void __init exynos5433_cmu_peric_init(struct device_node *np)
1741 {
1742     samsung_cmu_register_one(np, &peric_cmu_info);
1743 }
1744
1745 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1746         exynos5433_cmu_peric_init);
1747
1748 /*
1749  * Register offset definitions for CMU_PERIS
1750  */
1751 #define ENABLE_ACLK_PERIS               0x0800
1752 #define ENABLE_PCLK_PERIS               0x0900
1753 #define ENABLE_PCLK_PERIS_SECURE_TZPC           0x0904
1754 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF       0x0908
1755 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF       0x090c
1756 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC         0x0910
1757 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
1758 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF  0x0918
1759 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF      0x091c
1760 #define ENABLE_SCLK_PERIS               0x0a00
1761 #define ENABLE_SCLK_PERIS_SECURE_SECKEY         0x0a04
1762 #define ENABLE_SCLK_PERIS_SECURE_CHIPID         0x0a08
1763 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC         0x0a0c
1764 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE       0x0a10
1765 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT        0x0a14
1766 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON        0x0a18
1767 #define ENABLE_IP_PERIS0                0x0b00
1768 #define ENABLE_IP_PERIS1                0x0b04
1769 #define ENABLE_IP_PERIS_SECURE_TZPC         0x0b08
1770 #define ENABLE_IP_PERIS_SECURE_SECKEY           0x0b0c
1771 #define ENABLE_IP_PERIS_SECURE_CHIPID           0x0b10
1772 #define ENABLE_IP_PERIS_SECURE_TOPRTC           0x0b14
1773 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE     0x0b18
1774 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT      0x0b1c
1775 #define ENABLE_IP_PERIS_SECURE_OTP_CON          0x0b20
1776
1777 static const unsigned long peris_clk_regs[] __initconst = {
1778     ENABLE_ACLK_PERIS,
1779     ENABLE_PCLK_PERIS,
1780     ENABLE_PCLK_PERIS_SECURE_TZPC,
1781     ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1782     ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1783     ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1784     ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1785     ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1786     ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1787     ENABLE_SCLK_PERIS,
1788     ENABLE_SCLK_PERIS_SECURE_SECKEY,
1789     ENABLE_SCLK_PERIS_SECURE_CHIPID,
1790     ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1791     ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1792     ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1793     ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1794     ENABLE_IP_PERIS0,
1795     ENABLE_IP_PERIS1,
1796     ENABLE_IP_PERIS_SECURE_TZPC,
1797     ENABLE_IP_PERIS_SECURE_SECKEY,
1798     ENABLE_IP_PERIS_SECURE_CHIPID,
1799     ENABLE_IP_PERIS_SECURE_TOPRTC,
1800     ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1801     ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1802     ENABLE_IP_PERIS_SECURE_OTP_CON,
1803 };
1804
1805 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
1806     /* ENABLE_ACLK_PERIS */
1807     GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1808             ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1809     GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1810             ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1811     GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1812             ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1813
1814     /* ENABLE_PCLK_PERIS */
1815     GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1816             ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1817     GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1818             ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1819     GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1820             ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1821     GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1822             ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1823     GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1824             ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1825     GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1826             ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1827     GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1828             ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1829     GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1830             ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1831     GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1832             ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1833     GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1834             ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1835
1836     /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1837     GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1838             ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
1839     GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1840             ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
1841     GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1842             ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
1843     GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1844             ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
1845     GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1846             ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
1847     GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1848             ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
1849     GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1850             ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
1851     GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1852             ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
1853     GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1854             ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
1855     GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1856             ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
1857     GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1858             ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
1859     GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1860             ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
1861     GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1862             ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
1863
1864     /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1865     GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1866             ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1867
1868     /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1869     GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1870             ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1871
1872     /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1873     GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1874             ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1875
1876     /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1877     GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1878             "aclk_peris_66",
1879             ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1880
1881     /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1882     GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1883             "aclk_peris_66",
1884             ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1885
1886     /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1887     GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1888             "aclk_peris_66",
1889             ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1890
1891     /* ENABLE_SCLK_PERIS */
1892     GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1893             ENABLE_SCLK_PERIS, 10, 0, 0),
1894     GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1895             ENABLE_SCLK_PERIS, 4, 0, 0),
1896     GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1897             ENABLE_SCLK_PERIS, 3, 0, 0),
1898
1899     /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1900     GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1901             ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
1902
1903     /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1904     GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1905             ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
1906
1907     /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1908     GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1909             ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1910
1911     /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1912     GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1913             ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1914
1915     /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1916     GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1917             ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1918
1919     /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1920     GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1921             ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1922 };
1923
1924 static const struct samsung_cmu_info peris_cmu_info __initconst = {
1925     .gate_clks      = peris_gate_clks,
1926     .nr_gate_clks       = ARRAY_SIZE(peris_gate_clks),
1927     .nr_clk_ids     = PERIS_NR_CLK,
1928     .clk_regs       = peris_clk_regs,
1929     .nr_clk_regs        = ARRAY_SIZE(peris_clk_regs),
1930 };
1931
1932 static void __init exynos5433_cmu_peris_init(struct device_node *np)
1933 {
1934     samsung_cmu_register_one(np, &peris_cmu_info);
1935 }
1936
1937 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1938         exynos5433_cmu_peris_init);
1939
1940 /*
1941  * Register offset definitions for CMU_FSYS
1942  */
1943 #define MUX_SEL_FSYS0           0x0200
1944 #define MUX_SEL_FSYS1           0x0204
1945 #define MUX_SEL_FSYS2           0x0208
1946 #define MUX_SEL_FSYS3           0x020c
1947 #define MUX_SEL_FSYS4           0x0210
1948 #define MUX_ENABLE_FSYS0        0x0300
1949 #define MUX_ENABLE_FSYS1        0x0304
1950 #define MUX_ENABLE_FSYS2        0x0308
1951 #define MUX_ENABLE_FSYS3        0x030c
1952 #define MUX_ENABLE_FSYS4        0x0310
1953 #define MUX_STAT_FSYS0          0x0400
1954 #define MUX_STAT_FSYS1          0x0404
1955 #define MUX_STAT_FSYS2          0x0408
1956 #define MUX_STAT_FSYS3          0x040c
1957 #define MUX_STAT_FSYS4          0x0410
1958 #define MUX_IGNORE_FSYS2        0x0508
1959 #define MUX_IGNORE_FSYS3        0x050c
1960 #define ENABLE_ACLK_FSYS0       0x0800
1961 #define ENABLE_ACLK_FSYS1       0x0804
1962 #define ENABLE_PCLK_FSYS        0x0900
1963 #define ENABLE_SCLK_FSYS        0x0a00
1964 #define ENABLE_IP_FSYS0         0x0b00
1965 #define ENABLE_IP_FSYS1         0x0b04
1966
1967 /* list of all parent clock list */
1968 PNAME(mout_sclk_ufs_mphy_user_p)    = { "oscclk", "sclk_ufs_mphy", };
1969 PNAME(mout_aclk_fsys_200_user_p)    = { "oscclk", "aclk_fsys_200", };
1970 PNAME(mout_sclk_pcie_100_user_p)    = { "oscclk", "sclk_pcie_100_fsys",};
1971 PNAME(mout_sclk_ufsunipro_user_p)   = { "oscclk", "sclk_ufsunipro_fsys",};
1972 PNAME(mout_sclk_mmc2_user_p)        = { "oscclk", "sclk_mmc2_fsys", };
1973 PNAME(mout_sclk_mmc1_user_p)        = { "oscclk", "sclk_mmc1_fsys", };
1974 PNAME(mout_sclk_mmc0_user_p)        = { "oscclk", "sclk_mmc0_fsys", };
1975 PNAME(mout_sclk_usbhost30_user_p)   = { "oscclk", "sclk_usbhost30_fsys",};
1976 PNAME(mout_sclk_usbdrd30_user_p)    = { "oscclk", "sclk_usbdrd30_fsys", };
1977
1978 PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
1979         = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
1980 PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
1981         = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
1982 PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
1983         = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
1984 PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
1985         = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
1986 PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
1987         = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
1988 PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
1989         = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
1990 PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
1991         = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
1992 PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
1993         = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
1994 PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
1995         = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
1996 PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
1997         = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
1998 PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
1999         = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
2000 PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
2001         = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
2002 PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
2003         = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
2004 PNAME(mout_sclk_mphy_p)
2005         = { "mout_sclk_ufs_mphy_user",
2006                 "mout_phyclk_lli_mphy_to_ufs_user", };
2007
2008 static const unsigned long fsys_clk_regs[] __initconst = {
2009     MUX_SEL_FSYS0,
2010     MUX_SEL_FSYS1,
2011     MUX_SEL_FSYS2,
2012     MUX_SEL_FSYS3,
2013     MUX_SEL_FSYS4,
2014     MUX_ENABLE_FSYS0,
2015     MUX_ENABLE_FSYS1,
2016     MUX_ENABLE_FSYS2,
2017     MUX_ENABLE_FSYS3,
2018     MUX_ENABLE_FSYS4,
2019     MUX_IGNORE_FSYS2,
2020     MUX_IGNORE_FSYS3,
2021     ENABLE_ACLK_FSYS0,
2022     ENABLE_ACLK_FSYS1,
2023     ENABLE_PCLK_FSYS,
2024     ENABLE_SCLK_FSYS,
2025     ENABLE_IP_FSYS0,
2026     ENABLE_IP_FSYS1,
2027 };
2028
2029 static const struct samsung_clk_reg_dump fsys_suspend_regs[] = {
2030     { MUX_SEL_FSYS0, 0 },
2031     { MUX_SEL_FSYS1, 0 },
2032     { MUX_SEL_FSYS2, 0 },
2033     { MUX_SEL_FSYS3, 0 },
2034     { MUX_SEL_FSYS4, 0 },
2035 };
2036
2037 static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
2038     /* PHY clocks from USBDRD30_PHY */
2039     FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
2040             "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
2041             0, 60000000),
2042     FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
2043             "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
2044             0, 125000000),
2045     /* PHY clocks from USBHOST30_PHY */
2046     FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
2047             "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
2048             0, 60000000),
2049     FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
2050             "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
2051             0, 125000000),
2052     /* PHY clocks from USBHOST20_PHY */
2053     FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
2054             "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000),
2055     FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
2056             "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000),
2057     FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
2058             "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
2059             0, 48000000),
2060     FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
2061             "phyclk_usbhost20_phy_hsic1_phy", NULL, 0,
2062             60000000),
2063     /* PHY clocks from UFS_PHY */
2064     FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
2065             NULL, 0, 300000000),
2066     FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
2067             NULL, 0, 300000000),
2068     FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
2069             NULL, 0, 300000000),
2070     FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
2071             NULL, 0, 300000000),
2072     /* PHY clocks from LLI_PHY */
2073     FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
2074             NULL, 0, 26000000),
2075 };
2076
2077 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
2078     /* MUX_SEL_FSYS0 */
2079     MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
2080             mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
2081     MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
2082             mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2083
2084     /* MUX_SEL_FSYS1 */
2085     MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
2086             mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
2087     MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
2088             mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
2089     MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
2090             mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
2091     MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
2092             mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
2093     MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
2094             mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
2095     MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
2096             mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
2097     MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
2098             mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2099
2100     /* MUX_SEL_FSYS2 */
2101     MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
2102             "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2103             mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
2104             MUX_SEL_FSYS2, 28, 1),
2105     MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
2106             "mout_phyclk_usbhost30_uhost30_phyclock_user",
2107             mout_phyclk_usbhost30_uhost30_phyclock_user_p,
2108             MUX_SEL_FSYS2, 24, 1),
2109     MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
2110             "mout_phyclk_usbhost20_phy_hsic1",
2111             mout_phyclk_usbhost20_phy_hsic1_p,
2112             MUX_SEL_FSYS2, 20, 1),
2113     MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2114             "mout_phyclk_usbhost20_phy_clk48mohci_user",
2115             mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2116             MUX_SEL_FSYS2, 16, 1),
2117     MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2118             "mout_phyclk_usbhost20_phy_phyclock_user",
2119             mout_phyclk_usbhost20_phy_phyclock_user_p,
2120             MUX_SEL_FSYS2, 12, 1),
2121     MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2122             "mout_phyclk_usbhost20_phy_freeclk_user",
2123             mout_phyclk_usbhost20_phy_freeclk_user_p,
2124             MUX_SEL_FSYS2, 8, 1),
2125     MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2126             "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2127             mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2128             MUX_SEL_FSYS2, 4, 1),
2129     MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2130             "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2131             mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2132             MUX_SEL_FSYS2, 0, 1),
2133
2134     /* MUX_SEL_FSYS3 */
2135     MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2136             "mout_phyclk_ufs_rx1_symbol_user",
2137             mout_phyclk_ufs_rx1_symbol_user_p,
2138             MUX_SEL_FSYS3, 16, 1),
2139     MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2140             "mout_phyclk_ufs_rx0_symbol_user",
2141             mout_phyclk_ufs_rx0_symbol_user_p,
2142             MUX_SEL_FSYS3, 12, 1),
2143     MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2144             "mout_phyclk_ufs_tx1_symbol_user",
2145             mout_phyclk_ufs_tx1_symbol_user_p,
2146             MUX_SEL_FSYS3, 8, 1),
2147     MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2148             "mout_phyclk_ufs_tx0_symbol_user",
2149             mout_phyclk_ufs_tx0_symbol_user_p,
2150             MUX_SEL_FSYS3, 4, 1),
2151     MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2152             "mout_phyclk_lli_mphy_to_ufs_user",
2153             mout_phyclk_lli_mphy_to_ufs_user_p,
2154             MUX_SEL_FSYS3, 0, 1),
2155
2156     /* MUX_SEL_FSYS4 */
2157     MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2158             MUX_SEL_FSYS4, 0, 1),
2159 };
2160
2161 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
2162     /* ENABLE_ACLK_FSYS0 */
2163     GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2164             ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2165     GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
2166             ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2167     GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
2168             ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2169     GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
2170             ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2171     GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
2172             ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2173     GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
2174             ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2175     GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
2176             ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2177     GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2178             ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2179     GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2180             ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2181     GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2182             ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2183     GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
2184             ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2185
2186     /* ENABLE_ACLK_FSYS1 */
2187     GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2188             ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2189     GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2190             "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2191             26, CLK_IGNORE_UNUSED, 0),
2192     GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2193             ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2194     GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2195             ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
2196     GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2197             "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2198             22, CLK_IGNORE_UNUSED, 0),
2199     GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2200             ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2201     GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2202             ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2203     GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2204             "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2205             13, 0, 0),
2206     GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2207             "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2208             12, 0, 0),
2209     GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2210             "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2211             11, CLK_IGNORE_UNUSED, 0),
2212     GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2213             "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2214             10, CLK_IGNORE_UNUSED, 0),
2215     GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2216             "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2217             9, CLK_IGNORE_UNUSED, 0),
2218     GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2219             "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2220             8, CLK_IGNORE_UNUSED, 0),
2221     GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2222             "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2223             7, CLK_IGNORE_UNUSED, 0),
2224     GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2225             "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2226             6, CLK_IGNORE_UNUSED, 0),
2227     GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2228             ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2229     GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2230             ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2231     GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2232             ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2233     GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2234             ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2235     GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2236             ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2237     GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2238             ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2239
2240     /* ENABLE_PCLK_FSYS */
2241     GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2242             ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
2243     GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2244             ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2245     GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2246             ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
2247     GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2248             ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
2249     GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2250             ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2251     GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2252             ENABLE_PCLK_FSYS, 5, 0, 0),
2253     GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2254             "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2255     GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2256             "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2257     GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2258             ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2259     GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2260             ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2261     GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2262             "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2263             0, CLK_IGNORE_UNUSED, 0),
2264
2265     /* ENABLE_SCLK_FSYS */
2266     GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2267             ENABLE_SCLK_FSYS, 21, 0, 0),
2268     GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2269             "phyclk_usbhost30_uhost30_pipe_pclk",
2270             "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2271             ENABLE_SCLK_FSYS, 18, 0, 0),
2272     GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2273             "phyclk_usbhost30_uhost30_phyclock",
2274             "mout_phyclk_usbhost30_uhost30_phyclock_user",
2275             ENABLE_SCLK_FSYS, 17, 0, 0),
2276     GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2277             "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2278             16, 0, 0),
2279     GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2280             "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2281             15, 0, 0),
2282     GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2283             "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2284             14, 0, 0),
2285     GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2286             "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2287             13, 0, 0),
2288     GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2289             "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2290             12, 0, 0),
2291     GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2292             "phyclk_usbhost20_phy_clk48mohci",
2293             "mout_phyclk_usbhost20_phy_clk48mohci_user",
2294             ENABLE_SCLK_FSYS, 11, 0, 0),
2295     GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2296             "phyclk_usbhost20_phy_phyclock",
2297             "mout_phyclk_usbhost20_phy_phyclock_user",
2298             ENABLE_SCLK_FSYS, 10, 0, 0),
2299     GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2300             "phyclk_usbhost20_phy_freeclk",
2301             "mout_phyclk_usbhost20_phy_freeclk_user",
2302             ENABLE_SCLK_FSYS, 9, 0, 0),
2303     GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2304             "phyclk_usbdrd30_udrd30_pipe_pclk",
2305             "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2306             ENABLE_SCLK_FSYS, 8, 0, 0),
2307     GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2308             "phyclk_usbdrd30_udrd30_phyclock",
2309             "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2310             ENABLE_SCLK_FSYS, 7, 0, 0),
2311     GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2312             ENABLE_SCLK_FSYS, 6, 0, 0),
2313     GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2314             ENABLE_SCLK_FSYS, 5, 0, 0),
2315     GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
2316             ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2317     GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
2318             ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2319     GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
2320             ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2321     GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2322             ENABLE_SCLK_FSYS, 1, 0, 0),
2323     GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2324             ENABLE_SCLK_FSYS, 0, 0, 0),
2325
2326     /* ENABLE_IP_FSYS0 */
2327     GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
2328     GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2329     GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2330 };
2331
2332 static const struct samsung_cmu_info fsys_cmu_info __initconst = {
2333     .mux_clks       = fsys_mux_clks,
2334     .nr_mux_clks        = ARRAY_SIZE(fsys_mux_clks),
2335     .gate_clks      = fsys_gate_clks,
2336     .nr_gate_clks       = ARRAY_SIZE(fsys_gate_clks),
2337     .fixed_clks     = fsys_fixed_clks,
2338     .nr_fixed_clks      = ARRAY_SIZE(fsys_fixed_clks),
2339     .nr_clk_ids     = FSYS_NR_CLK,
2340     .clk_regs       = fsys_clk_regs,
2341     .nr_clk_regs        = ARRAY_SIZE(fsys_clk_regs),
2342     .suspend_regs       = fsys_suspend_regs,
2343     .nr_suspend_regs    = ARRAY_SIZE(fsys_suspend_regs),
2344     .clk_name       = "aclk_fsys_200",
2345 };
2346
2347 /*
2348  * Register offset definitions for CMU_G2D
2349  */
2350 #define MUX_SEL_G2D0                0x0200
2351 #define MUX_SEL_ENABLE_G2D0         0x0300
2352 #define MUX_SEL_STAT_G2D0           0x0400
2353 #define DIV_G2D                 0x0600
2354 #define DIV_STAT_G2D                0x0700
2355 #define DIV_ENABLE_ACLK_G2D         0x0800
2356 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
2357 #define DIV_ENABLE_PCLK_G2D         0x0900
2358 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
2359 #define DIV_ENABLE_IP_G2D0          0x0b00
2360 #define DIV_ENABLE_IP_G2D1          0x0b04
2361 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D   0x0b08
2362
2363 static const unsigned long g2d_clk_regs[] __initconst = {
2364     MUX_SEL_G2D0,
2365     MUX_SEL_ENABLE_G2D0,
2366     DIV_G2D,
2367     DIV_ENABLE_ACLK_G2D,
2368     DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
2369     DIV_ENABLE_PCLK_G2D,
2370     DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
2371     DIV_ENABLE_IP_G2D0,
2372     DIV_ENABLE_IP_G2D1,
2373     DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2374 };
2375
2376 static const struct samsung_clk_reg_dump g2d_suspend_regs[] = {
2377     { MUX_SEL_G2D0, 0 },
2378 };
2379
2380 /* list of all parent clock list */
2381 PNAME(mout_aclk_g2d_266_user_p)     = { "oscclk", "aclk_g2d_266", };
2382 PNAME(mout_aclk_g2d_400_user_p)     = { "oscclk", "aclk_g2d_400", };
2383
2384 static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
2385     /* MUX_SEL_G2D0 */
2386     MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2387             mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
2388     MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
2389             mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2390 };
2391
2392 static const struct samsung_div_clock g2d_div_clks[] __initconst = {
2393     /* DIV_G2D */
2394     DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2395             DIV_G2D, 0, 2),
2396 };
2397
2398 static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
2399     /* DIV_ENABLE_ACLK_G2D */
2400     GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2401             DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2402     GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2403             DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2404     GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2405             DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2406     GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2407             DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2408     GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2409             DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2410     GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
2411             "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
2412             7, 0, 0),
2413     GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2414             DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2415     GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2416             DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2417     GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2418             DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2419     GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
2420             DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2421     GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2422             DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2423     GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
2424             DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2425     GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
2426             DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2427
2428     /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2429     GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2430         DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2431
2432     /* DIV_ENABLE_PCLK_G2D */
2433     GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
2434             DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2435     GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
2436             DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2437     GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
2438             DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2439     GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
2440             DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2441     GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2442             DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2443     GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
2444             DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2445     GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
2446             DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2447     GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
2448             0, 0, 0),
2449
2450     /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2451     GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2452         DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2453 };
2454
2455 static const struct samsung_cmu_info g2d_cmu_info __initconst = {
2456     .mux_clks       = g2d_mux_clks,
2457     .nr_mux_clks        = ARRAY_SIZE(g2d_mux_clks),
2458     .div_clks       = g2d_div_clks,
2459     .nr_div_clks        = ARRAY_SIZE(g2d_div_clks),
2460     .gate_clks      = g2d_gate_clks,
2461     .nr_gate_clks       = ARRAY_SIZE(g2d_gate_clks),
2462     .nr_clk_ids     = G2D_NR_CLK,
2463     .clk_regs       = g2d_clk_regs,
2464     .nr_clk_regs        = ARRAY_SIZE(g2d_clk_regs),
2465     .suspend_regs       = g2d_suspend_regs,
2466     .nr_suspend_regs    = ARRAY_SIZE(g2d_suspend_regs),
2467     .clk_name       = "aclk_g2d_400",
2468 };
2469
2470 /*
2471  * Register offset definitions for CMU_DISP
2472  */
2473 #define DISP_PLL_LOCK           0x0000
2474 #define DISP_PLL_CON0           0x0100
2475 #define DISP_PLL_CON1           0x0104
2476 #define DISP_PLL_FREQ_DET       0x0108
2477 #define MUX_SEL_DISP0           0x0200
2478 #define MUX_SEL_DISP1           0x0204
2479 #define MUX_SEL_DISP2           0x0208
2480 #define MUX_SEL_DISP3           0x020c
2481 #define MUX_SEL_DISP4           0x0210
2482 #define MUX_ENABLE_DISP0        0x0300
2483 #define MUX_ENABLE_DISP1        0x0304
2484 #define MUX_ENABLE_DISP2        0x0308
2485 #define MUX_ENABLE_DISP3        0x030c
2486 #define MUX_ENABLE_DISP4        0x0310
2487 #define MUX_STAT_DISP0          0x0400
2488 #define MUX_STAT_DISP1          0x0404
2489 #define MUX_STAT_DISP2          0x0408
2490 #define MUX_STAT_DISP3          0x040c
2491 #define MUX_STAT_DISP4          0x0410
2492 #define MUX_IGNORE_DISP2        0x0508
2493 #define DIV_DISP            0x0600
2494 #define DIV_DISP_PLL_FREQ_DET       0x0604
2495 #define DIV_STAT_DISP           0x0700
2496 #define DIV_STAT_DISP_PLL_FREQ_DET  0x0704
2497 #define ENABLE_ACLK_DISP0       0x0800
2498 #define ENABLE_ACLK_DISP1       0x0804
2499 #define ENABLE_PCLK_DISP        0x0900
2500 #define ENABLE_SCLK_DISP        0x0a00
2501 #define ENABLE_IP_DISP0         0x0b00
2502 #define ENABLE_IP_DISP1         0x0b04
2503 #define CLKOUT_CMU_DISP         0x0c00
2504 #define CLKOUT_CMU_DISP_DIV_STAT    0x0c04
2505
2506 static const unsigned long disp_clk_regs[] __initconst = {
2507     DISP_PLL_LOCK,
2508     DISP_PLL_CON0,
2509     DISP_PLL_CON1,
2510     DISP_PLL_FREQ_DET,
2511     MUX_SEL_DISP0,
2512     MUX_SEL_DISP1,
2513     MUX_SEL_DISP2,
2514     MUX_SEL_DISP3,
2515     MUX_SEL_DISP4,
2516     MUX_ENABLE_DISP0,
2517     MUX_ENABLE_DISP1,
2518     MUX_ENABLE_DISP2,
2519     MUX_ENABLE_DISP3,
2520     MUX_ENABLE_DISP4,
2521     MUX_IGNORE_DISP2,
2522     DIV_DISP,
2523     DIV_DISP_PLL_FREQ_DET,
2524     ENABLE_ACLK_DISP0,
2525     ENABLE_ACLK_DISP1,
2526     ENABLE_PCLK_DISP,
2527     ENABLE_SCLK_DISP,
2528     ENABLE_IP_DISP0,
2529     ENABLE_IP_DISP1,
2530     CLKOUT_CMU_DISP,
2531     CLKOUT_CMU_DISP_DIV_STAT,
2532 };
2533
2534 static const struct samsung_clk_reg_dump disp_suspend_regs[] = {
2535     /* PLL has to be enabled for suspend */
2536     { DISP_PLL_CON0, 0x85f40502 },
2537     /* ignore status of external PHY muxes during suspend to avoid hangs */
2538     { MUX_IGNORE_DISP2, 0x00111111 },
2539     { MUX_SEL_DISP0, 0 },
2540     { MUX_SEL_DISP1, 0 },
2541     { MUX_SEL_DISP2, 0 },
2542     { MUX_SEL_DISP3, 0 },
2543     { MUX_SEL_DISP4, 0 },
2544 };
2545
2546 /* list of all parent clock list */
2547 PNAME(mout_disp_pll_p)          = { "oscclk", "fout_disp_pll", };
2548 PNAME(mout_sclk_dsim1_user_p)       = { "oscclk", "sclk_dsim1_disp", };
2549 PNAME(mout_sclk_dsim0_user_p)       = { "oscclk", "sclk_dsim0_disp", };
2550 PNAME(mout_sclk_dsd_user_p)     = { "oscclk", "sclk_dsd_disp", };
2551 PNAME(mout_sclk_decon_tv_eclk_user_p)   = { "oscclk",
2552                         "sclk_decon_tv_eclk_disp", };
2553 PNAME(mout_sclk_decon_vclk_user_p)  = { "oscclk",
2554                         "sclk_decon_vclk_disp", };
2555 PNAME(mout_sclk_decon_eclk_user_p)  = { "oscclk",
2556                         "sclk_decon_eclk_disp", };
2557 PNAME(mout_sclk_decon_tv_vlkc_user_p)   = { "oscclk",
2558                         "sclk_decon_tv_vclk_disp", };
2559 PNAME(mout_aclk_disp_333_user_p)    = { "oscclk", "aclk_disp_333", };
2560
2561 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p)  = { "oscclk",
2562                     "phyclk_mipidphy1_bitclkdiv8_phy", };
2563 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p)   = { "oscclk",
2564                     "phyclk_mipidphy1_rxclkesc0_phy", };
2565 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p)  = { "oscclk",
2566                     "phyclk_mipidphy0_bitclkdiv8_phy", };
2567 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p)   = { "oscclk",
2568                     "phyclk_mipidphy0_rxclkesc0_phy", };
2569 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk",
2570                     "phyclk_hdmiphy_tmds_clko_phy", };
2571 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p)    = { "oscclk",
2572                     "phyclk_hdmiphy_pixel_clko_phy", };
2573
2574 PNAME(mout_sclk_dsim0_p)        = { "mout_disp_pll",
2575                         "mout_sclk_dsim0_user", };
2576 PNAME(mout_sclk_decon_tv_eclk_p)    = { "mout_disp_pll",
2577                         "mout_sclk_decon_tv_eclk_user", };
2578 PNAME(mout_sclk_decon_vclk_p)       = { "mout_disp_pll",
2579                         "mout_sclk_decon_vclk_user", };
2580 PNAME(mout_sclk_decon_eclk_p)       = { "mout_disp_pll",
2581                         "mout_sclk_decon_eclk_user", };
2582
2583 PNAME(mout_sclk_dsim1_b_disp_p)     = { "mout_sclk_dsim1_a_disp",
2584                         "mout_sclk_dsim1_user", };
2585 PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2586                 "mout_phyclk_hdmiphy_pixel_clko_user",
2587                 "mout_sclk_decon_tv_vclk_b_disp", };
2588 PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2589                         "mout_sclk_decon_tv_vclk_user", };
2590
2591 static const struct samsung_pll_clock disp_pll_clks[] __initconst = {
2592     PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2593         DISP_PLL_LOCK, DISP_PLL_CON0, exynos5433_pll_rates),
2594 };
2595
2596 static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = {
2597     /*
2598      * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2599      * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2600      * and sclk_decon_{vclk|tv_vclk}.
2601      */
2602     FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2603             1, 2, 0),
2604     FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2605             1, 2, 0),
2606 };
2607
2608 static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
2609     /* PHY clocks from MIPI_DPHY1 */
2610     FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
2611     FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
2612     /* PHY clocks from MIPI_DPHY0 */
2613     FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
2614             NULL, 0, 188000000),
2615     FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
2616             NULL, 0, 100000000),
2617     /* PHY clocks from HDMI_PHY */
2618     FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
2619             NULL, 0, 300000000),
2620     FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
2621             NULL, 0, 166000000),
2622 };
2623
2624 static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
2625     /* MUX_SEL_DISP0 */
2626     MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2627             0, 1),
2628
2629     /* MUX_SEL_DISP1 */
2630     MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2631             mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2632     MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2633             mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2634     MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2635             MUX_SEL_DISP1, 20, 1),
2636     MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2637             mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2638     MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2639             mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2640     MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2641             mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2642     MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2643             mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2644     MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2645             mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2646
2647     /* MUX_SEL_DISP2 */
2648     MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2649             "mout_phyclk_mipidphy1_bitclkdiv8_user",
2650             mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2651             20, 1),
2652     MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2653             "mout_phyclk_mipidphy1_rxclkesc0_user",
2654             mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2655             16, 1),
2656     MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2657             "mout_phyclk_mipidphy0_bitclkdiv8_user",
2658             mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2659             12, 1),
2660     MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2661             "mout_phyclk_mipidphy0_rxclkesc0_user",
2662             mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2663             8, 1),
2664     MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2665             "mout_phyclk_hdmiphy_tmds_clko_user",
2666             mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2667             4, 1),
2668     MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2669             "mout_phyclk_hdmiphy_pixel_clko_user",
2670             mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2671             0, 1),
2672
2673     /* MUX_SEL_DISP3 */
2674     MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2675             MUX_SEL_DISP3, 12, 1),
2676     MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2677             mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2678     MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2679             mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2680     MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2681             mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2682
2683     /* MUX_SEL_DISP4 */
2684     MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2685             mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2686     MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2687             mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2688     MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2689             "mout_sclk_decon_tv_vclk_c_disp",
2690             mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2691     MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2692             "mout_sclk_decon_tv_vclk_b_disp",
2693             mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2694     MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2695             "mout_sclk_decon_tv_vclk_a_disp",
2696             mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2697 };
2698
2699 static const struct samsung_div_clock disp_div_clks[] __initconst = {
2700     /* DIV_DISP */
2701     DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2702             "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2703     DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2704             "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2705     DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2706             DIV_DISP, 16, 3),
2707     DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2708             "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2709     DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2710             "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2711     DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2712             "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2713     DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2714             DIV_DISP, 0, 2),
2715 };
2716
2717 static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
2718     /* ENABLE_ACLK_DISP0 */
2719     GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2720             ENABLE_ACLK_DISP0, 2, 0, 0),
2721     GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2722             ENABLE_ACLK_DISP0, 0, 0, 0),
2723
2724     /* ENABLE_ACLK_DISP1 */
2725     GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2726             ENABLE_ACLK_DISP1, 25, 0, 0),
2727     GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2728             ENABLE_ACLK_DISP1, 24, 0, 0),
2729     GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2730             "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2731     GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2732             "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2733     GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2734             "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2735     GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2736             "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2737     GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2738             "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2739     GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2740             "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2741     GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2742             "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2743     GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2744             "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2745     GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2746             "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2747     GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2748             "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2749     GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2750             "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2751     GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2752             "div_pclk_disp", ENABLE_ACLK_DISP1,
2753             12, CLK_IGNORE_UNUSED, 0),
2754     GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2755             "div_pclk_disp", ENABLE_ACLK_DISP1,
2756             11, CLK_IGNORE_UNUSED, 0),
2757     GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2758             "div_pclk_disp", ENABLE_ACLK_DISP1,
2759             10, CLK_IGNORE_UNUSED, 0),
2760     GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2761             ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2762     GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2763             ENABLE_ACLK_DISP1, 7, 0, 0),
2764     GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2765             ENABLE_ACLK_DISP1, 6, 0, 0),
2766     GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2767             "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2768     GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2769             "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2770     GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2771             ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2772     GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2773             ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2774     GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2775             "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2776             CLK_IGNORE_UNUSED, 0),
2777     GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2778             "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2779             0, CLK_IGNORE_UNUSED, 0),
2780
2781     /* ENABLE_PCLK_DISP */
2782     GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2783             ENABLE_PCLK_DISP, 23, 0, 0),
2784     GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2785             ENABLE_PCLK_DISP, 22, 0, 0),
2786     GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2787             ENABLE_PCLK_DISP, 21, 0, 0),
2788     GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2789             ENABLE_PCLK_DISP, 20, 0, 0),
2790     GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2791             ENABLE_PCLK_DISP, 19, 0, 0),
2792     GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2793             ENABLE_PCLK_DISP, 18, 0, 0),
2794     GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2795             ENABLE_PCLK_DISP, 17, 0, 0),
2796     GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2797             ENABLE_PCLK_DISP, 16, 0, 0),
2798     GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2799             ENABLE_PCLK_DISP, 15, 0, 0),
2800     GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2801             ENABLE_PCLK_DISP, 14, 0, 0),
2802     GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2803             ENABLE_PCLK_DISP, 13, 0, 0),
2804     GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2805             ENABLE_PCLK_DISP, 12, 0, 0),
2806     GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2807             ENABLE_PCLK_DISP, 11, 0, 0),
2808     GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2809             ENABLE_PCLK_DISP, 10, 0, 0),
2810     GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2811             ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2812     GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2813             ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2814     GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2815             ENABLE_PCLK_DISP, 7, 0, 0),
2816     GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2817             ENABLE_PCLK_DISP, 6, 0, 0),
2818     GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2819             ENABLE_PCLK_DISP, 5, 0, 0),
2820     GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2821             ENABLE_PCLK_DISP, 3, 0, 0),
2822     GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2823             ENABLE_PCLK_DISP, 2, 0, 0),
2824     GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2825             ENABLE_PCLK_DISP, 1, 0, 0),
2826     GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp",
2827             ENABLE_PCLK_DISP, 0, 0, 0),
2828
2829     /* ENABLE_SCLK_DISP */
2830     GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2831             "mout_phyclk_mipidphy1_bitclkdiv8_user",
2832             ENABLE_SCLK_DISP, 26, 0, 0),
2833     GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2834             "mout_phyclk_mipidphy1_rxclkesc0_user",
2835             ENABLE_SCLK_DISP, 25, 0, 0),
2836     GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2837             "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2838     GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2839             "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2840     GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2841             ENABLE_SCLK_DISP, 22, 0, 0),
2842     GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2843             "div_sclk_decon_tv_vclk_disp",
2844             ENABLE_SCLK_DISP, 21, 0, 0),
2845     GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2846             "mout_phyclk_mipidphy0_bitclkdiv8_user",
2847             ENABLE_SCLK_DISP, 15, 0, 0),
2848     GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2849             "mout_phyclk_mipidphy0_rxclkesc0_user",
2850             ENABLE_SCLK_DISP, 14, 0, 0),
2851     GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2852             "mout_phyclk_hdmiphy_tmds_clko_user",
2853             ENABLE_SCLK_DISP, 13, 0, 0),
2854     GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2855             "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2856     GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2857             "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2858     GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2859             "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2860     GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2861             "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2862     GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2863             ENABLE_SCLK_DISP, 7, 0, 0),
2864     GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2865             ENABLE_SCLK_DISP, 6, 0, 0),
2866     GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2867             ENABLE_SCLK_DISP, 5, 0, 0),
2868     GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2869             "div_sclk_decon_tv_eclk_disp",
2870             ENABLE_SCLK_DISP, 4, 0, 0),
2871     GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2872             "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2873     GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2874             "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2875 };
2876
2877 static const struct samsung_cmu_info disp_cmu_info __initconst = {
2878     .pll_clks       = disp_pll_clks,
2879     .nr_pll_clks        = ARRAY_SIZE(disp_pll_clks),
2880     .mux_clks       = disp_mux_clks,
2881     .nr_mux_clks        = ARRAY_SIZE(disp_mux_clks),
2882     .div_clks       = disp_div_clks,
2883     .nr_div_clks        = ARRAY_SIZE(disp_div_clks),
2884     .gate_clks      = disp_gate_clks,
2885     .nr_gate_clks       = ARRAY_SIZE(disp_gate_clks),
2886     .fixed_clks     = disp_fixed_clks,
2887     .nr_fixed_clks      = ARRAY_SIZE(disp_fixed_clks),
2888     .fixed_factor_clks  = disp_fixed_factor_clks,
2889     .nr_fixed_factor_clks   = ARRAY_SIZE(disp_fixed_factor_clks),
2890     .nr_clk_ids     = DISP_NR_CLK,
2891     .clk_regs       = disp_clk_regs,
2892     .nr_clk_regs        = ARRAY_SIZE(disp_clk_regs),
2893     .suspend_regs       = disp_suspend_regs,
2894     .nr_suspend_regs    = ARRAY_SIZE(disp_suspend_regs),
2895     .clk_name       = "aclk_disp_333",
2896 };
2897
2898 /*
2899  * Register offset definitions for CMU_AUD
2900  */
2901 #define MUX_SEL_AUD0            0x0200
2902 #define MUX_SEL_AUD1            0x0204
2903 #define MUX_ENABLE_AUD0         0x0300
2904 #define MUX_ENABLE_AUD1         0x0304
2905 #define MUX_STAT_AUD0           0x0400
2906 #define DIV_AUD0            0x0600
2907 #define DIV_AUD1            0x0604
2908 #define DIV_STAT_AUD0           0x0700
2909 #define DIV_STAT_AUD1           0x0704
2910 #define ENABLE_ACLK_AUD         0x0800
2911 #define ENABLE_PCLK_AUD         0x0900
2912 #define ENABLE_SCLK_AUD0        0x0a00
2913 #define ENABLE_SCLK_AUD1        0x0a04
2914 #define ENABLE_IP_AUD0          0x0b00
2915 #define ENABLE_IP_AUD1          0x0b04
2916
2917 static const unsigned long aud_clk_regs[] __initconst = {
2918     MUX_SEL_AUD0,
2919     MUX_SEL_AUD1,
2920     MUX_ENABLE_AUD0,
2921     MUX_ENABLE_AUD1,
2922     DIV_AUD0,
2923     DIV_AUD1,
2924     ENABLE_ACLK_AUD,
2925     ENABLE_PCLK_AUD,
2926     ENABLE_SCLK_AUD0,
2927     ENABLE_SCLK_AUD1,
2928     ENABLE_IP_AUD0,
2929     ENABLE_IP_AUD1,
2930 };
2931
2932 static const struct samsung_clk_reg_dump aud_suspend_regs[] = {
2933     { MUX_SEL_AUD0, 0 },
2934     { MUX_SEL_AUD1, 0 },
2935 };
2936
2937 /* list of all parent clock list */
2938 PNAME(mout_aud_pll_user_aud_p)  = { "oscclk", "fout_aud_pll", };
2939 PNAME(mout_sclk_aud_pcm_p)  = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2940
2941 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
2942     FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
2943     FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
2944     FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
2945 };
2946
2947 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
2948     /* MUX_SEL_AUD0 */
2949     MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2950             mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2951
2952     /* MUX_SEL_AUD1 */
2953     MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
2954             MUX_SEL_AUD1, 8, 1),
2955     MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
2956             MUX_SEL_AUD1, 0, 1),
2957 };
2958
2959 static const struct samsung_div_clock aud_div_clks[] __initconst = {
2960     /* DIV_AUD0 */
2961     DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2962             12, 4),
2963     DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
2964             8, 4),
2965     DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
2966             4, 4),
2967     DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
2968             0, 4),
2969
2970     /* DIV_AUD1 */
2971     DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
2972             "mout_aud_pll_user", DIV_AUD1, 16, 5),
2973     DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
2974             DIV_AUD1, 12, 4),
2975     DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2976             DIV_AUD1, 4, 8),
2977     DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s",  "mout_sclk_aud_i2s",
2978             DIV_AUD1, 0, 4),
2979 };
2980
2981 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
2982     /* ENABLE_ACLK_AUD */
2983     GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2984             ENABLE_ACLK_AUD, 12, 0, 0),
2985     GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
2986             ENABLE_ACLK_AUD, 7, 0, 0),
2987     GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
2988             ENABLE_ACLK_AUD, 0, 4, 0),
2989     GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
2990             ENABLE_ACLK_AUD, 0, 3, 0),
2991     GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
2992             ENABLE_ACLK_AUD, 0, 2, 0),
2993     GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
2994             0, 1, 0),
2995     GATE(CLK_ACLK_DMAC, "aclk_dmac",  "div_aclk_aud", ENABLE_ACLK_AUD,
2996             0, CLK_IGNORE_UNUSED, 0),
2997
2998     /* ENABLE_PCLK_AUD */
2999     GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
3000             13, 0, 0),
3001     GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
3002             12, 0, 0),
3003     GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
3004             11, 0, 0),
3005     GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
3006             ENABLE_PCLK_AUD, 10, 0, 0),
3007     GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
3008             ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
3009     GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
3010             ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
3011     GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
3012             ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
3013     GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
3014             ENABLE_PCLK_AUD, 6, 0, 0),
3015     GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
3016             ENABLE_PCLK_AUD, 5, 0, 0),
3017     GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
3018             ENABLE_PCLK_AUD, 4, 0, 0),
3019     GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
3020             ENABLE_PCLK_AUD, 3, 0, 0),
3021     GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
3022             2, 0, 0),
3023     GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
3024             ENABLE_PCLK_AUD, 0, 0, 0),
3025
3026     /* ENABLE_SCLK_AUD0 */
3027     GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
3028             2, CLK_IGNORE_UNUSED, 0),
3029     GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
3030             ENABLE_SCLK_AUD0, 1, 0, 0),
3031     GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
3032             0, 0, 0),
3033
3034     /* ENABLE_SCLK_AUD1 */
3035     GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
3036             ENABLE_SCLK_AUD1, 6, 0, 0),
3037     GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
3038             ENABLE_SCLK_AUD1, 5, 0, 0),
3039     GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
3040             ENABLE_SCLK_AUD1, 4, 0, 0),
3041     GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
3042             ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
3043     GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
3044             ENABLE_SCLK_AUD1, 2, 0, 0),
3045     GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
3046             ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
3047     GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
3048             ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
3049 };
3050
3051 static const struct samsung_cmu_info aud_cmu_info __initconst = {
3052     .mux_clks       = aud_mux_clks,
3053     .nr_mux_clks        = ARRAY_SIZE(aud_mux_clks),
3054     .div_clks       = aud_div_clks,
3055     .nr_div_clks        = ARRAY_SIZE(aud_div_clks),
3056     .gate_clks      = aud_gate_clks,
3057     .nr_gate_clks       = ARRAY_SIZE(aud_gate_clks),
3058     .fixed_clks     = aud_fixed_clks,
3059     .nr_fixed_clks      = ARRAY_SIZE(aud_fixed_clks),
3060     .nr_clk_ids     = AUD_NR_CLK,
3061     .clk_regs       = aud_clk_regs,
3062     .nr_clk_regs        = ARRAY_SIZE(aud_clk_regs),
3063     .suspend_regs       = aud_suspend_regs,
3064     .nr_suspend_regs    = ARRAY_SIZE(aud_suspend_regs),
3065     .clk_name       = "fout_aud_pll",
3066 };
3067
3068 /*
3069  * Register offset definitions for CMU_BUS{0|1|2}
3070  */
3071 #define DIV_BUS             0x0600
3072 #define DIV_STAT_BUS            0x0700
3073 #define ENABLE_ACLK_BUS         0x0800
3074 #define ENABLE_PCLK_BUS         0x0900
3075 #define ENABLE_IP_BUS0          0x0b00
3076 #define ENABLE_IP_BUS1          0x0b04
3077
3078 #define MUX_SEL_BUS2            0x0200  /* Only for CMU_BUS2 */
3079 #define MUX_ENABLE_BUS2         0x0300  /* Only for CMU_BUS2 */
3080 #define MUX_STAT_BUS2           0x0400  /* Only for CMU_BUS2 */
3081
3082 /* list of all parent clock list */
3083 PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
3084
3085 #define CMU_BUS_COMMON_CLK_REGS \
3086     DIV_BUS,        \
3087     ENABLE_ACLK_BUS,    \
3088     ENABLE_PCLK_BUS,    \
3089     ENABLE_IP_BUS0,     \
3090     ENABLE_IP_BUS1
3091
3092 static const unsigned long bus01_clk_regs[] __initconst = {
3093     CMU_BUS_COMMON_CLK_REGS,
3094 };
3095
3096 static const unsigned long bus2_clk_regs[] __initconst = {
3097     MUX_SEL_BUS2,
3098     MUX_ENABLE_BUS2,
3099     CMU_BUS_COMMON_CLK_REGS,
3100 };
3101
3102 static const struct samsung_div_clock bus0_div_clks[] __initconst = {
3103     /* DIV_BUS0 */
3104     DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3105             DIV_BUS, 0, 3),
3106 };
3107
3108 /* CMU_BUS0 clocks */
3109 static const struct samsung_gate_clock bus0_gate_clks[] __initconst = {
3110     /* ENABLE_ACLK_BUS0 */
3111     GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3112             ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3113     GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
3114             ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3115     GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
3116             ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3117
3118     /* ENABLE_PCLK_BUS0 */
3119     GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3120             ENABLE_PCLK_BUS, 2, 0, 0),
3121     GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
3122             ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3123     GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3124             ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3125 };
3126
3127 /* CMU_BUS1 clocks */
3128 static const struct samsung_div_clock bus1_div_clks[] __initconst = {
3129     /* DIV_BUS1 */
3130     DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3131             DIV_BUS, 0, 3),
3132 };
3133
3134 static const struct samsung_gate_clock bus1_gate_clks[] __initconst = {
3135     /* ENABLE_ACLK_BUS1 */
3136     GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3137             ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3138     GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
3139             ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3140     GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
3141             ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3142
3143     /* ENABLE_PCLK_BUS1 */
3144     GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3145             ENABLE_PCLK_BUS, 2, 0, 0),
3146     GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
3147             ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3148     GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3149             ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3150 };
3151
3152 /* CMU_BUS2 clocks */
3153 static const struct samsung_mux_clock bus2_mux_clks[] __initconst = {
3154     /* MUX_SEL_BUS2 */
3155     MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3156             mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3157 };
3158
3159 static const struct samsung_div_clock bus2_div_clks[] __initconst = {
3160     /* DIV_BUS2 */
3161     DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3162             "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3163 };
3164
3165 static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
3166     /* ENABLE_ACLK_BUS2 */
3167     GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3168             ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3169     GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
3170             ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3171     GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
3172             "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3173             1, CLK_IGNORE_UNUSED, 0),
3174     GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
3175             "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3176             0, CLK_IGNORE_UNUSED, 0),
3177
3178     /* ENABLE_PCLK_BUS2 */
3179     GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3180             ENABLE_PCLK_BUS, 2, 0, 0),
3181     GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
3182             ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3183     GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3184             ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3185 };
3186
3187 #define CMU_BUS_INFO_CLKS(id)                       \
3188     .div_clks       = bus##id##_div_clks,           \
3189     .nr_div_clks        = ARRAY_SIZE(bus##id##_div_clks),   \
3190     .gate_clks      = bus##id##_gate_clks,          \
3191     .nr_gate_clks       = ARRAY_SIZE(bus##id##_gate_clks),  \
3192     .nr_clk_ids     = BUSx_NR_CLK
3193
3194 static const struct samsung_cmu_info bus0_cmu_info __initconst = {
3195     CMU_BUS_INFO_CLKS(0),
3196     .clk_regs       = bus01_clk_regs,
3197     .nr_clk_regs        = ARRAY_SIZE(bus01_clk_regs),
3198 };
3199
3200 static const struct samsung_cmu_info bus1_cmu_info __initconst = {
3201     CMU_BUS_INFO_CLKS(1),
3202     .clk_regs       = bus01_clk_regs,
3203     .nr_clk_regs        = ARRAY_SIZE(bus01_clk_regs),
3204 };
3205
3206 static const struct samsung_cmu_info bus2_cmu_info __initconst = {
3207     CMU_BUS_INFO_CLKS(2),
3208     .mux_clks       = bus2_mux_clks,
3209     .nr_mux_clks        = ARRAY_SIZE(bus2_mux_clks),
3210     .clk_regs       = bus2_clk_regs,
3211     .nr_clk_regs        = ARRAY_SIZE(bus2_clk_regs),
3212 };
3213
3214 #define exynos5433_cmu_bus_init(id)                 \
3215 static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3216 {                                   \
3217     samsung_cmu_register_one(np, &bus##id##_cmu_info);      \
3218 }                                   \
3219 CLK_OF_DECLARE(exynos5433_cmu_bus##id,                  \
3220         "samsung,exynos5433-cmu-bus"#id,            \
3221         exynos5433_cmu_bus##id##_init)
3222
3223 exynos5433_cmu_bus_init(0);
3224 exynos5433_cmu_bus_init(1);
3225 exynos5433_cmu_bus_init(2);
3226
3227 /*
3228  * Register offset definitions for CMU_G3D
3229  */
3230 #define G3D_PLL_LOCK            0x0000
3231 #define G3D_PLL_CON0            0x0100
3232 #define G3D_PLL_CON1            0x0104
3233 #define G3D_PLL_FREQ_DET        0x010c
3234 #define MUX_SEL_G3D         0x0200
3235 #define MUX_ENABLE_G3D          0x0300
3236 #define MUX_STAT_G3D            0x0400
3237 #define DIV_G3D             0x0600
3238 #define DIV_G3D_PLL_FREQ_DET        0x0604
3239 #define DIV_STAT_G3D            0x0700
3240 #define DIV_STAT_G3D_PLL_FREQ_DET   0x0704
3241 #define ENABLE_ACLK_G3D         0x0800
3242 #define ENABLE_PCLK_G3D         0x0900
3243 #define ENABLE_SCLK_G3D         0x0a00
3244 #define ENABLE_IP_G3D0          0x0b00
3245 #define ENABLE_IP_G3D1          0x0b04
3246 #define CLKOUT_CMU_G3D          0x0c00
3247 #define CLKOUT_CMU_G3D_DIV_STAT     0x0c04
3248 #define CLK_STOPCTRL            0x1000
3249
3250 static const unsigned long g3d_clk_regs[] __initconst = {
3251     G3D_PLL_LOCK,
3252     G3D_PLL_CON0,
3253     G3D_PLL_CON1,
3254     G3D_PLL_FREQ_DET,
3255     MUX_SEL_G3D,
3256     MUX_ENABLE_G3D,
3257     DIV_G3D,
3258     DIV_G3D_PLL_FREQ_DET,
3259     ENABLE_ACLK_G3D,
3260     ENABLE_PCLK_G3D,
3261     ENABLE_SCLK_G3D,
3262     ENABLE_IP_G3D0,
3263     ENABLE_IP_G3D1,
3264     CLKOUT_CMU_G3D,
3265     CLKOUT_CMU_G3D_DIV_STAT,
3266     CLK_STOPCTRL,
3267 };
3268
3269 static const struct samsung_clk_reg_dump g3d_suspend_regs[] = {
3270     { MUX_SEL_G3D, 0 },
3271 };
3272
3273 /* list of all parent clock list */
3274 PNAME(mout_aclk_g3d_400_p)  = { "mout_g3d_pll", "aclk_g3d_400", };
3275 PNAME(mout_g3d_pll_p)       = { "oscclk", "fout_g3d_pll", };
3276
3277 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
3278     PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3279         G3D_PLL_LOCK, G3D_PLL_CON0, exynos5433_pll_rates),
3280 };
3281
3282 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
3283     /* MUX_SEL_G3D */
3284     MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3285             MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
3286     MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3287             MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
3288 };
3289
3290 static const struct samsung_div_clock g3d_div_clks[] __initconst = {
3291     /* DIV_G3D */
3292     DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3293             8, 2),
3294     DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
3295             4, 3),
3296     DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3297             0, 3, CLK_SET_RATE_PARENT, 0),
3298 };
3299
3300 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
3301     /* ENABLE_ACLK_G3D */
3302     GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3303             ENABLE_ACLK_G3D, 7, 0, 0),
3304     GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
3305             ENABLE_ACLK_G3D, 6, 0, 0),
3306     GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3307             ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
3308     GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3309             ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
3310     GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3311             ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3312     GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
3313             ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3314     GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
3315             ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3316     GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
3317             ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
3318
3319     /* ENABLE_PCLK_G3D */
3320     GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
3321             ENABLE_PCLK_G3D, 3, 0, 0),
3322     GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
3323             ENABLE_PCLK_G3D, 2, 0, 0),
3324     GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
3325             ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3326     GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
3327             ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3328
3329     /* ENABLE_SCLK_G3D */
3330     GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3331             ENABLE_SCLK_G3D, 0, 0, 0),
3332 };
3333
3334 static const struct samsung_cmu_info g3d_cmu_info __initconst = {
3335     .pll_clks       = g3d_pll_clks,
3336     .nr_pll_clks        = ARRAY_SIZE(g3d_pll_clks),
3337     .mux_clks       = g3d_mux_clks,
3338     .nr_mux_clks        = ARRAY_SIZE(g3d_mux_clks),
3339     .div_clks       = g3d_div_clks,
3340     .nr_div_clks        = ARRAY_SIZE(g3d_div_clks),
3341     .gate_clks      = g3d_gate_clks,
3342     .nr_gate_clks       = ARRAY_SIZE(g3d_gate_clks),
3343     .nr_clk_ids     = G3D_NR_CLK,
3344     .clk_regs       = g3d_clk_regs,
3345     .nr_clk_regs        = ARRAY_SIZE(g3d_clk_regs),
3346     .suspend_regs       = g3d_suspend_regs,
3347     .nr_suspend_regs    = ARRAY_SIZE(g3d_suspend_regs),
3348     .clk_name       = "aclk_g3d_400",
3349 };
3350
3351 /*
3352  * Register offset definitions for CMU_GSCL
3353  */
3354 #define MUX_SEL_GSCL                0x0200
3355 #define MUX_ENABLE_GSCL             0x0300
3356 #define MUX_STAT_GSCL               0x0400
3357 #define ENABLE_ACLK_GSCL            0x0800
3358 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0  0x0804
3359 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1  0x0808
3360 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2  0x080c
3361 #define ENABLE_PCLK_GSCL            0x0900
3362 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0  0x0904
3363 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1  0x0908
3364 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2  0x090c
3365 #define ENABLE_IP_GSCL0             0x0b00
3366 #define ENABLE_IP_GSCL1             0x0b04
3367 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0    0x0b08
3368 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1    0x0b0c
3369 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2    0x0b10
3370
3371 static const unsigned long gscl_clk_regs[] __initconst = {
3372     MUX_SEL_GSCL,
3373     MUX_ENABLE_GSCL,
3374     ENABLE_ACLK_GSCL,
3375     ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
3376     ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
3377     ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
3378     ENABLE_PCLK_GSCL,
3379     ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
3380     ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
3381     ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
3382     ENABLE_IP_GSCL0,
3383     ENABLE_IP_GSCL1,
3384     ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
3385     ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
3386     ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3387 };
3388
3389 static const struct samsung_clk_reg_dump gscl_suspend_regs[] = {
3390     { MUX_SEL_GSCL, 0 },
3391     { ENABLE_ACLK_GSCL, 0xfff },
3392     { ENABLE_PCLK_GSCL, 0xff },
3393 };
3394
3395 /* list of all parent clock list */
3396 PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
3397 PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
3398
3399 static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
3400     /* MUX_SEL_GSCL */
3401     MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3402             aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
3403     MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
3404             aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3405 };
3406
3407 static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
3408     /* ENABLE_ACLK_GSCL */
3409     GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3410             ENABLE_ACLK_GSCL, 11, 0, 0),
3411     GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3412             ENABLE_ACLK_GSCL, 10, 0, 0),
3413     GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3414             ENABLE_ACLK_GSCL, 9, 0, 0),
3415     GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
3416             "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
3417             8, CLK_IGNORE_UNUSED, 0),
3418     GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3419             ENABLE_ACLK_GSCL, 7, 0, 0),
3420     GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3421             ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3422     GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3423             "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
3424             CLK_IGNORE_UNUSED, 0),
3425     GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3426             "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
3427             CLK_IGNORE_UNUSED, 0),
3428     GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3429             ENABLE_ACLK_GSCL, 3, 0, 0),
3430     GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
3431             ENABLE_ACLK_GSCL, 2, 0, 0),
3432     GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
3433             ENABLE_ACLK_GSCL, 1, 0, 0),
3434     GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
3435             ENABLE_ACLK_GSCL, 0, 0, 0),
3436
3437     /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3438     GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3439             ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3440
3441     /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3442     GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3443             ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3444
3445     /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3446     GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3447             ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3448
3449     /* ENABLE_PCLK_GSCL */
3450     GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3451             ENABLE_PCLK_GSCL, 7, 0, 0),
3452     GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3453             ENABLE_PCLK_GSCL, 6, 0, 0),
3454     GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3455             ENABLE_PCLK_GSCL, 5, 0, 0),
3456     GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3457             ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3458     GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
3459             "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3460             3, CLK_IGNORE_UNUSED, 0),
3461     GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
3462             ENABLE_PCLK_GSCL, 2, 0, 0),
3463     GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
3464             ENABLE_PCLK_GSCL, 1, 0, 0),
3465     GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
3466             ENABLE_PCLK_GSCL, 0, 0, 0),
3467
3468     /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3469     GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3470         ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3471
3472     /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3473     GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3474         ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3475
3476     /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3477     GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3478         ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3479 };
3480
3481 static const struct samsung_cmu_info gscl_cmu_info __initconst = {
3482     .mux_clks       = gscl_mux_clks,
3483     .nr_mux_clks        = ARRAY_SIZE(gscl_mux_clks),
3484     .gate_clks      = gscl_gate_clks,
3485     .nr_gate_clks       = ARRAY_SIZE(gscl_gate_clks),
3486     .nr_clk_ids     = GSCL_NR_CLK,
3487     .clk_regs       = gscl_clk_regs,
3488     .nr_clk_regs        = ARRAY_SIZE(gscl_clk_regs),
3489     .suspend_regs       = gscl_suspend_regs,
3490     .nr_suspend_regs    = ARRAY_SIZE(gscl_suspend_regs),
3491     .clk_name       = "aclk_gscl_111",
3492 };
3493
3494 /*
3495  * Register offset definitions for CMU_APOLLO
3496  */
3497 #define APOLLO_PLL_LOCK             0x0000
3498 #define APOLLO_PLL_CON0             0x0100
3499 #define APOLLO_PLL_CON1             0x0104
3500 #define APOLLO_PLL_FREQ_DET         0x010c
3501 #define MUX_SEL_APOLLO0             0x0200
3502 #define MUX_SEL_APOLLO1             0x0204
3503 #define MUX_SEL_APOLLO2             0x0208
3504 #define MUX_ENABLE_APOLLO0          0x0300
3505 #define MUX_ENABLE_APOLLO1          0x0304
3506 #define MUX_ENABLE_APOLLO2          0x0308
3507 #define MUX_STAT_APOLLO0            0x0400
3508 #define MUX_STAT_APOLLO1            0x0404
3509 #define MUX_STAT_APOLLO2            0x0408
3510 #define DIV_APOLLO0             0x0600
3511 #define DIV_APOLLO1             0x0604
3512 #define DIV_APOLLO_PLL_FREQ_DET         0x0608
3513 #define DIV_STAT_APOLLO0            0x0700
3514 #define DIV_STAT_APOLLO1            0x0704
3515 #define DIV_STAT_APOLLO_PLL_FREQ_DET        0x0708
3516 #define ENABLE_ACLK_APOLLO          0x0800
3517 #define ENABLE_PCLK_APOLLO          0x0900
3518 #define ENABLE_SCLK_APOLLO          0x0a00
3519 #define ENABLE_IP_APOLLO0           0x0b00
3520 #define ENABLE_IP_APOLLO1           0x0b04
3521 #define CLKOUT_CMU_APOLLO           0x0c00
3522 #define CLKOUT_CMU_APOLLO_DIV_STAT      0x0c04
3523 #define ARMCLK_STOPCTRL             0x1000
3524 #define APOLLO_PWR_CTRL             0x1020
3525 #define APOLLO_PWR_CTRL2            0x1024
3526 #define APOLLO_INTR_SPREAD_ENABLE       0x1080
3527 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI   0x1084
3528 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION    0x1088
3529
3530 static const unsigned long apollo_clk_regs[] __initconst = {
3531     APOLLO_PLL_LOCK,
3532     APOLLO_PLL_CON0,
3533     APOLLO_PLL_CON1,
3534     APOLLO_PLL_FREQ_DET,
3535     MUX_SEL_APOLLO0,
3536     MUX_SEL_APOLLO1,
3537     MUX_SEL_APOLLO2,
3538     MUX_ENABLE_APOLLO0,
3539     MUX_ENABLE_APOLLO1,
3540     MUX_ENABLE_APOLLO2,
3541     DIV_APOLLO0,
3542     DIV_APOLLO1,
3543     DIV_APOLLO_PLL_FREQ_DET,
3544     ENABLE_ACLK_APOLLO,
3545     ENABLE_PCLK_APOLLO,
3546     ENABLE_SCLK_APOLLO,
3547     ENABLE_IP_APOLLO0,
3548     ENABLE_IP_APOLLO1,
3549     CLKOUT_CMU_APOLLO,
3550     CLKOUT_CMU_APOLLO_DIV_STAT,
3551     ARMCLK_STOPCTRL,
3552     APOLLO_PWR_CTRL,
3553     APOLLO_PWR_CTRL2,
3554     APOLLO_INTR_SPREAD_ENABLE,
3555     APOLLO_INTR_SPREAD_USE_STANDBYWFI,
3556     APOLLO_INTR_SPREAD_BLOCKING_DURATION,
3557 };
3558
3559 /* list of all parent clock list */
3560 PNAME(mout_apollo_pll_p)        = { "oscclk", "fout_apollo_pll", };
3561 PNAME(mout_bus_pll_apollo_user_p)   = { "oscclk", "sclk_bus_pll_apollo", };
3562 PNAME(mout_apollo_p)            = { "mout_apollo_pll",
3563                         "mout_bus_pll_apollo_user", };
3564
3565 static const struct samsung_pll_clock apollo_pll_clks[] __initconst = {
3566     PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3567         APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5433_pll_rates),
3568 };
3569
3570 static const struct samsung_mux_clock apollo_mux_clks[] __initconst = {
3571     /* MUX_SEL_APOLLO0 */
3572     MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3573             MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT |
3574             CLK_RECALC_NEW_RATES, 0),
3575
3576     /* MUX_SEL_APOLLO1 */
3577     MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
3578             mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3579
3580     /* MUX_SEL_APOLLO2 */
3581     MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3582             0, 1, CLK_SET_RATE_PARENT, 0),
3583 };
3584
3585 static const struct samsung_div_clock apollo_div_clks[] __initconst = {
3586     /* DIV_APOLLO0 */
3587     DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3588             DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
3589             CLK_DIVIDER_READ_ONLY),
3590     DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3591             DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
3592             CLK_DIVIDER_READ_ONLY),
3593     DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3594             DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
3595             CLK_DIVIDER_READ_ONLY),
3596     DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3597             DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
3598             CLK_DIVIDER_READ_ONLY),
3599     DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3600             DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
3601             CLK_DIVIDER_READ_ONLY),
3602     DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3603             DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0),
3604     DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
3605             DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0),
3606
3607     /* DIV_APOLLO1 */
3608     DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
3609             DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
3610             CLK_DIVIDER_READ_ONLY),
3611     DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
3612             DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3613             CLK_DIVIDER_READ_ONLY),
3614 };
3615
3616 static const struct samsung_gate_clock apollo_gate_clks[] __initconst = {
3617     /* ENABLE_ACLK_APOLLO */
3618     GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3619             "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3620             6, CLK_IGNORE_UNUSED, 0),
3621     GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
3622             "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3623             5, CLK_IGNORE_UNUSED, 0),
3624     GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
3625             "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3626             4, CLK_IGNORE_UNUSED, 0),
3627     GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
3628             "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3629             3, CLK_IGNORE_UNUSED, 0),
3630     GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
3631             "div_aclk_apollo", ENABLE_ACLK_APOLLO,
3632             2, CLK_IGNORE_UNUSED, 0),
3633     GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
3634             "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3635             1, CLK_IGNORE_UNUSED, 0),
3636     GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
3637             "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3638             0, CLK_IGNORE_UNUSED, 0),
3639
3640     /* ENABLE_PCLK_APOLLO */
3641     GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
3642             "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
3643             2, CLK_IGNORE_UNUSED, 0),
3644     GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
3645             ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3646     GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
3647             "div_pclk_apollo", ENABLE_PCLK_APOLLO,
3648             0, CLK_IGNORE_UNUSED, 0),
3649
3650     /* ENABLE_SCLK_APOLLO */
3651     GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
3652             ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3653     GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3654             ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3655 };
3656
3657 #define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3658         (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3659          ((pclk) << 12) | ((aclk) << 8))
3660
3661 #define E5433_APOLLO_DIV1(hpm, copy) \
3662         (((hpm) << 4) | ((copy) << 0))
3663
3664 static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = {
3665     { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3666     { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3667     { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3668     { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3669     {  900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3670     {  800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3671     {  700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3672     {  600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3673     {  500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3674     {  400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3675     {  0 },
3676 };
3677
3678 static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = {
3679     CPU_CLK(CLK_SCLK_APOLLO, "apolloclk", CLK_MOUT_APOLLO_PLL,
3680             CLK_MOUT_BUS_PLL_APOLLO_USER,
3681             CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200,
3682             exynos5433_apolloclk_d),
3683 };
3684
3685 static const struct samsung_cmu_info apollo_cmu_info __initconst = {
3686     .pll_clks   = apollo_pll_clks,
3687     .nr_pll_clks    = ARRAY_SIZE(apollo_pll_clks),
3688     .mux_clks   = apollo_mux_clks,
3689     .nr_mux_clks    = ARRAY_SIZE(apollo_mux_clks),
3690     .div_clks   = apollo_div_clks,
3691     .nr_div_clks    = ARRAY_SIZE(apollo_div_clks),
3692     .gate_clks  = apollo_gate_clks,
3693     .nr_gate_clks   = ARRAY_SIZE(apollo_gate_clks),
3694     .cpu_clks   = apollo_cpu_clks,
3695     .nr_cpu_clks    = ARRAY_SIZE(apollo_cpu_clks),
3696     .nr_clk_ids = APOLLO_NR_CLK,
3697     .clk_regs   = apollo_clk_regs,
3698     .nr_clk_regs    = ARRAY_SIZE(apollo_clk_regs),
3699 };
3700
3701 static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3702 {
3703     samsung_cmu_register_one(np, &apollo_cmu_info);
3704 }
3705 CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3706         exynos5433_cmu_apollo_init);
3707
3708 /*
3709  * Register offset definitions for CMU_ATLAS
3710  */
3711 #define ATLAS_PLL_LOCK              0x0000
3712 #define ATLAS_PLL_CON0              0x0100
3713 #define ATLAS_PLL_CON1              0x0104
3714 #define ATLAS_PLL_FREQ_DET          0x010c
3715 #define MUX_SEL_ATLAS0              0x0200
3716 #define MUX_SEL_ATLAS1              0x0204
3717 #define MUX_SEL_ATLAS2              0x0208
3718 #define MUX_ENABLE_ATLAS0           0x0300
3719 #define MUX_ENABLE_ATLAS1           0x0304
3720 #define MUX_ENABLE_ATLAS2           0x0308
3721 #define MUX_STAT_ATLAS0             0x0400
3722 #define MUX_STAT_ATLAS1             0x0404
3723 #define MUX_STAT_ATLAS2             0x0408
3724 #define DIV_ATLAS0              0x0600
3725 #define DIV_ATLAS1              0x0604
3726 #define DIV_ATLAS_PLL_FREQ_DET          0x0608
3727 #define DIV_STAT_ATLAS0             0x0700
3728 #define DIV_STAT_ATLAS1             0x0704
3729 #define DIV_STAT_ATLAS_PLL_FREQ_DET     0x0708
3730 #define ENABLE_ACLK_ATLAS           0x0800
3731 #define ENABLE_PCLK_ATLAS           0x0900
3732 #define ENABLE_SCLK_ATLAS           0x0a00
3733 #define ENABLE_IP_ATLAS0            0x0b00
3734 #define ENABLE_IP_ATLAS1            0x0b04
3735 #define CLKOUT_CMU_ATLAS            0x0c00
3736 #define CLKOUT_CMU_ATLAS_DIV_STAT       0x0c04
3737 #define ARMCLK_STOPCTRL             0x1000
3738 #define ATLAS_PWR_CTRL              0x1020
3739 #define ATLAS_PWR_CTRL2             0x1024
3740 #define ATLAS_INTR_SPREAD_ENABLE        0x1080
3741 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI    0x1084
3742 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3743
3744 static const unsigned long atlas_clk_regs[] __initconst = {
3745     ATLAS_PLL_LOCK,
3746     ATLAS_PLL_CON0,
3747     ATLAS_PLL_CON1,
3748     ATLAS_PLL_FREQ_DET,
3749     MUX_SEL_ATLAS0,
3750     MUX_SEL_ATLAS1,
3751     MUX_SEL_ATLAS2,
3752     MUX_ENABLE_ATLAS0,
3753     MUX_ENABLE_ATLAS1,
3754     MUX_ENABLE_ATLAS2,
3755     DIV_ATLAS0,
3756     DIV_ATLAS1,
3757     DIV_ATLAS_PLL_FREQ_DET,
3758     ENABLE_ACLK_ATLAS,
3759     ENABLE_PCLK_ATLAS,
3760     ENABLE_SCLK_ATLAS,
3761     ENABLE_IP_ATLAS0,
3762     ENABLE_IP_ATLAS1,
3763     CLKOUT_CMU_ATLAS,
3764     CLKOUT_CMU_ATLAS_DIV_STAT,
3765     ARMCLK_STOPCTRL,
3766     ATLAS_PWR_CTRL,
3767     ATLAS_PWR_CTRL2,
3768     ATLAS_INTR_SPREAD_ENABLE,
3769     ATLAS_INTR_SPREAD_USE_STANDBYWFI,
3770     ATLAS_INTR_SPREAD_BLOCKING_DURATION,
3771 };
3772
3773 /* list of all parent clock list */
3774 PNAME(mout_atlas_pll_p)         = { "oscclk", "fout_atlas_pll", };
3775 PNAME(mout_bus_pll_atlas_user_p)    = { "oscclk", "sclk_bus_pll_atlas", };
3776 PNAME(mout_atlas_p)         = { "mout_atlas_pll",
3777                         "mout_bus_pll_atlas_user", };
3778
3779 static const struct samsung_pll_clock atlas_pll_clks[] __initconst = {
3780     PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3781         ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5433_pll_rates),
3782 };
3783
3784 static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {
3785     /* MUX_SEL_ATLAS0 */
3786     MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3787             MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT |
3788             CLK_RECALC_NEW_RATES, 0),
3789
3790     /* MUX_SEL_ATLAS1 */
3791     MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
3792             mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3793
3794     /* MUX_SEL_ATLAS2 */
3795     MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
3796             0, 1, CLK_SET_RATE_PARENT, 0),
3797 };
3798
3799 static const struct samsung_div_clock atlas_div_clks[] __initconst = {
3800     /* DIV_ATLAS0 */
3801     DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3802             DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
3803             CLK_DIVIDER_READ_ONLY),
3804     DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
3805             DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
3806             CLK_DIVIDER_READ_ONLY),
3807     DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
3808             DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
3809             CLK_DIVIDER_READ_ONLY),
3810     DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
3811             DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
3812             CLK_DIVIDER_READ_ONLY),
3813     DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
3814             DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
3815             CLK_DIVIDER_READ_ONLY),
3816     DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
3817             DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
3818     DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
3819             DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
3820
3821     /* DIV_ATLAS1 */
3822     DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
3823             DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
3824             CLK_DIVIDER_READ_ONLY),
3825     DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
3826             DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3827             CLK_DIVIDER_READ_ONLY),
3828 };
3829
3830 static const struct samsung_gate_clock atlas_gate_clks[] __initconst = {
3831     /* ENABLE_ACLK_ATLAS */
3832     GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3833             "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3834             9, CLK_IGNORE_UNUSED, 0),
3835     GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
3836             "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3837             8, CLK_IGNORE_UNUSED, 0),
3838     GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
3839             "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3840             7, CLK_IGNORE_UNUSED, 0),
3841     GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
3842             "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3843             6, CLK_IGNORE_UNUSED, 0),
3844     GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
3845             "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3846             5, CLK_IGNORE_UNUSED, 0),
3847     GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
3848             "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3849             4, CLK_IGNORE_UNUSED, 0),
3850     GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
3851             "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3852             3, CLK_IGNORE_UNUSED, 0),
3853     GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
3854             "div_aclk_atlas", ENABLE_ACLK_ATLAS,
3855             2, CLK_IGNORE_UNUSED, 0),
3856     GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3857             ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3858     GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
3859             ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3860
3861     /* ENABLE_PCLK_ATLAS */
3862     GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
3863             "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3864             5, CLK_IGNORE_UNUSED, 0),
3865     GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
3866             "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3867             4, CLK_IGNORE_UNUSED, 0),
3868     GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
3869             "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3870             3, CLK_IGNORE_UNUSED, 0),
3871     GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
3872             ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3873     GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
3874             ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3875     GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
3876             ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3877
3878     /* ENABLE_SCLK_ATLAS */
3879     GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
3880             ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3881     GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3882             ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3883     GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
3884             ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3885     GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
3886             ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3887     GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
3888             ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3889     GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3890             ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3891     GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
3892             ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3893     GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3894             ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3895 };
3896
3897 #define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3898         (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3899          ((pclk) << 12) | ((aclk) << 8))
3900
3901 #define E5433_ATLAS_DIV1(hpm, copy) \
3902         (((hpm) << 4) | ((copy) << 0))
3903
3904 static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = {
3905     { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3906     { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3907     { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3908     { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3909     { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3910     { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3911     { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3912     { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3913     { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3914     { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3915     {  900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3916     {  800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3917     {  700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3918     {  600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3919     {  500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3920     {  0 },
3921 };
3922
3923 static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = {
3924     CPU_CLK(CLK_SCLK_ATLAS, "atlasclk", CLK_MOUT_ATLAS_PLL,
3925             CLK_MOUT_BUS_PLL_ATLAS_USER,
3926             CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200,
3927             exynos5433_atlasclk_d),
3928 };
3929
3930 static const struct samsung_cmu_info atlas_cmu_info __initconst = {
3931     .pll_clks   = atlas_pll_clks,
3932     .nr_pll_clks    = ARRAY_SIZE(atlas_pll_clks),
3933     .mux_clks   = atlas_mux_clks,
3934     .nr_mux_clks    = ARRAY_SIZE(atlas_mux_clks),
3935     .div_clks   = atlas_div_clks,
3936     .nr_div_clks    = ARRAY_SIZE(atlas_div_clks),
3937     .gate_clks  = atlas_gate_clks,
3938     .nr_gate_clks   = ARRAY_SIZE(atlas_gate_clks),
3939     .cpu_clks   = atlas_cpu_clks,
3940     .nr_cpu_clks    = ARRAY_SIZE(atlas_cpu_clks),
3941     .nr_clk_ids = ATLAS_NR_CLK,
3942     .clk_regs   = atlas_clk_regs,
3943     .nr_clk_regs    = ARRAY_SIZE(atlas_clk_regs),
3944 };
3945
3946 static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3947 {
3948     samsung_cmu_register_one(np, &atlas_cmu_info);
3949 }
3950 CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3951         exynos5433_cmu_atlas_init);
3952
3953 /*
3954  * Register offset definitions for CMU_MSCL
3955  */
3956 #define MUX_SEL_MSCL0                   0x0200
3957 #define MUX_SEL_MSCL1                   0x0204
3958 #define MUX_ENABLE_MSCL0                0x0300
3959 #define MUX_ENABLE_MSCL1                0x0304
3960 #define MUX_STAT_MSCL0                  0x0400
3961 #define MUX_STAT_MSCL1                  0x0404
3962 #define DIV_MSCL                    0x0600
3963 #define DIV_STAT_MSCL                   0x0700
3964 #define ENABLE_ACLK_MSCL                0x0800
3965 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0     0x0804
3966 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1     0x0808
3967 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG       0x080c
3968 #define ENABLE_PCLK_MSCL                0x0900
3969 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0     0x0904
3970 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1     0x0908
3971 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG       0x090c
3972 #define ENABLE_SCLK_MSCL                0x0a00
3973 #define ENABLE_IP_MSCL0                 0x0b00
3974 #define ENABLE_IP_MSCL1                 0x0b04
3975 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0       0x0b08
3976 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1       0x0b0c
3977 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG         0x0b10
3978
3979 static const unsigned long mscl_clk_regs[] __initconst = {
3980     MUX_SEL_MSCL0,
3981     MUX_SEL_MSCL1,
3982     MUX_ENABLE_MSCL0,
3983     MUX_ENABLE_MSCL1,
3984     DIV_MSCL,
3985     ENABLE_ACLK_MSCL,
3986     ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
3987     ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
3988     ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
3989     ENABLE_PCLK_MSCL,
3990     ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
3991     ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
3992     ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
3993     ENABLE_SCLK_MSCL,
3994     ENABLE_IP_MSCL0,
3995     ENABLE_IP_MSCL1,
3996     ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
3997     ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
3998     ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
3999 };
4000
4001 static const struct samsung_clk_reg_dump mscl_suspend_regs[] = {
4002     { MUX_SEL_MSCL0, 0 },
4003     { MUX_SEL_MSCL1, 0 },
4004 };
4005
4006 /* list of all parent clock list */
4007 PNAME(mout_sclk_jpeg_user_p)        = { "oscclk", "sclk_jpeg_mscl", };
4008 PNAME(mout_aclk_mscl_400_user_p)    = { "oscclk", "aclk_mscl_400", };
4009 PNAME(mout_sclk_jpeg_p)         = { "mout_sclk_jpeg_user",
4010                     "mout_aclk_mscl_400_user", };
4011
4012 static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
4013     /* MUX_SEL_MSCL0 */
4014     MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
4015             mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
4016     MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
4017             mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
4018
4019     /* MUX_SEL_MSCL1 */
4020     MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
4021             MUX_SEL_MSCL1, 0, 1),
4022 };
4023
4024 static const struct samsung_div_clock mscl_div_clks[] __initconst = {
4025     /* DIV_MSCL */
4026     DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
4027             DIV_MSCL, 0, 3),
4028 };
4029
4030 static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
4031     /* ENABLE_ACLK_MSCL */
4032     GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
4033             ENABLE_ACLK_MSCL, 9, 0, 0),
4034     GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
4035             "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
4036     GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
4037             "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
4038     GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
4039             ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
4040     GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
4041             ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
4042     GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
4043             ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4044     GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
4045             ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4046     GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
4047             ENABLE_ACLK_MSCL, 2, 0, 0),
4048     GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
4049             ENABLE_ACLK_MSCL, 1, 0, 0),
4050     GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
4051             ENABLE_ACLK_MSCL, 0, 0, 0),
4052
4053     /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4054     GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
4055             "mout_aclk_mscl_400_user",
4056             ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
4057             0, CLK_IGNORE_UNUSED, 0),
4058
4059     /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4060     GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
4061             "mout_aclk_mscl_400_user",
4062             ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
4063             0, CLK_IGNORE_UNUSED, 0),
4064
4065     /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
4066     GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
4067             ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
4068             0, CLK_IGNORE_UNUSED, 0),
4069
4070     /* ENABLE_PCLK_MSCL */
4071     GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
4072             ENABLE_PCLK_MSCL, 7, 0, 0),
4073     GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
4074             ENABLE_PCLK_MSCL, 6, 0, 0),
4075     GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
4076             ENABLE_PCLK_MSCL, 5, 0, 0),
4077     GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
4078             ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4079     GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
4080             ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4081     GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
4082             ENABLE_PCLK_MSCL, 2, 0, 0),
4083     GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
4084             ENABLE_PCLK_MSCL, 1, 0, 0),
4085     GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
4086             ENABLE_PCLK_MSCL, 0, 0, 0),
4087
4088     /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4089     GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
4090             ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
4091             0, CLK_IGNORE_UNUSED, 0),
4092
4093     /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4094     GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
4095             ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
4096             0, CLK_IGNORE_UNUSED, 0),
4097
4098     /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
4099     GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
4100             ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
4101             0, CLK_IGNORE_UNUSED, 0),
4102
4103     /* ENABLE_SCLK_MSCL */
4104     GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
4105             CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
4106 };
4107
4108 static const struct samsung_cmu_info mscl_cmu_info __initconst = {
4109     .mux_clks       = mscl_mux_clks,
4110     .nr_mux_clks        = ARRAY_SIZE(mscl_mux_clks),
4111     .div_clks       = mscl_div_clks,
4112     .nr_div_clks        = ARRAY_SIZE(mscl_div_clks),
4113     .gate_clks      = mscl_gate_clks,
4114     .nr_gate_clks       = ARRAY_SIZE(mscl_gate_clks),
4115     .nr_clk_ids     = MSCL_NR_CLK,
4116     .clk_regs       = mscl_clk_regs,
4117     .nr_clk_regs        = ARRAY_SIZE(mscl_clk_regs),
4118     .suspend_regs       = mscl_suspend_regs,
4119     .nr_suspend_regs    = ARRAY_SIZE(mscl_suspend_regs),
4120     .clk_name       = "aclk_mscl_400",
4121 };
4122
4123 /*
4124  * Register offset definitions for CMU_MFC
4125  */
4126 #define MUX_SEL_MFC             0x0200
4127 #define MUX_ENABLE_MFC              0x0300
4128 #define MUX_STAT_MFC                0x0400
4129 #define DIV_MFC                 0x0600
4130 #define DIV_STAT_MFC                0x0700
4131 #define ENABLE_ACLK_MFC             0x0800
4132 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC     0x0804
4133 #define ENABLE_PCLK_MFC             0x0900
4134 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC     0x0904
4135 #define ENABLE_IP_MFC0              0x0b00
4136 #define ENABLE_IP_MFC1              0x0b04
4137 #define ENABLE_IP_MFC_SECURE_SMMU_MFC       0x0b08
4138
4139 static const unsigned long mfc_clk_regs[] __initconst = {
4140     MUX_SEL_MFC,
4141     MUX_ENABLE_MFC,
4142     DIV_MFC,
4143     ENABLE_ACLK_MFC,
4144     ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4145     ENABLE_PCLK_MFC,
4146     ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4147     ENABLE_IP_MFC0,
4148     ENABLE_IP_MFC1,
4149     ENABLE_IP_MFC_SECURE_SMMU_MFC,
4150 };
4151
4152 static const struct samsung_clk_reg_dump mfc_suspend_regs[] = {
4153     { MUX_SEL_MFC, 0 },
4154 };
4155
4156 PNAME(mout_aclk_mfc_400_user_p)     = { "oscclk", "aclk_mfc_400", };
4157
4158 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
4159     /* MUX_SEL_MFC */
4160     MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4161             mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4162 };
4163
4164 static const struct samsung_div_clock mfc_div_clks[] __initconst = {
4165     /* DIV_MFC */
4166     DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4167             DIV_MFC, 0, 2),
4168 };
4169
4170 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
4171     /* ENABLE_ACLK_MFC */
4172     GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4173             ENABLE_ACLK_MFC, 6, 0, 0),
4174     GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4175             ENABLE_ACLK_MFC, 5, 0, 0),
4176     GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4177             ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4178     GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4179             ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4180     GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
4181             ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4182     GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4183             ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4184     GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
4185             ENABLE_ACLK_MFC, 0, 0, 0),
4186
4187     /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4188     GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4189             ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4190             1, CLK_IGNORE_UNUSED, 0),
4191     GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4192             ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4193             0, CLK_IGNORE_UNUSED, 0),
4194
4195     /* ENABLE_PCLK_MFC */
4196     GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
4197             ENABLE_PCLK_MFC, 4, 0, 0),
4198     GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
4199             ENABLE_PCLK_MFC, 3, 0, 0),
4200     GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
4201             ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4202     GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
4203             ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4204     GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
4205             ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4206
4207     /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4208     GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
4209             ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4210             1, CLK_IGNORE_UNUSED, 0),
4211     GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
4212             ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4213             0, CLK_IGNORE_UNUSED, 0),
4214 };
4215
4216 static const struct samsung_cmu_info mfc_cmu_info __initconst = {
4217     .mux_clks       = mfc_mux_clks,
4218     .nr_mux_clks        = ARRAY_SIZE(mfc_mux_clks),
4219     .div_clks       = mfc_div_clks,
4220     .nr_div_clks        = ARRAY_SIZE(mfc_div_clks),
4221     .gate_clks      = mfc_gate_clks,
4222     .nr_gate_clks       = ARRAY_SIZE(mfc_gate_clks),
4223     .nr_clk_ids     = MFC_NR_CLK,
4224     .clk_regs       = mfc_clk_regs,
4225     .nr_clk_regs        = ARRAY_SIZE(mfc_clk_regs),
4226     .suspend_regs       = mfc_suspend_regs,
4227     .nr_suspend_regs    = ARRAY_SIZE(mfc_suspend_regs),
4228     .clk_name       = "aclk_mfc_400",
4229 };
4230
4231 /*
4232  * Register offset definitions for CMU_HEVC
4233  */
4234 #define MUX_SEL_HEVC                0x0200
4235 #define MUX_ENABLE_HEVC             0x0300
4236 #define MUX_STAT_HEVC               0x0400
4237 #define DIV_HEVC                0x0600
4238 #define DIV_STAT_HEVC               0x0700
4239 #define ENABLE_ACLK_HEVC            0x0800
4240 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC   0x0804
4241 #define ENABLE_PCLK_HEVC            0x0900
4242 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC   0x0904
4243 #define ENABLE_IP_HEVC0             0x0b00
4244 #define ENABLE_IP_HEVC1             0x0b04
4245 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC     0x0b08
4246
4247 static const unsigned long hevc_clk_regs[] __initconst = {
4248     MUX_SEL_HEVC,
4249     MUX_ENABLE_HEVC,
4250     DIV_HEVC,
4251     ENABLE_ACLK_HEVC,
4252     ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4253     ENABLE_PCLK_HEVC,
4254     ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4255     ENABLE_IP_HEVC0,
4256     ENABLE_IP_HEVC1,
4257     ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
4258 };
4259
4260 static const struct samsung_clk_reg_dump hevc_suspend_regs[] = {
4261     { MUX_SEL_HEVC, 0 },
4262 };
4263
4264 PNAME(mout_aclk_hevc_400_user_p)    = { "oscclk", "aclk_hevc_400", };
4265
4266 static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {
4267     /* MUX_SEL_HEVC */
4268     MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4269             mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4270 };
4271
4272 static const struct samsung_div_clock hevc_div_clks[] __initconst = {
4273     /* DIV_HEVC */
4274     DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4275             DIV_HEVC, 0, 2),
4276 };
4277
4278 static const struct samsung_gate_clock hevc_gate_clks[] __initconst = {
4279     /* ENABLE_ACLK_HEVC */
4280     GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4281             ENABLE_ACLK_HEVC, 6, 0, 0),
4282     GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
4283             ENABLE_ACLK_HEVC, 5, 0, 0),
4284     GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
4285             ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4286     GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
4287             ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4288     GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
4289             ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4290     GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
4291             ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4292     GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
4293             ENABLE_ACLK_HEVC, 0, 0, 0),
4294
4295     /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
4296     GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
4297             "mout_aclk_hevc_400_user",
4298             ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4299             1, CLK_IGNORE_UNUSED, 0),
4300     GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
4301             "mout_aclk_hevc_400_user",
4302             ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4303             0, CLK_IGNORE_UNUSED, 0),
4304
4305     /* ENABLE_PCLK_HEVC */
4306     GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
4307             ENABLE_PCLK_HEVC, 4, 0, 0),
4308     GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
4309             ENABLE_PCLK_HEVC, 3, 0, 0),
4310     GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
4311             ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4312     GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
4313             ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4314     GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
4315             ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4316
4317     /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
4318     GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
4319             ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4320             1, CLK_IGNORE_UNUSED, 0),
4321     GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
4322             ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4323             0, CLK_IGNORE_UNUSED, 0),
4324 };
4325
4326 static const struct samsung_cmu_info hevc_cmu_info __initconst = {
4327     .mux_clks       = hevc_mux_clks,
4328     .nr_mux_clks        = ARRAY_SIZE(hevc_mux_clks),
4329     .div_clks       = hevc_div_clks,
4330     .nr_div_clks        = ARRAY_SIZE(hevc_div_clks),
4331     .gate_clks      = hevc_gate_clks,
4332     .nr_gate_clks       = ARRAY_SIZE(hevc_gate_clks),
4333     .nr_clk_ids     = HEVC_NR_CLK,
4334     .clk_regs       = hevc_clk_regs,
4335     .nr_clk_regs        = ARRAY_SIZE(hevc_clk_regs),
4336     .suspend_regs       = hevc_suspend_regs,
4337     .nr_suspend_regs    = ARRAY_SIZE(hevc_suspend_regs),
4338     .clk_name       = "aclk_hevc_400",
4339 };
4340
4341 /*
4342  * Register offset definitions for CMU_ISP
4343  */
4344 #define MUX_SEL_ISP         0x0200
4345 #define MUX_ENABLE_ISP          0x0300
4346 #define MUX_STAT_ISP            0x0400
4347 #define DIV_ISP             0x0600
4348 #define DIV_STAT_ISP            0x0700
4349 #define ENABLE_ACLK_ISP0        0x0800
4350 #define ENABLE_ACLK_ISP1        0x0804
4351 #define ENABLE_ACLK_ISP2        0x0808
4352 #define ENABLE_PCLK_ISP         0x0900
4353 #define ENABLE_SCLK_ISP         0x0a00
4354 #define ENABLE_IP_ISP0          0x0b00
4355 #define ENABLE_IP_ISP1          0x0b04
4356 #define ENABLE_IP_ISP2          0x0b08
4357 #define ENABLE_IP_ISP3          0x0b0c
4358
4359 static const unsigned long isp_clk_regs[] __initconst = {
4360     MUX_SEL_ISP,
4361     MUX_ENABLE_ISP,
4362     DIV_ISP,
4363     ENABLE_ACLK_ISP0,
4364     ENABLE_ACLK_ISP1,
4365     ENABLE_ACLK_ISP2,
4366     ENABLE_PCLK_ISP,
4367     ENABLE_SCLK_ISP,
4368     ENABLE_IP_ISP0,
4369     ENABLE_IP_ISP1,
4370     ENABLE_IP_ISP2,
4371     ENABLE_IP_ISP3,
4372 };
4373
4374 static const struct samsung_clk_reg_dump isp_suspend_regs[] = {
4375     { MUX_SEL_ISP, 0 },
4376 };
4377
4378 PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
4379 PNAME(mout_aclk_isp_400_user_p)     = { "oscclk", "aclk_isp_400", };
4380
4381 static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
4382     /* MUX_SEL_ISP */
4383     MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
4384             mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4385     MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
4386             mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4387 };
4388
4389 static const struct samsung_div_clock isp_div_clks[] __initconst = {
4390     /* DIV_ISP */
4391     DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
4392             "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
4393     DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
4394             DIV_ISP, 8, 3),
4395     DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
4396             "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
4397     DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
4398             "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4399 };
4400
4401 static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
4402     /* ENABLE_ACLK_ISP0 */
4403     GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4404             ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4405     GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
4406             ENABLE_ACLK_ISP0, 5, 0, 0),
4407     GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
4408             ENABLE_ACLK_ISP0, 4, 0, 0),
4409     GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
4410             ENABLE_ACLK_ISP0, 3, 0, 0),
4411     GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
4412             ENABLE_ACLK_ISP0, 2, 0, 0),
4413     GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
4414             ENABLE_ACLK_ISP0, 1, 0, 0),
4415     GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
4416             ENABLE_ACLK_ISP0, 0, 0, 0),
4417
4418     /* ENABLE_ACLK_ISP1 */
4419     GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
4420             "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4421             17, CLK_IGNORE_UNUSED, 0),
4422     GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
4423             "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4424             16, CLK_IGNORE_UNUSED, 0),
4425     GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
4426             "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4427             15, CLK_IGNORE_UNUSED, 0),
4428     GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
4429             "div_pclk_isp", ENABLE_ACLK_ISP1,
4430             14, CLK_IGNORE_UNUSED, 0),
4431     GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
4432             "div_pclk_isp", ENABLE_ACLK_ISP1,
4433             13, CLK_IGNORE_UNUSED, 0),
4434     GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
4435             "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4436             12, CLK_IGNORE_UNUSED, 0),
4437     GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
4438             "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4439             11, CLK_IGNORE_UNUSED, 0),
4440     GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
4441             "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4442             10, CLK_IGNORE_UNUSED, 0),
4443     GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
4444             "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4445             9, CLK_IGNORE_UNUSED, 0),
4446     GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
4447             "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4448             8, CLK_IGNORE_UNUSED, 0),
4449     GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
4450             "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4451             7, CLK_IGNORE_UNUSED, 0),
4452     GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
4453             ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4454     GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
4455             ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4456     GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
4457             "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4458             4, CLK_IGNORE_UNUSED, 0),
4459     GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
4460             "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4461             3, CLK_IGNORE_UNUSED, 0),
4462     GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
4463             ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4464     GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
4465             ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4466     GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
4467             ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4468
4469     /* ENABLE_ACLK_ISP2 */
4470     GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
4471             "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4472             13, CLK_IGNORE_UNUSED, 0),
4473     GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
4474             ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4475     GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
4476             ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4477     GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
4478             ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4479     GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
4480             "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4481             9, CLK_IGNORE_UNUSED, 0),
4482     GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
4483             ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4484     GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
4485             ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4486     GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
4487             "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4488             6, CLK_IGNORE_UNUSED, 0),
4489     GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
4490             ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4491     GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
4492             ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4493     GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
4494             ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4495     GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
4496             "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4497             2, CLK_IGNORE_UNUSED, 0),
4498     GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
4499             ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4500     GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
4501             ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4502
4503     /* ENABLE_PCLK_ISP */
4504     GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
4505             ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4506     GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
4507             ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4508     GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
4509             ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4510     GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
4511             ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4512     GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
4513             ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4514     GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
4515             ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4516     GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
4517             ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4518     GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
4519             ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4520     GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
4521             ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4522     GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
4523             ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4524     GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
4525             ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4526     GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
4527             ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4528     GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
4529             ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4530     GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
4531             ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4532     GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
4533             ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4534     GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
4535             ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4536     GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
4537             ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4538     GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
4539             ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4540     GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
4541             "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
4542             7, CLK_IGNORE_UNUSED, 0),
4543     GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
4544             ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4545     GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
4546             ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4547     GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
4548             ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4549     GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
4550             ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4551     GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
4552             ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4553     GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
4554             ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4555     GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
4556             ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4557
4558     /* ENABLE_SCLK_ISP */
4559     GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
4560             "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4561             5, CLK_IGNORE_UNUSED, 0),
4562     GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
4563             "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4564             4, CLK_IGNORE_UNUSED, 0),
4565     GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
4566             "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4567             3, CLK_IGNORE_UNUSED, 0),
4568     GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
4569             "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4570             2, CLK_IGNORE_UNUSED, 0),
4571     GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
4572             "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4573             1, CLK_IGNORE_UNUSED, 0),
4574     GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
4575             "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4576             0, CLK_IGNORE_UNUSED, 0),
4577 };
4578
4579 static const struct samsung_cmu_info isp_cmu_info __initconst = {
4580     .mux_clks       = isp_mux_clks,
4581     .nr_mux_clks        = ARRAY_SIZE(isp_mux_clks),
4582     .div_clks       = isp_div_clks,
4583     .nr_div_clks        = ARRAY_SIZE(isp_div_clks),
4584     .gate_clks      = isp_gate_clks,
4585     .nr_gate_clks       = ARRAY_SIZE(isp_gate_clks),
4586     .nr_clk_ids     = ISP_NR_CLK,
4587     .clk_regs       = isp_clk_regs,
4588     .nr_clk_regs        = ARRAY_SIZE(isp_clk_regs),
4589     .suspend_regs       = isp_suspend_regs,
4590     .nr_suspend_regs    = ARRAY_SIZE(isp_suspend_regs),
4591     .clk_name       = "aclk_isp_400",
4592 };
4593
4594 /*
4595  * Register offset definitions for CMU_CAM0
4596  */
4597 #define MUX_SEL_CAM00           0x0200
4598 #define MUX_SEL_CAM01           0x0204
4599 #define MUX_SEL_CAM02           0x0208
4600 #define MUX_SEL_CAM03           0x020c
4601 #define MUX_SEL_CAM04           0x0210
4602 #define MUX_ENABLE_CAM00        0x0300
4603 #define MUX_ENABLE_CAM01        0x0304
4604 #define MUX_ENABLE_CAM02        0x0308
4605 #define MUX_ENABLE_CAM03        0x030c
4606 #define MUX_ENABLE_CAM04        0x0310
4607 #define MUX_STAT_CAM00          0x0400
4608 #define MUX_STAT_CAM01          0x0404
4609 #define MUX_STAT_CAM02          0x0408
4610 #define MUX_STAT_CAM03          0x040c
4611 #define MUX_STAT_CAM04          0x0410
4612 #define MUX_IGNORE_CAM01        0x0504
4613 #define DIV_CAM00           0x0600
4614 #define DIV_CAM01           0x0604
4615 #define DIV_CAM02           0x0608
4616 #define DIV_CAM03           0x060c
4617 #define DIV_STAT_CAM00          0x0700
4618 #define DIV_STAT_CAM01          0x0704
4619 #define DIV_STAT_CAM02          0x0708
4620 #define DIV_STAT_CAM03          0x070c
4621 #define ENABLE_ACLK_CAM00       0X0800
4622 #define ENABLE_ACLK_CAM01       0X0804
4623 #define ENABLE_ACLK_CAM02       0X0808
4624 #define ENABLE_PCLK_CAM0        0X0900
4625 #define ENABLE_SCLK_CAM0        0X0a00
4626 #define ENABLE_IP_CAM00         0X0b00
4627 #define ENABLE_IP_CAM01         0X0b04
4628 #define ENABLE_IP_CAM02         0X0b08
4629 #define ENABLE_IP_CAM03         0X0b0C
4630
4631 static const unsigned long cam0_clk_regs[] __initconst = {
4632     MUX_SEL_CAM00,
4633     MUX_SEL_CAM01,
4634     MUX_SEL_CAM02,
4635     MUX_SEL_CAM03,
4636     MUX_SEL_CAM04,
4637     MUX_ENABLE_CAM00,
4638     MUX_ENABLE_CAM01,
4639     MUX_ENABLE_CAM02,
4640     MUX_ENABLE_CAM03,
4641     MUX_ENABLE_CAM04,
4642     MUX_IGNORE_CAM01,
4643     DIV_CAM00,
4644     DIV_CAM01,
4645     DIV_CAM02,
4646     DIV_CAM03,
4647     ENABLE_ACLK_CAM00,
4648     ENABLE_ACLK_CAM01,
4649     ENABLE_ACLK_CAM02,
4650     ENABLE_PCLK_CAM0,
4651     ENABLE_SCLK_CAM0,
4652     ENABLE_IP_CAM00,
4653     ENABLE_IP_CAM01,
4654     ENABLE_IP_CAM02,
4655     ENABLE_IP_CAM03,
4656 };
4657
4658 static const struct samsung_clk_reg_dump cam0_suspend_regs[] = {
4659     { MUX_SEL_CAM00, 0 },
4660     { MUX_SEL_CAM01, 0 },
4661     { MUX_SEL_CAM02, 0 },
4662     { MUX_SEL_CAM03, 0 },
4663     { MUX_SEL_CAM04, 0 },
4664 };
4665
4666 PNAME(mout_aclk_cam0_333_user_p)    = { "oscclk", "aclk_cam0_333", };
4667 PNAME(mout_aclk_cam0_400_user_p)    = { "oscclk", "aclk_cam0_400", };
4668 PNAME(mout_aclk_cam0_552_user_p)    = { "oscclk", "aclk_cam0_552", };
4669
4670 PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
4671                           "phyclk_rxbyteclkhs0_s4_phy", };
4672 PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
4673                            "phyclk_rxbyteclkhs0_s2a_phy", };
4674
4675 PNAME(mout_aclk_lite_d_b_p)     = { "mout_aclk_lite_d_a",
4676                         "mout_aclk_cam0_333_user", };
4677 PNAME(mout_aclk_lite_d_a_p)     = { "mout_aclk_cam0_552_user",
4678                         "mout_aclk_cam0_400_user", };
4679 PNAME(mout_aclk_lite_b_b_p)     = { "mout_aclk_lite_b_a",
4680                         "mout_aclk_cam0_333_user", };
4681 PNAME(mout_aclk_lite_b_a_p)     = { "mout_aclk_cam0_552_user",
4682                         "mout_aclk_cam0_400_user", };
4683 PNAME(mout_aclk_lite_a_b_p)     = { "mout_aclk_lite_a_a",
4684                         "mout_aclk_cam0_333_user", };
4685 PNAME(mout_aclk_lite_a_a_p)     = { "mout_aclk_cam0_552_user",
4686                         "mout_aclk_cam0_400_user", };
4687 PNAME(mout_aclk_cam0_400_p)     = { "mout_aclk_cam0_400_user",
4688                         "mout_aclk_cam0_333_user", };
4689
4690 PNAME(mout_aclk_csis1_b_p)      = { "mout_aclk_csis1_a",
4691                         "mout_aclk_cam0_333_user" };
4692 PNAME(mout_aclk_csis1_a_p)      = { "mout_aclk_cam0_552_user",
4693                         "mout_aclk_cam0_400_user", };
4694 PNAME(mout_aclk_csis0_b_p)      = { "mout_aclk_csis0_a",
4695                         "mout_aclk_cam0_333_user", };
4696 PNAME(mout_aclk_csis0_a_p)      = { "mout_aclk_cam0_552_user",
4697                         "mout_aclk-cam0_400_user", };
4698 PNAME(mout_aclk_3aa1_b_p)       = { "mout_aclk_3aa1_a",
4699                         "mout_aclk_cam0_333_user", };
4700 PNAME(mout_aclk_3aa1_a_p)       = { "mout_aclk_cam0_552_user",
4701                         "mout_aclk_cam0_400_user", };
4702 PNAME(mout_aclk_3aa0_b_p)       = { "mout_aclk_3aa0_a",
4703                         "mout_aclk_cam0_333_user", };
4704 PNAME(mout_aclk_3aa0_a_p)       = { "mout_aclk_cam0_552_user",
4705                         "mout_aclk_cam0_400_user", };
4706
4707 PNAME(mout_sclk_lite_freecnt_c_p)   = { "mout_sclk_lite_freecnt_b",
4708                         "div_pclk_lite_d", };
4709 PNAME(mout_sclk_lite_freecnt_b_p)   = { "mout_sclk_lite_freecnt_a",
4710                         "div_pclk_pixelasync_lite_c", };
4711 PNAME(mout_sclk_lite_freecnt_a_p)   = { "div_pclk_lite_a",
4712                         "div_pclk_lite_b", };
4713 PNAME(mout_sclk_pixelasync_lite_c_b_p)  = { "mout_sclk_pixelasync_lite_c_a",
4714                         "mout_aclk_cam0_333_user", };
4715 PNAME(mout_sclk_pixelasync_lite_c_a_p)  = { "mout_aclk_cam0_552_user",
4716                         "mout_aclk_cam0_400_user", };
4717 PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
4718                     "mout_sclk_pixelasync_lite_c_init_a",
4719                     "mout_aclk_cam0_400_user", };
4720 PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
4721                     "mout_aclk_cam0_552_user",
4722                     "mout_aclk_cam0_400_user", };
4723
4724 static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = {
4725     FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
4726             NULL, 0, 100000000),
4727     FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
4728             NULL, 0, 100000000),
4729 };
4730
4731 static const struct samsung_mux_clock cam0_mux_clks[] __initconst = {
4732     /* MUX_SEL_CAM00 */
4733     MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
4734             mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
4735     MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
4736             mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
4737     MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
4738             mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
4739
4740     /* MUX_SEL_CAM01 */
4741     MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
4742             "mout_phyclk_rxbyteclkhs0_s4_user",
4743             mout_phyclk_rxbyteclkhs0_s4_user_p,
4744             MUX_SEL_CAM01, 4, 1),
4745     MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
4746             "mout_phyclk_rxbyteclkhs0_s2a_user",
4747             mout_phyclk_rxbyteclkhs0_s2a_user_p,
4748             MUX_SEL_CAM01, 0, 1),
4749
4750     /* MUX_SEL_CAM02 */
4751     MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
4752             MUX_SEL_CAM02, 24, 1),
4753     MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
4754             MUX_SEL_CAM02, 20, 1),
4755     MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
4756             MUX_SEL_CAM02, 16, 1),
4757     MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
4758             MUX_SEL_CAM02, 12, 1),
4759     MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
4760             MUX_SEL_CAM02, 8, 1),
4761     MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
4762             MUX_SEL_CAM02, 4, 1),
4763     MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
4764             MUX_SEL_CAM02, 0, 1),
4765
4766     /* MUX_SEL_CAM03 */
4767     MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
4768             MUX_SEL_CAM03, 28, 1),
4769     MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
4770             MUX_SEL_CAM03, 24, 1),
4771     MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
4772             MUX_SEL_CAM03, 20, 1),
4773     MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
4774             MUX_SEL_CAM03, 16, 1),
4775     MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
4776             MUX_SEL_CAM03, 12, 1),
4777     MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
4778             MUX_SEL_CAM03, 8, 1),
4779     MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
4780             MUX_SEL_CAM03, 4, 1),
4781     MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
4782             MUX_SEL_CAM03, 0, 1),
4783
4784     /* MUX_SEL_CAM04 */
4785     MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
4786             mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
4787     MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
4788             mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1),
4789     MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
4790             mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1),
4791     MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
4792             mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1),
4793     MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
4794             mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1),
4795     MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
4796             "mout_sclk_pixelasync_lite_c_init_b",
4797             mout_sclk_pixelasync_lite_c_init_b_p,
4798             MUX_SEL_CAM04, 4, 1),
4799     MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
4800             "mout_sclk_pixelasync_lite_c_init_a",
4801             mout_sclk_pixelasync_lite_c_init_a_p,
4802             MUX_SEL_CAM04, 0, 1),
4803 };
4804
4805 static const struct samsung_div_clock cam0_div_clks[] __initconst = {
4806     /* DIV_CAM00 */
4807     DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
4808             DIV_CAM00, 8, 2),
4809     DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
4810             DIV_CAM00, 4, 3),
4811     DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
4812             "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
4813
4814     /* DIV_CAM01 */
4815     DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
4816             DIV_CAM01, 20, 2),
4817     DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
4818             DIV_CAM01, 16, 3),
4819     DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
4820             DIV_CAM01, 12, 2),
4821     DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
4822             DIV_CAM01, 8, 3),
4823     DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
4824             DIV_CAM01, 4, 2),
4825     DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
4826             DIV_CAM01, 0, 3),
4827
4828     /* DIV_CAM02 */
4829     DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
4830             DIV_CAM02, 20, 3),
4831     DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
4832             DIV_CAM02, 16, 3),
4833     DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
4834             DIV_CAM02, 12, 2),
4835     DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
4836             DIV_CAM02, 8, 3),
4837     DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
4838             DIV_CAM02, 4, 2),
4839     DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
4840             DIV_CAM02, 0, 3),
4841
4842     /* DIV_CAM03 */
4843     DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
4844             "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
4845     DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
4846             "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
4847     DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
4848             "div_sclk_pixelasync_lite_c_init",
4849             "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4850 };
4851
4852 static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {
4853     /* ENABLE_ACLK_CAM00 */
4854     GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
4855             6, 0, 0),
4856     GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
4857             5, 0, 0),
4858     GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
4859             4, 0, 0),
4860     GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
4861             3, 0, 0),
4862     GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
4863             ENABLE_ACLK_CAM00, 2, 0, 0),
4864     GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
4865             ENABLE_ACLK_CAM00, 1, 0, 0),
4866     GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
4867             ENABLE_ACLK_CAM00, 0, 0, 0),
4868
4869     /* ENABLE_ACLK_CAM01 */
4870     GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
4871             ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
4872     GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
4873             ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
4874     GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
4875             ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
4876     GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
4877             ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
4878     GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
4879             ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
4880     GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
4881             ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
4882     GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
4883             ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
4884     GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
4885             ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
4886     GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
4887             "div_pclk_lite_d", ENABLE_ACLK_CAM01,
4888             23, CLK_IGNORE_UNUSED, 0),
4889     GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
4890             "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4891             22, CLK_IGNORE_UNUSED, 0),
4892     GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
4893             "div_pclk_lite_b", ENABLE_ACLK_CAM01,
4894             21, CLK_IGNORE_UNUSED, 0),
4895     GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
4896             "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4897             20, CLK_IGNORE_UNUSED, 0),
4898     GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
4899             "div_pclk_lite_a", ENABLE_ACLK_CAM01,
4900             19, CLK_IGNORE_UNUSED, 0),
4901     GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
4902             "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4903             18, CLK_IGNORE_UNUSED, 0),
4904     GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
4905             "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4906             17, CLK_IGNORE_UNUSED, 0),
4907     GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
4908             "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4909             16, CLK_IGNORE_UNUSED, 0),
4910     GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
4911             "div_aclk_3aa1", ENABLE_ACLK_CAM01,
4912             15, CLK_IGNORE_UNUSED, 0),
4913     GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
4914             "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4915             14, CLK_IGNORE_UNUSED, 0),
4916     GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
4917             "div_aclk_3aa0", ENABLE_ACLK_CAM01,
4918             13, CLK_IGNORE_UNUSED, 0),
4919     GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
4920             "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4921             12, CLK_IGNORE_UNUSED, 0),
4922     GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
4923             "div_aclk_lite_d", ENABLE_ACLK_CAM01,
4924             11, CLK_IGNORE_UNUSED, 0),
4925     GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
4926             "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4927             10, CLK_IGNORE_UNUSED, 0),
4928     GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
4929             "div_aclk_lite_b", ENABLE_ACLK_CAM01,
4930             9, CLK_IGNORE_UNUSED, 0),
4931     GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
4932             "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4933             8, CLK_IGNORE_UNUSED, 0),
4934     GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
4935             "div_aclk_lite_a", ENABLE_ACLK_CAM01,
4936             7, CLK_IGNORE_UNUSED, 0),
4937     GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
4938             "div_pclk_cam0_50", ENABLE_ACLK_CAM01,
4939             6, CLK_IGNORE_UNUSED, 0),
4940     GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
4941             ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
4942     GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
4943             ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
4944     GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
4945             ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
4946     GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
4947             ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
4948     GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
4949             ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
4950     GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
4951             ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
4952
4953     /* ENABLE_ACLK_CAM02 */
4954     GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
4955             ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
4956     GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
4957             ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
4958     GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
4959             ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
4960     GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
4961             ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
4962     GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
4963             ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
4964     GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
4965             ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
4966     GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
4967             ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
4968     GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
4969             ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
4970     GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
4971             ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
4972     GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
4973             ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
4974
4975     /* ENABLE_PCLK_CAM0 */
4976     GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
4977             ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
4978     GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
4979             ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
4980     GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
4981             ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
4982     GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
4983             ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
4984     GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
4985             ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
4986     GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
4987             ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
4988     GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
4989             ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
4990     GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
4991             ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
4992     GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
4993             ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
4994     GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
4995             ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
4996     GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
4997             ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
4998     GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
4999             ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
5000     GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
5001             ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
5002     GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
5003             "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5004             12, CLK_IGNORE_UNUSED, 0),
5005     GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
5006             "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5007             11, CLK_IGNORE_UNUSED, 0),
5008     GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
5009             "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5010             10, CLK_IGNORE_UNUSED, 0),
5011     GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
5012             ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
5013     GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
5014             ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
5015     GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
5016             "div_aclk_cam0_200", ENABLE_PCLK_CAM0,
5017             7, CLK_IGNORE_UNUSED, 0),
5018     GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
5019             ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
5020     GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
5021             ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
5022     GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
5023             ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
5024     GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
5025             ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
5026     GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
5027             ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
5028     GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
5029             ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
5030     GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
5031             ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
5032
5033     /* ENABLE_SCLK_CAM0 */
5034     GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
5035             "mout_phyclk_rxbyteclkhs0_s4_user",
5036             ENABLE_SCLK_CAM0, 8, 0, 0),
5037     GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
5038             "mout_phyclk_rxbyteclkhs0_s2a_user",
5039             ENABLE_SCLK_CAM0, 7, 0, 0),
5040     GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
5041             "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
5042     GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
5043             "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
5044     GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
5045             "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
5046     GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
5047             "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
5048     GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
5049             "div_sclk_pixelasync_lite_c",
5050             ENABLE_SCLK_CAM0, 2, 0, 0),
5051     GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
5052             "div_sclk_pixelasync_lite_c_init",
5053             ENABLE_SCLK_CAM0, 1, 0, 0),
5054     GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
5055             "div_sclk_pixelasync_lite_c",
5056             ENABLE_SCLK_CAM0, 0, 0, 0),
5057 };
5058
5059 static const struct samsung_cmu_info cam0_cmu_info __initconst = {
5060     .mux_clks       = cam0_mux_clks,
5061     .nr_mux_clks        = ARRAY_SIZE(cam0_mux_clks),
5062     .div_clks       = cam0_div_clks,
5063     .nr_div_clks        = ARRAY_SIZE(cam0_div_clks),
5064     .gate_clks      = cam0_gate_clks,
5065     .nr_gate_clks       = ARRAY_SIZE(cam0_gate_clks),
5066     .fixed_clks     = cam0_fixed_clks,
5067     .nr_fixed_clks      = ARRAY_SIZE(cam0_fixed_clks),
5068     .nr_clk_ids     = CAM0_NR_CLK,
5069     .clk_regs       = cam0_clk_regs,
5070     .nr_clk_regs        = ARRAY_SIZE(cam0_clk_regs),
5071     .suspend_regs       = cam0_suspend_regs,
5072     .nr_suspend_regs    = ARRAY_SIZE(cam0_suspend_regs),
5073     .clk_name       = "aclk_cam0_400",
5074 };
5075
5076 /*
5077  * Register offset definitions for CMU_CAM1
5078  */
5079 #define MUX_SEL_CAM10           0x0200
5080 #define MUX_SEL_CAM11           0x0204
5081 #define MUX_SEL_CAM12           0x0208
5082 #define MUX_ENABLE_CAM10        0x0300
5083 #define MUX_ENABLE_CAM11        0x0304
5084 #define MUX_ENABLE_CAM12        0x0308
5085 #define MUX_STAT_CAM10          0x0400
5086 #define MUX_STAT_CAM11          0x0404
5087 #define MUX_STAT_CAM12          0x0408
5088 #define MUX_IGNORE_CAM11        0x0504
5089 #define DIV_CAM10           0x0600
5090 #define DIV_CAM11           0x0604
5091 #define DIV_STAT_CAM10          0x0700
5092 #define DIV_STAT_CAM11          0x0704
5093 #define ENABLE_ACLK_CAM10       0X0800
5094 #define ENABLE_ACLK_CAM11       0X0804
5095 #define ENABLE_ACLK_CAM12       0X0808
5096 #define ENABLE_PCLK_CAM1        0X0900
5097 #define ENABLE_SCLK_CAM1        0X0a00
5098 #define ENABLE_IP_CAM10         0X0b00
5099 #define ENABLE_IP_CAM11         0X0b04
5100 #define ENABLE_IP_CAM12         0X0b08
5101
5102 static const unsigned long cam1_clk_regs[] __initconst = {
5103     MUX_SEL_CAM10,
5104     MUX_SEL_CAM11,
5105     MUX_SEL_CAM12,
5106     MUX_ENABLE_CAM10,
5107     MUX_ENABLE_CAM11,
5108     MUX_ENABLE_CAM12,
5109     MUX_IGNORE_CAM11,
5110     DIV_CAM10,
5111     DIV_CAM11,
5112     ENABLE_ACLK_CAM10,
5113     ENABLE_ACLK_CAM11,
5114     ENABLE_ACLK_CAM12,
5115     ENABLE_PCLK_CAM1,
5116     ENABLE_SCLK_CAM1,
5117     ENABLE_IP_CAM10,
5118     ENABLE_IP_CAM11,
5119     ENABLE_IP_CAM12,
5120 };
5121
5122 static const struct samsung_clk_reg_dump cam1_suspend_regs[] = {
5123     { MUX_SEL_CAM10, 0 },
5124     { MUX_SEL_CAM11, 0 },
5125     { MUX_SEL_CAM12, 0 },
5126 };
5127
5128 PNAME(mout_sclk_isp_uart_user_p)    = { "oscclk", "sclk_isp_uart_cam1", };
5129 PNAME(mout_sclk_isp_spi1_user_p)    = { "oscclk", "sclk_isp_spi1_cam1", };
5130 PNAME(mout_sclk_isp_spi0_user_p)    = { "oscclk", "sclk_isp_spi0_cam1", };
5131
5132 PNAME(mout_aclk_cam1_333_user_p)    = { "oscclk", "aclk_cam1_333", };
5133 PNAME(mout_aclk_cam1_400_user_p)    = { "oscclk", "aclk_cam1_400", };
5134 PNAME(mout_aclk_cam1_552_user_p)    = { "oscclk", "aclk_cam1_552", };
5135
5136 PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
5137                            "phyclk_rxbyteclkhs0_s2b_phy", };
5138
5139 PNAME(mout_aclk_csis2_b_p)      = { "mout_aclk_csis2_a",
5140                         "mout_aclk_cam1_333_user", };
5141 PNAME(mout_aclk_csis2_a_p)      = { "mout_aclk_cam1_552_user",
5142                         "mout_aclk_cam1_400_user", };
5143
5144 PNAME(mout_aclk_fd_b_p)         = { "mout_aclk_fd_a",
5145                         "mout_aclk_cam1_333_user", };
5146 PNAME(mout_aclk_fd_a_p)         = { "mout_aclk_cam1_552_user",
5147                         "mout_aclk_cam1_400_user", };
5148
5149 PNAME(mout_aclk_lite_c_b_p)     = { "mout_aclk_lite_c_a",
5150                         "mout_aclk_cam1_333_user", };
5151 PNAME(mout_aclk_lite_c_a_p)     = { "mout_aclk_cam1_552_user",
5152                         "mout_aclk_cam1_400_user", };
5153
5154 static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = {
5155     FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
5156             0, 100000000),
5157 };
5158
5159 static const struct samsung_mux_clock cam1_mux_clks[] __initconst = {
5160     /* MUX_SEL_CAM10 */
5161     MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
5162             mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
5163     MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
5164             mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
5165     MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
5166             mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
5167     MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
5168             mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
5169     MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
5170             mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1),
5171     MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
5172             mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
5173
5174     /* MUX_SEL_CAM11 */
5175     MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
5176             "mout_phyclk_rxbyteclkhs0_s2b_user",
5177             mout_phyclk_rxbyteclkhs0_s2b_user_p,
5178             MUX_SEL_CAM11, 0, 1),
5179
5180     /* MUX_SEL_CAM12 */
5181     MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
5182             MUX_SEL_CAM12, 20, 1),
5183     MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
5184             MUX_SEL_CAM12, 16, 1),
5185     MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
5186             MUX_SEL_CAM12, 12, 1),
5187     MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
5188             MUX_SEL_CAM12, 8, 1),
5189     MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
5190             MUX_SEL_CAM12, 4, 1),
5191     MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
5192             MUX_SEL_CAM12, 0, 1),
5193 };
5194
5195 static const struct samsung_div_clock cam1_div_clks[] __initconst = {
5196     /* DIV_CAM10 */
5197     DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm",
5198             "div_pclk_cam1_83", DIV_CAM10, 16, 2),
5199     DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
5200             "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
5201     DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
5202             "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
5203     DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
5204             "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
5205     DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
5206             DIV_CAM10, 0, 3),
5207
5208     /* DIV_CAM11 */
5209     DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
5210             DIV_CAM11, 16, 3),
5211     DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
5212     DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
5213     DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
5214             DIV_CAM11, 4, 2),
5215     DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
5216             DIV_CAM11, 0, 3),
5217 };
5218
5219 static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {
5220     /* ENABLE_ACLK_CAM10 */
5221     GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
5222             ENABLE_ACLK_CAM10, 4, 0, 0),
5223     GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
5224             ENABLE_ACLK_CAM10, 3, 0, 0),
5225     GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
5226             ENABLE_ACLK_CAM10, 1, 0, 0),
5227     GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
5228             ENABLE_ACLK_CAM10, 0, 0, 0),
5229
5230     /* ENABLE_ACLK_CAM11 */
5231     GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
5232             ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
5233     GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
5234             ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
5235     GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
5236             "div_pclk_lite_c", ENABLE_ACLK_CAM11,
5237             27, CLK_IGNORE_UNUSED, 0),
5238     GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
5239             "div_pclk_cam1_166", ENABLE_ACLK_CAM11,
5240             26, CLK_IGNORE_UNUSED, 0),
5241     GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
5242             "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5243             25, CLK_IGNORE_UNUSED, 0),
5244     GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
5245             "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5246             24, CLK_IGNORE_UNUSED, 0),
5247     GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
5248             "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5249             23, CLK_IGNORE_UNUSED, 0),
5250     GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
5251             "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
5252             22, CLK_IGNORE_UNUSED, 0),
5253     GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
5254             "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5255             21, CLK_IGNORE_UNUSED, 0),
5256     GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
5257             "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5258             20, CLK_IGNORE_UNUSED, 0),
5259     GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
5260             "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5261             19, CLK_IGNORE_UNUSED, 0),
5262     GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
5263             "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5264             18, CLK_IGNORE_UNUSED, 0),
5265     GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
5266             "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5267             17, CLK_IGNORE_UNUSED, 0),
5268     GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
5269             "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5270             16, CLK_IGNORE_UNUSED, 0),
5271     GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
5272             "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5273             15, CLK_IGNORE_UNUSED, 0),
5274     GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
5275             ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
5276     GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
5277             "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5278             13, CLK_IGNORE_UNUSED, 0),
5279     GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
5280             "div_aclk_lite_c", ENABLE_ACLK_CAM11,
5281             12, CLK_IGNORE_UNUSED, 0),
5282     GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
5283             ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
5284     GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
5285             ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
5286     GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
5287             "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5288             9, CLK_IGNORE_UNUSED, 0),
5289     GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
5290             ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
5291     GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
5292             ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
5293     GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
5294             ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
5295     GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
5296             ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
5297     GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
5298             ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
5299     GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
5300             ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
5301     GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
5302             ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
5303     GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
5304             ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
5305     GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
5306             ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
5307
5308     /* ENABLE_ACLK_CAM12 */
5309     GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
5310             "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5311             10, CLK_IGNORE_UNUSED, 0),
5312     GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
5313             ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
5314     GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
5315             "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5316             8, CLK_IGNORE_UNUSED, 0),
5317     GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
5318             ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
5319     GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
5320             ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5321     GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
5322             ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
5323     GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
5324             "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5325             4, CLK_IGNORE_UNUSED, 0),
5326     GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
5327             "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5328             3, CLK_IGNORE_UNUSED, 0),
5329     GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
5330             "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5331             2, CLK_IGNORE_UNUSED, 0),
5332     GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
5333             ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
5334     GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
5335             "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5336             0, CLK_IGNORE_UNUSED, 0),
5337
5338     /* ENABLE_PCLK_CAM1 */
5339     GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
5340             ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
5341     GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
5342             ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
5343     GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
5344             ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
5345     GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
5346             ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
5347     GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
5348             ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
5349     GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
5350             ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
5351     GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
5352             ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
5353     GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
5354             "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5355             20, CLK_IGNORE_UNUSED, 0),
5356     GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
5357             "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5358             19, CLK_IGNORE_UNUSED, 0),
5359     GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
5360             ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
5361     GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
5362             "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5363             17, CLK_IGNORE_UNUSED, 0),
5364     GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
5365             ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
5366     GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
5367             ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
5368     GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
5369             "div_pclk_cam1_166", ENABLE_PCLK_CAM1,
5370             14, CLK_IGNORE_UNUSED, 0),
5371     GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
5372             ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
5373     GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
5374             ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
5375     GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
5376             ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5377     GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
5378             ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5379     GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
5380             ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5381     GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
5382             ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
5383     GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
5384             ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5385     GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
5386             ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5387     GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
5388             ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5389     GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
5390             ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5391     GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83",
5392             ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5393     GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
5394             ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5395     GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
5396             ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5397     GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
5398             ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5399
5400     /* ENABLE_SCLK_CAM1 */
5401     GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
5402             15, 0, 0),
5403     GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
5404             14, 0, 0),
5405     GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
5406             13, 0, 0),
5407     GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
5408             12, 0, 0),
5409     GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
5410             "mout_phyclk_rxbyteclkhs0_s2b_user",
5411             ENABLE_SCLK_CAM1, 11, 0, 0),
5412     GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
5413             ENABLE_SCLK_CAM1, 10, 0, 0),
5414     GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
5415             ENABLE_SCLK_CAM1, 9, 0, 0),
5416     GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
5417             ENABLE_SCLK_CAM1, 7, 0, 0),
5418     GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
5419             ENABLE_SCLK_CAM1, 6, 0, 0),
5420     GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
5421             ENABLE_SCLK_CAM1, 5, 0, 0),
5422     GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
5423             ENABLE_SCLK_CAM1, 4, 0, 0),
5424     GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm",
5425             ENABLE_SCLK_CAM1, 3, 0, 0),
5426     GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
5427             ENABLE_SCLK_CAM1, 2, 0, 0),
5428     GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
5429             ENABLE_SCLK_CAM1, 1, 0, 0),
5430     GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
5431             ENABLE_SCLK_CAM1, 0, 0, 0),
5432 };
5433
5434 static const struct samsung_cmu_info cam1_cmu_info __initconst = {
5435     .mux_clks       = cam1_mux_clks,
5436     .nr_mux_clks        = ARRAY_SIZE(cam1_mux_clks),
5437     .div_clks       = cam1_div_clks,
5438     .nr_div_clks        = ARRAY_SIZE(cam1_div_clks),
5439     .gate_clks      = cam1_gate_clks,
5440     .nr_gate_clks       = ARRAY_SIZE(cam1_gate_clks),
5441     .fixed_clks     = cam1_fixed_clks,
5442     .nr_fixed_clks      = ARRAY_SIZE(cam1_fixed_clks),
5443     .nr_clk_ids     = CAM1_NR_CLK,
5444     .clk_regs       = cam1_clk_regs,
5445     .nr_clk_regs        = ARRAY_SIZE(cam1_clk_regs),
5446     .suspend_regs       = cam1_suspend_regs,
5447     .nr_suspend_regs    = ARRAY_SIZE(cam1_suspend_regs),
5448     .clk_name       = "aclk_cam1_400",
5449 };
5450
5451 /*
5452  * Register offset definitions for CMU_IMEM
5453  */
5454 #define ENABLE_ACLK_IMEM_SLIMSSS        0x080c
5455 #define ENABLE_PCLK_IMEM_SLIMSSS        0x0908
5456
5457 static const unsigned long imem_clk_regs[] __initconst = {
5458     ENABLE_ACLK_IMEM_SLIMSSS,
5459     ENABLE_PCLK_IMEM_SLIMSSS,
5460 };
5461
5462 static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
5463     /* ENABLE_ACLK_IMEM_SLIMSSS */
5464     GATE(CLK_ACLK_SLIMSSS, "aclk_slimsss", "aclk_imem_sssx_266",
5465             ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
5466
5467     /* ENABLE_PCLK_IMEM_SLIMSSS */
5468     GATE(CLK_PCLK_SLIMSSS, "pclk_slimsss", "aclk_imem_200",
5469             ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
5470 };
5471
5472 static const struct samsung_cmu_info imem_cmu_info __initconst = {
5473     .gate_clks      = imem_gate_clks,
5474     .nr_gate_clks       = ARRAY_SIZE(imem_gate_clks),
5475     .nr_clk_ids     = IMEM_NR_CLK,
5476     .clk_regs       = imem_clk_regs,
5477     .nr_clk_regs        = ARRAY_SIZE(imem_clk_regs),
5478     .clk_name       = "aclk_imem_200",
5479 };
5480
5481 struct exynos5433_cmu_data {
5482     struct samsung_clk_reg_dump *clk_save;
5483     unsigned int nr_clk_save;
5484     const struct samsung_clk_reg_dump *clk_suspend;
5485     unsigned int nr_clk_suspend;
5486
5487     struct clk *clk;
5488     struct clk **pclks;
5489     int nr_pclks;
5490
5491     /* must be the last entry */
5492     struct samsung_clk_provider ctx;
5493 };
5494
5495 static int __maybe_unused exynos5433_cmu_suspend(struct device *dev)
5496 {
5497     struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
5498     int i;
5499
5500     samsung_clk_save(data->ctx.reg_base, data->clk_save,
5501              data->nr_clk_save);
5502
5503     for (i = 0; i < data->nr_pclks; i++)
5504         clk_prepare_enable(data->pclks[i]);
5505
5506     /* for suspend some registers have to be set to certain values */
5507     samsung_clk_restore(data->ctx.reg_base, data->clk_suspend,
5508                 data->nr_clk_suspend);
5509
5510     for (i = 0; i < data->nr_pclks; i++)
5511         clk_disable_unprepare(data->pclks[i]);
5512
5513     clk_disable_unprepare(data->clk);
5514
5515     return 0;
5516 }
5517
5518 static int __maybe_unused exynos5433_cmu_resume(struct device *dev)
5519 {
5520     struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
5521     int i;
5522
5523     clk_prepare_enable(data->clk);
5524
5525     for (i = 0; i < data->nr_pclks; i++)
5526         clk_prepare_enable(data->pclks[i]);
5527
5528     samsung_clk_restore(data->ctx.reg_base, data->clk_save,
5529                 data->nr_clk_save);
5530
5531     for (i = 0; i < data->nr_pclks; i++)
5532         clk_disable_unprepare(data->pclks[i]);
5533
5534     return 0;
5535 }
5536
5537 static int __init exynos5433_cmu_probe(struct platform_device *pdev)
5538 {
5539     const struct samsung_cmu_info *info;
5540     struct exynos5433_cmu_data *data;
5541     struct samsung_clk_provider *ctx;
5542     struct device *dev = &pdev->dev;
5543     void __iomem *reg_base;
5544     int i;
5545
5546     info = of_device_get_match_data(dev);
5547
5548     data = devm_kzalloc(dev,
5549                 struct_size(data, ctx.clk_data.hws, info->nr_clk_ids),
5550                 GFP_KERNEL);
5551     if (!data)
5552         return -ENOMEM;
5553     ctx = &data->ctx;
5554
5555     reg_base = devm_platform_ioremap_resource(pdev, 0);
5556     if (IS_ERR(reg_base))
5557         return PTR_ERR(reg_base);
5558
5559     for (i = 0; i < info->nr_clk_ids; ++i)
5560         ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
5561
5562     ctx->clk_data.num = info->nr_clk_ids;
5563     ctx->reg_base = reg_base;
5564     ctx->dev = dev;
5565     spin_lock_init(&ctx->lock);
5566
5567     data->clk_save = samsung_clk_alloc_reg_dump(info->clk_regs,
5568                             info->nr_clk_regs);
5569     if (!data->clk_save)
5570         return -ENOMEM;
5571     data->nr_clk_save = info->nr_clk_regs;
5572     data->clk_suspend = info->suspend_regs;
5573     data->nr_clk_suspend = info->nr_suspend_regs;
5574     data->nr_pclks = of_clk_get_parent_count(dev->of_node);
5575
5576     if (data->nr_pclks > 0) {
5577         data->pclks = devm_kcalloc(dev, sizeof(struct clk *),
5578                        data->nr_pclks, GFP_KERNEL);
5579         if (!data->pclks) {
5580             kfree(data->clk_save);
5581             return -ENOMEM;
5582         }
5583         for (i = 0; i < data->nr_pclks; i++) {
5584             struct clk *clk = of_clk_get(dev->of_node, i);
5585
5586             if (IS_ERR(clk)) {
5587                 kfree(data->clk_save);
5588                 while (--i >= 0)
5589                     clk_put(data->pclks[i]);
5590                 return PTR_ERR(clk);
5591             }
5592             data->pclks[i] = clk;
5593         }
5594     }
5595
5596     if (info->clk_name)
5597         data->clk = clk_get(dev, info->clk_name);
5598     clk_prepare_enable(data->clk);
5599
5600     platform_set_drvdata(pdev, data);
5601
5602     /*
5603      * Enable runtime PM here to allow the clock core using runtime PM
5604      * for the registered clocks. Additionally, we increase the runtime
5605      * PM usage count before registering the clocks, to prevent the
5606      * clock core from runtime suspending the device.
5607      */
5608     pm_runtime_get_noresume(dev);
5609     pm_runtime_set_active(dev);
5610     pm_runtime_enable(dev);
5611
5612     if (info->pll_clks)
5613         samsung_clk_register_pll(ctx, info->pll_clks, info->nr_pll_clks,
5614                      reg_base);
5615     if (info->mux_clks)
5616         samsung_clk_register_mux(ctx, info->mux_clks,
5617                      info->nr_mux_clks);
5618     if (info->div_clks)
5619         samsung_clk_register_div(ctx, info->div_clks,
5620                      info->nr_div_clks);
5621     if (info->gate_clks)
5622         samsung_clk_register_gate(ctx, info->gate_clks,
5623                       info->nr_gate_clks);
5624     if (info->fixed_clks)
5625         samsung_clk_register_fixed_rate(ctx, info->fixed_clks,
5626                         info->nr_fixed_clks);
5627     if (info->fixed_factor_clks)
5628         samsung_clk_register_fixed_factor(ctx, info->fixed_factor_clks,
5629                           info->nr_fixed_factor_clks);
5630
5631     samsung_clk_of_add_provider(dev->of_node, ctx);
5632     pm_runtime_put_sync(dev);
5633
5634     return 0;
5635 }
5636
5637 static const struct of_device_id exynos5433_cmu_of_match[] = {
5638     {
5639         .compatible = "samsung,exynos5433-cmu-aud",
5640         .data = &aud_cmu_info,
5641     }, {
5642         .compatible = "samsung,exynos5433-cmu-cam0",
5643         .data = &cam0_cmu_info,
5644     }, {
5645         .compatible = "samsung,exynos5433-cmu-cam1",
5646         .data = &cam1_cmu_info,
5647     }, {
5648         .compatible = "samsung,exynos5433-cmu-disp",
5649         .data = &disp_cmu_info,
5650     }, {
5651         .compatible = "samsung,exynos5433-cmu-g2d",
5652         .data = &g2d_cmu_info,
5653     }, {
5654         .compatible = "samsung,exynos5433-cmu-g3d",
5655         .data = &g3d_cmu_info,
5656     }, {
5657         .compatible = "samsung,exynos5433-cmu-fsys",
5658         .data = &fsys_cmu_info,
5659     }, {
5660         .compatible = "samsung,exynos5433-cmu-gscl",
5661         .data = &gscl_cmu_info,
5662     }, {
5663         .compatible = "samsung,exynos5433-cmu-mfc",
5664         .data = &mfc_cmu_info,
5665     }, {
5666         .compatible = "samsung,exynos5433-cmu-hevc",
5667         .data = &hevc_cmu_info,
5668     }, {
5669         .compatible = "samsung,exynos5433-cmu-isp",
5670         .data = &isp_cmu_info,
5671     }, {
5672         .compatible = "samsung,exynos5433-cmu-mscl",
5673         .data = &mscl_cmu_info,
5674     }, {
5675         .compatible = "samsung,exynos5433-cmu-imem",
5676         .data = &imem_cmu_info,
5677     }, {
5678     },
5679 };
5680
5681 static const struct dev_pm_ops exynos5433_cmu_pm_ops = {
5682     SET_RUNTIME_PM_OPS(exynos5433_cmu_suspend, exynos5433_cmu_resume,
5683                NULL)
5684     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
5685                      pm_runtime_force_resume)
5686 };
5687
5688 static struct platform_driver exynos5433_cmu_driver __refdata = {
5689     .driver = {
5690         .name = "exynos5433-cmu",
5691         .of_match_table = exynos5433_cmu_of_match,
5692         .suppress_bind_attrs = true,
5693         .pm = &exynos5433_cmu_pm_ops,
5694     },
5695     .probe = exynos5433_cmu_probe,
5696 };
5697
5698 static int __init exynos5433_cmu_init(void)
5699 {
5700     return platform_driver_register(&exynos5433_cmu_driver);
5701 }
5702 core_initcall(exynos5433_cmu_init);