clk/samsung/clk-exynos5410.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
0004  * Author: Tarek Dakhran <t.dakhran@samsung.com>
0005  *
0006  * Common Clock Framework support for Exynos5410 SoC.
0007 */
0008
0009 #include <dt-bindings/clock/exynos5410.h>
0010
0011 #include <linux/clk-provider.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/clk.h>
0015
0016 #include "clk.h"
0017
0018 #define APLL_LOCK               0x0
0019 #define APLL_CON0               0x100
0020 #define CPLL_LOCK               0x10020
0021 #define CPLL_CON0               0x10120
0022 #define EPLL_LOCK               0x10040
0023 #define EPLL_CON0               0x10130
0024 #define MPLL_LOCK               0x4000
0025 #define MPLL_CON0               0x4100
0026 #define BPLL_LOCK               0x20010
0027 #define BPLL_CON0               0x20110
0028 #define KPLL_LOCK               0x28000
0029 #define KPLL_CON0               0x28100
0030
0031 #define SRC_CPU         0x200
0032 #define DIV_CPU0        0x500
0033 #define SRC_CPERI1      0x4204
0034 #define GATE_IP_G2D     0x8800
0035 #define DIV_TOP0        0x10510
0036 #define DIV_TOP1        0x10514
0037 #define DIV_FSYS0       0x10548
0038 #define DIV_FSYS1       0x1054c
0039 #define DIV_FSYS2       0x10550
0040 #define DIV_PERIC0      0x10558
0041 #define DIV_PERIC3      0x10564
0042 #define SRC_TOP0        0x10210
0043 #define SRC_TOP1        0x10214
0044 #define SRC_TOP2        0x10218
0045 #define SRC_FSYS        0x10244
0046 #define SRC_PERIC0      0x10250
0047 #define SRC_MASK_FSYS       0x10340
0048 #define SRC_MASK_PERIC0     0x10350
0049 #define GATE_BUS_FSYS0      0x10740
0050 #define GATE_TOP_SCLK_FSYS  0x10840
0051 #define GATE_TOP_SCLK_PERIC 0x10850
0052 #define GATE_IP_FSYS        0x10944
0053 #define GATE_IP_PERIC       0x10950
0054 #define GATE_IP_PERIS       0x10960
0055 #define SRC_CDREX       0x20200
0056 #define SRC_KFC         0x28200
0057 #define DIV_KFC0        0x28500
0058
0059 /* list of PLLs */
0060 enum exynos5410_plls {
0061     apll, cpll, epll, mpll,
0062     bpll, kpll,
0063     nr_plls                 /* number of PLLs */
0064 };
0065
0066 /* list of all parent clocks */
0067 PNAME(apll_p)       = { "fin_pll", "fout_apll", };
0068 PNAME(bpll_p)       = { "fin_pll", "fout_bpll", };
0069 PNAME(cpll_p)       = { "fin_pll", "fout_cpll" };
0070 PNAME(epll_p)       = { "fin_pll", "fout_epll" };
0071 PNAME(mpll_p)       = { "fin_pll", "fout_mpll", };
0072 PNAME(kpll_p)       = { "fin_pll", "fout_kpll", };
0073
0074 PNAME(mout_cpu_p)   = { "mout_apll", "sclk_mpll", };
0075 PNAME(mout_kfc_p)   = { "mout_kpll", "sclk_mpll", };
0076
0077 PNAME(mpll_user_p)  = { "fin_pll", "sclk_mpll", };
0078 PNAME(bpll_user_p)  = { "fin_pll", "sclk_bpll", };
0079 PNAME(mpll_bpll_p)  = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
0080 PNAME(sclk_mpll_bpll_p) = { "sclk_mpll_bpll", "fin_pll", };
0081
0082 PNAME(group2_p)     = { "fin_pll", "fin_pll", "none", "none",
0083             "none", "none", "sclk_mpll_bpll",
0084              "none", "none", "sclk_cpll" };
0085
0086 static const struct samsung_mux_clock exynos5410_mux_clks[] __initconst = {
0087     MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
0088     MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
0089
0090     MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
0091     MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
0092
0093     MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
0094     MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
0095
0096     MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
0097     MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
0098
0099     MUX(0, "sclk_epll", epll_p, SRC_TOP2, 12, 1),
0100
0101     MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
0102
0103     MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
0104
0105     MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
0106     MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
0107     MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
0108     MUX(0, "mout_usbd300", sclk_mpll_bpll_p, SRC_FSYS, 28, 1),
0109     MUX(0, "mout_usbd301", sclk_mpll_bpll_p, SRC_FSYS, 29, 1),
0110
0111     MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
0112     MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
0113     MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
0114     MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 12, 4),
0115     MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 4),
0116
0117     MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
0118     MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
0119 };
0120
0121 static const struct samsung_div_clock exynos5410_div_clks[] __initconst = {
0122     DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
0123     DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
0124
0125     DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
0126     DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
0127     DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
0128     DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
0129
0130     DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
0131     DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
0132     DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
0133
0134     DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
0135     DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
0136
0137     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
0138     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 20, 4),
0139     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
0140     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 28, 4),
0141
0142     DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
0143     DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
0144     DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
0145
0146     DIV_F(0, "div_mmc_pre0", "div_mmc0",
0147             DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
0148     DIV_F(0, "div_mmc_pre1", "div_mmc1",
0149             DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
0150     DIV_F(0, "div_mmc_pre2", "div_mmc2",
0151             DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
0152
0153     DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
0154     DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
0155     DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
0156     DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
0157
0158     DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
0159
0160     DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
0161     DIV(0, "aclk266", "mpll_user_p", DIV_TOP0, 16, 3),
0162     DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
0163 };
0164
0165 static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = {
0166     GATE(CLK_SSS, "sss", "aclk266", GATE_IP_G2D, 2, 0, 0),
0167     GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
0168     GATE(CLK_WDT, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
0169     GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
0170     GATE(CLK_TMU, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
0171
0172     GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
0173             SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
0174     GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
0175             SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
0176     GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
0177             SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
0178
0179     GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
0180     GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
0181     GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
0182     GATE(CLK_PDMA1, "pdma1", "aclk200", GATE_BUS_FSYS0, 2, 0, 0),
0183     GATE(CLK_PDMA0, "pdma0", "aclk200", GATE_BUS_FSYS0, 1, 0, 0),
0184
0185     GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
0186          GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
0187     GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
0188          GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
0189     GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
0190          GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
0191     GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
0192          GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
0193
0194     GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
0195          GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
0196
0197     GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
0198     GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
0199     GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
0200     GATE(CLK_UART3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
0201     GATE(CLK_I2C0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
0202     GATE(CLK_I2C1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
0203     GATE(CLK_I2C2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
0204     GATE(CLK_I2C3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
0205     GATE(CLK_USI0, "usi0", "aclk66", GATE_IP_PERIC, 10, 0, 0),
0206     GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0),
0207     GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0),
0208     GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0),
0209     GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
0210     GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
0211
0212     GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
0213             SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
0214     GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
0215             SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
0216     GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
0217             SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
0218     GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
0219             SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
0220
0221     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
0222     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
0223     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
0224 };
0225
0226 static const struct samsung_pll_rate_table exynos5410_pll2550x_24mhz_tbl[] __initconst = {
0227     PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
0228     PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0),
0229     PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0),
0230     PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0),
0231     PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
0232     PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0),
0233     PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0),
0234     PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0),
0235     PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
0236     PLL_36XX_RATE(24 * MHZ, 66000000U,  176, 2, 5, 0),
0237 };
0238
0239 static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
0240     [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
0241         APLL_CON0, NULL),
0242     [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
0243         CPLL_CON0, NULL),
0244     [epll] = PLL(pll_2650x, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
0245         EPLL_CON0, NULL),
0246     [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
0247         MPLL_CON0, NULL),
0248     [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
0249         BPLL_CON0, NULL),
0250     [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
0251         KPLL_CON0, NULL),
0252 };
0253
0254 static const struct samsung_cmu_info cmu __initconst = {
0255     .pll_clks   = exynos5410_plls,
0256     .nr_pll_clks    = ARRAY_SIZE(exynos5410_plls),
0257     .mux_clks   = exynos5410_mux_clks,
0258     .nr_mux_clks    = ARRAY_SIZE(exynos5410_mux_clks),
0259     .div_clks   = exynos5410_div_clks,
0260     .nr_div_clks    = ARRAY_SIZE(exynos5410_div_clks),
0261     .gate_clks  = exynos5410_gate_clks,
0262     .nr_gate_clks   = ARRAY_SIZE(exynos5410_gate_clks),
0263     .nr_clk_ids = CLK_NR_CLKS,
0264 };
0265
0266 /* register exynos5410 clocks */
0267 static void __init exynos5410_clk_init(struct device_node *np)
0268 {
0269     struct clk *xxti = of_clk_get(np, 0);
0270
0271     if (!IS_ERR(xxti) && clk_get_rate(xxti) == 24 * MHZ)
0272         exynos5410_plls[epll].rate_table = exynos5410_pll2550x_24mhz_tbl;
0273
0274     samsung_cmu_register_one(np, &cmu);
0275
0276     pr_debug("Exynos5410: clock setup completed.\n");
0277 }
0278 CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);