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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
0004  * Copyright (c) 2013 Linaro Ltd.
0005  * Author: Thomas Abraham <thomas.ab@samsung.com>
0006  *
0007  * Common Clock Framework support for Exynos5250 SoC.
0008 */
0009 
0010 #include <dt-bindings/clock/exynos5250.h>
0011 #include <linux/clk-provider.h>
0012 #include <linux/io.h>
0013 #include <linux/of.h>
0014 #include <linux/of_address.h>
0015 
0016 #include "clk.h"
0017 #include "clk-cpu.h"
0018 #include "clk-exynos5-subcmu.h"
0019 
0020 #define APLL_LOCK       0x0
0021 #define APLL_CON0       0x100
0022 #define SRC_CPU         0x200
0023 #define DIV_CPU0        0x500
0024 #define PWR_CTRL1       0x1020
0025 #define PWR_CTRL2       0x1024
0026 #define MPLL_LOCK       0x4000
0027 #define MPLL_CON0       0x4100
0028 #define SRC_CORE1       0x4204
0029 #define GATE_IP_ACP     0x8800
0030 #define GATE_IP_ISP0        0xc800
0031 #define GATE_IP_ISP1        0xc804
0032 #define CPLL_LOCK       0x10020
0033 #define EPLL_LOCK       0x10030
0034 #define VPLL_LOCK       0x10040
0035 #define GPLL_LOCK       0x10050
0036 #define CPLL_CON0       0x10120
0037 #define EPLL_CON0       0x10130
0038 #define VPLL_CON0       0x10140
0039 #define GPLL_CON0       0x10150
0040 #define SRC_TOP0        0x10210
0041 #define SRC_TOP1        0x10214
0042 #define SRC_TOP2        0x10218
0043 #define SRC_TOP3        0x1021c
0044 #define SRC_GSCL        0x10220
0045 #define SRC_DISP1_0     0x1022c
0046 #define SRC_MAU         0x10240
0047 #define SRC_FSYS        0x10244
0048 #define SRC_GEN         0x10248
0049 #define SRC_PERIC0      0x10250
0050 #define SRC_PERIC1      0x10254
0051 #define SRC_MASK_GSCL       0x10320
0052 #define SRC_MASK_DISP1_0    0x1032c
0053 #define SRC_MASK_MAU        0x10334
0054 #define SRC_MASK_FSYS       0x10340
0055 #define SRC_MASK_GEN        0x10344
0056 #define SRC_MASK_PERIC0     0x10350
0057 #define SRC_MASK_PERIC1     0x10354
0058 #define DIV_TOP0        0x10510
0059 #define DIV_TOP1        0x10514
0060 #define DIV_GSCL        0x10520
0061 #define DIV_DISP1_0     0x1052c
0062 #define DIV_GEN         0x1053c
0063 #define DIV_MAU         0x10544
0064 #define DIV_FSYS0       0x10548
0065 #define DIV_FSYS1       0x1054c
0066 #define DIV_FSYS2       0x10550
0067 #define DIV_PERIC0      0x10558
0068 #define DIV_PERIC1      0x1055c
0069 #define DIV_PERIC2      0x10560
0070 #define DIV_PERIC3      0x10564
0071 #define DIV_PERIC4      0x10568
0072 #define DIV_PERIC5      0x1056c
0073 #define GATE_IP_GSCL        0x10920
0074 #define GATE_IP_DISP1       0x10928
0075 #define GATE_IP_MFC     0x1092c
0076 #define GATE_IP_G3D     0x10930
0077 #define GATE_IP_GEN     0x10934
0078 #define GATE_IP_FSYS        0x10944
0079 #define GATE_IP_PERIC       0x10950
0080 #define GATE_IP_PERIS       0x10960
0081 #define BPLL_LOCK       0x20010
0082 #define BPLL_CON0       0x20110
0083 #define SRC_CDREX       0x20200
0084 #define PLL_DIV2_SEL        0x20a24
0085 
0086 /*Below definitions are used for PWR_CTRL settings*/
0087 #define PWR_CTRL1_CORE2_DOWN_RATIO      (7 << 28)
0088 #define PWR_CTRL1_CORE1_DOWN_RATIO      (7 << 16)
0089 #define PWR_CTRL1_DIV2_DOWN_EN          (1 << 9)
0090 #define PWR_CTRL1_DIV1_DOWN_EN          (1 << 8)
0091 #define PWR_CTRL1_USE_CORE1_WFE         (1 << 5)
0092 #define PWR_CTRL1_USE_CORE0_WFE         (1 << 4)
0093 #define PWR_CTRL1_USE_CORE1_WFI         (1 << 1)
0094 #define PWR_CTRL1_USE_CORE0_WFI         (1 << 0)
0095 
0096 #define PWR_CTRL2_DIV2_UP_EN            (1 << 25)
0097 #define PWR_CTRL2_DIV1_UP_EN            (1 << 24)
0098 #define PWR_CTRL2_DUR_STANDBY2_VAL      (1 << 16)
0099 #define PWR_CTRL2_DUR_STANDBY1_VAL      (1 << 8)
0100 #define PWR_CTRL2_CORE2_UP_RATIO        (1 << 4)
0101 #define PWR_CTRL2_CORE1_UP_RATIO        (1 << 0)
0102 
0103 /* list of PLLs to be registered */
0104 enum exynos5250_plls {
0105     apll, mpll, cpll, epll, vpll, gpll, bpll,
0106     nr_plls         /* number of PLLs */
0107 };
0108 
0109 static void __iomem *reg_base;
0110 
0111 /*
0112  * list of controller registers to be saved and restored during a
0113  * suspend/resume cycle.
0114  */
0115 static const unsigned long exynos5250_clk_regs[] __initconst = {
0116     SRC_CPU,
0117     DIV_CPU0,
0118     PWR_CTRL1,
0119     PWR_CTRL2,
0120     SRC_CORE1,
0121     SRC_TOP0,
0122     SRC_TOP1,
0123     SRC_TOP2,
0124     SRC_TOP3,
0125     SRC_GSCL,
0126     SRC_DISP1_0,
0127     SRC_MAU,
0128     SRC_FSYS,
0129     SRC_GEN,
0130     SRC_PERIC0,
0131     SRC_PERIC1,
0132     SRC_MASK_GSCL,
0133     SRC_MASK_DISP1_0,
0134     SRC_MASK_MAU,
0135     SRC_MASK_FSYS,
0136     SRC_MASK_GEN,
0137     SRC_MASK_PERIC0,
0138     SRC_MASK_PERIC1,
0139     DIV_TOP0,
0140     DIV_TOP1,
0141     DIV_GSCL,
0142     DIV_DISP1_0,
0143     DIV_GEN,
0144     DIV_MAU,
0145     DIV_FSYS0,
0146     DIV_FSYS1,
0147     DIV_FSYS2,
0148     DIV_PERIC0,
0149     DIV_PERIC1,
0150     DIV_PERIC2,
0151     DIV_PERIC3,
0152     DIV_PERIC4,
0153     DIV_PERIC5,
0154     GATE_IP_GSCL,
0155     GATE_IP_MFC,
0156     GATE_IP_G3D,
0157     GATE_IP_GEN,
0158     GATE_IP_FSYS,
0159     GATE_IP_PERIC,
0160     GATE_IP_PERIS,
0161     SRC_CDREX,
0162     PLL_DIV2_SEL,
0163     GATE_IP_DISP1,
0164     GATE_IP_ACP,
0165     GATE_IP_ISP0,
0166     GATE_IP_ISP1,
0167 };
0168 
0169 /* list of all parent clock list */
0170 PNAME(mout_apll_p)  = { "fin_pll", "fout_apll", };
0171 PNAME(mout_cpu_p)   = { "mout_apll", "mout_mpll", };
0172 PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
0173 PNAME(mout_mpll_p)  = { "fin_pll", "mout_mpll_fout" };
0174 PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
0175 PNAME(mout_bpll_p)  = { "fin_pll", "mout_bpll_fout" };
0176 PNAME(mout_vpllsrc_p)   = { "fin_pll", "sclk_hdmi27m" };
0177 PNAME(mout_vpll_p)  = { "mout_vpllsrc", "fout_vpll" };
0178 PNAME(mout_cpll_p)  = { "fin_pll", "fout_cpll" };
0179 PNAME(mout_epll_p)  = { "fin_pll", "fout_epll" };
0180 PNAME(mout_gpll_p)  = { "fin_pll", "fout_gpll" };
0181 PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
0182 PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
0183 PNAME(mout_aclk166_p)   = { "mout_cpll", "mout_mpll_user" };
0184 PNAME(mout_aclk200_p)   = { "mout_mpll_user", "mout_bpll_user" };
0185 PNAME(mout_aclk300_p)   = { "mout_aclk300_disp1_mid",
0186                 "mout_aclk300_disp1_mid1" };
0187 PNAME(mout_aclk400_p)   = { "mout_aclk400_g3d_mid", "mout_gpll" };
0188 PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
0189 PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
0190 PNAME(mout_aclk300_sub_p) = { "fin_pll", "div_aclk300_disp" };
0191 PNAME(mout_aclk300_disp1_mid1_p) = { "mout_vpll", "mout_cpll" };
0192 PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
0193 PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" };
0194 PNAME(mout_hdmi_p)  = { "div_hdmi_pixel", "sclk_hdmiphy" };
0195 PNAME(mout_usb3_p)  = { "mout_mpll_user", "mout_cpll" };
0196 PNAME(mout_group1_p)    = { "fin_pll", "fin_pll", "sclk_hdmi27m",
0197                 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
0198                 "mout_mpll_user", "mout_epll", "mout_vpll",
0199                 "mout_cpll", "none", "none",
0200                 "none", "none", "none",
0201                 "none" };
0202 PNAME(mout_audio0_p)    = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
0203                 "sclk_uhostphy", "fin_pll",
0204                 "mout_mpll_user", "mout_epll", "mout_vpll",
0205                 "mout_cpll", "none", "none",
0206                 "none", "none", "none",
0207                 "none" };
0208 PNAME(mout_audio1_p)    = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
0209                 "sclk_uhostphy", "fin_pll",
0210                 "mout_mpll_user", "mout_epll", "mout_vpll",
0211                 "mout_cpll", "none", "none",
0212                 "none", "none", "none",
0213                 "none" };
0214 PNAME(mout_audio2_p)    = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
0215                 "sclk_uhostphy", "fin_pll",
0216                 "mout_mpll_user", "mout_epll", "mout_vpll",
0217                 "mout_cpll", "none", "none",
0218                 "none", "none", "none",
0219                 "none" };
0220 PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
0221                 "spdif_extclk" };
0222 
0223 /* fixed rate clocks generated outside the soc */
0224 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
0225     FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
0226 };
0227 
0228 /* fixed rate clocks generated inside the soc */
0229 static const struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initconst = {
0230     FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
0231     FRATE(0, "sclk_hdmi27m", NULL, 0, 27000000),
0232     FRATE(0, "sclk_dptxphy", NULL, 0, 24000000),
0233     FRATE(0, "sclk_uhostphy", NULL, 0, 48000000),
0234 };
0235 
0236 static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initconst = {
0237     FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
0238     FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
0239 };
0240 
0241 static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = {
0242     MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
0243 };
0244 
0245 static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
0246     /*
0247      * NOTE: Following table is sorted by (clock domain, register address,
0248      * bitfield shift) triplet in ascending order. When adding new entries,
0249      * please make sure that the order is kept, to avoid merge conflicts
0250      * and make further work with defined data easier.
0251      */
0252 
0253     /*
0254      * CMU_CPU
0255      */
0256     MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
0257                     CLK_SET_RATE_PARENT, 0),
0258     MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
0259 
0260     /*
0261      * CMU_CORE
0262      */
0263     MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
0264 
0265     /*
0266      * CMU_TOP
0267      */
0268     MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
0269     MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
0270     MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1),
0271     MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1),
0272     MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
0273     MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
0274 
0275     MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1,
0276         8, 1),
0277     MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1),
0278     MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
0279 
0280     MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
0281     MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
0282     MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
0283     MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
0284     MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
0285     MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
0286 
0287     MUX(CLK_MOUT_ACLK200_DISP1_SUB, "mout_aclk200_disp1_sub",
0288         mout_aclk200_sub_p, SRC_TOP3, 4, 1),
0289     MUX(CLK_MOUT_ACLK300_DISP1_SUB, "mout_aclk300_disp1_sub",
0290         mout_aclk300_sub_p, SRC_TOP3, 6, 1),
0291     MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
0292     MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1),
0293     MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p,
0294             SRC_TOP3, 20, 1),
0295     MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
0296 
0297     MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
0298     MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
0299     MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
0300     MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
0301     MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
0302 
0303     MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
0304     MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
0305     MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
0306     MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
0307 
0308     MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
0309 
0310     MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
0311     MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
0312     MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
0313     MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
0314     MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
0315     MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
0316 
0317     MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
0318 
0319     MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
0320     MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
0321     MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
0322     MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
0323     MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
0324 
0325     MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
0326     MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
0327     MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
0328     MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
0329     MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
0330     MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
0331 
0332     /*
0333      * CMU_CDREX
0334      */
0335     MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
0336 
0337     MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
0338     MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
0339 };
0340 
0341 static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
0342     /*
0343      * NOTE: Following table is sorted by (clock domain, register address,
0344      * bitfield shift) triplet in ascending order. When adding new entries,
0345      * please make sure that the order is kept, to avoid merge conflicts
0346      * and make further work with defined data easier.
0347      */
0348 
0349     /*
0350      * CMU_CPU
0351      */
0352     DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
0353     DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
0354     DIV(CLK_DIV_ARM2, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
0355 
0356     /*
0357      * CMU_TOP
0358      */
0359     DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3),
0360     DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
0361     DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
0362     DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
0363     DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
0364     DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
0365                             24, 3),
0366     DIV(0, "div_aclk300_disp", "mout_aclk300", DIV_TOP0, 28, 3),
0367 
0368     DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3),
0369     DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
0370 
0371     DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
0372     DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
0373     DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
0374     DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
0375     DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
0376 
0377     DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
0378     DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
0379     DIV_F(0, "div_mipi1_pre", "div_mipi1",
0380             DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
0381     DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
0382     DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4),
0383 
0384     DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
0385 
0386     DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
0387     DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
0388 
0389     DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
0390     DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
0391 
0392     DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
0393     DIV_F(0, "div_mmc_pre0", "div_mmc0",
0394             DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
0395     DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
0396     DIV_F(0, "div_mmc_pre1", "div_mmc1",
0397             DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
0398 
0399     DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
0400     DIV_F(0, "div_mmc_pre2", "div_mmc2",
0401             DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
0402     DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
0403     DIV_F(0, "div_mmc_pre3", "div_mmc3",
0404             DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
0405 
0406     DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
0407     DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
0408     DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
0409     DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
0410 
0411     DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
0412     DIV_F(0, "div_spi_pre0", "div_spi0",
0413             DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
0414     DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
0415     DIV_F(0, "div_spi_pre1", "div_spi1",
0416             DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
0417 
0418     DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
0419     DIV_F(0, "div_spi_pre2", "div_spi2",
0420             DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
0421 
0422     DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
0423 
0424     DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
0425     DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
0426     DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
0427     DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
0428 
0429     DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
0430     DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
0431 };
0432 
0433 static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = {
0434     /*
0435      * NOTE: Following table is sorted by (clock domain, register address,
0436      * bitfield shift) triplet in ascending order. When adding new entries,
0437      * please make sure that the order is kept, to avoid merge conflicts
0438      * and make further work with defined data easier.
0439      */
0440 
0441     /*
0442      * CMU_ACP
0443      */
0444     GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
0445     GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
0446     GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
0447     GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
0448 
0449     /*
0450      * CMU_TOP
0451      */
0452     GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer",
0453             SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
0454     GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
0455             SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
0456     GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
0457             SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
0458     GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa",
0459             SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
0460     GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb",
0461             SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
0462 
0463     GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
0464             SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
0465     GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1",
0466             SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
0467     GATE(CLK_SCLK_DP, "sclk_dp", "div_dp",
0468             SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
0469     GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
0470             SRC_MASK_DISP1_0, 20, 0, 0),
0471 
0472     GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
0473             SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
0474 
0475     GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
0476             SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
0477     GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
0478             SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
0479     GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
0480             SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
0481     GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3",
0482             SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
0483     GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
0484             SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
0485     GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3",
0486             SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
0487 
0488     GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
0489             SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
0490 
0491     GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
0492             SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
0493     GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
0494             SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
0495     GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
0496             SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
0497     GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
0498             SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
0499     GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm",
0500             SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
0501 
0502     GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
0503             SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
0504     GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
0505             SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
0506     GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
0507             SRC_MASK_PERIC1, 4, 0, 0),
0508     GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
0509             SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
0510     GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1",
0511             SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
0512     GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2",
0513             SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
0514 
0515     GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0,
0516         0),
0517     GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0,
0518         0),
0519     GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0,
0520         0),
0521     GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0,
0522         0),
0523     GATE(CLK_CAMIF_TOP, "camif_top", "mout_aclk266_gscl_sub",
0524             GATE_IP_GSCL, 4, 0, 0),
0525     GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
0526     GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
0527     GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub",
0528             GATE_IP_GSCL, 7, 0, 0),
0529     GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub",
0530             GATE_IP_GSCL, 8, 0, 0),
0531     GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub",
0532             GATE_IP_GSCL, 9, 0, 0),
0533     GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
0534             GATE_IP_GSCL, 10, 0, 0),
0535     GATE(CLK_SMMU_FIMC_LITE0, "smmu_fimc_lite0", "mout_aclk266_gscl_sub",
0536             GATE_IP_GSCL, 11, 0, 0),
0537     GATE(CLK_SMMU_FIMC_LITE1, "smmu_fimc_lite1", "mout_aclk266_gscl_sub",
0538             GATE_IP_GSCL, 12, 0, 0),
0539 
0540 
0541     GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
0542     GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0,
0543         0),
0544     GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
0545         0),
0546     GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0,
0547                     CLK_SET_RATE_PARENT, 0),
0548     GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
0549     GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
0550     GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
0551     GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0,
0552         0),
0553     GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0),
0554     GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0),
0555 
0556     GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
0557     GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
0558     GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0),
0559     GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0),
0560     GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0),
0561     GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
0562     GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0),
0563     GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0),
0564     GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0),
0565     GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0),
0566     GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0),
0567     GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0),
0568     GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200",
0569             GATE_IP_FSYS, 24, 0, 0),
0570     GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0,
0571         0),
0572 
0573     GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
0574     GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
0575     GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
0576     GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0),
0577     GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0),
0578     GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0),
0579     GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
0580     GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0),
0581     GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0),
0582     GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0),
0583     GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0),
0584     GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0),
0585     GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0),
0586     GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0),
0587     GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0),
0588     GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
0589     GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0),
0590     GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0),
0591     GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0),
0592     GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0),
0593     GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0),
0594     GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0),
0595     GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
0596     GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0),
0597     GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0),
0598     GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0),
0599     GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0),
0600     GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0),
0601     GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0),
0602 
0603     GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0),
0604     GATE(CLK_SYSREG, "sysreg", "div_aclk66",
0605             GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
0606     GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED,
0607         0),
0608     GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
0609             GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
0610     GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66",
0611             GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
0612     GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66",
0613             GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
0614     GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0),
0615     GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0),
0616     GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0),
0617     GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0),
0618     GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0),
0619     GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0),
0620     GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0),
0621     GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
0622     GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
0623     GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
0624     GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
0625     GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
0626     GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
0627     GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
0628     GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
0629     GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
0630     GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub",
0631             GATE_IP_ISP0, 8, 0, 0),
0632     GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub",
0633             GATE_IP_ISP0, 9, 0, 0),
0634     GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub",
0635             GATE_IP_ISP0, 10, 0, 0),
0636     GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub",
0637             GATE_IP_ISP0, 11, 0, 0),
0638     GATE(CLK_SMMU_FIMC_SCP, "smmu_fimc_scp", "mout_aclk_266_isp_sub",
0639             GATE_IP_ISP0, 12, 0, 0),
0640     GATE(CLK_SMMU_FIMC_MCU, "smmu_fimc_mcu", "mout_aclk_400_isp_sub",
0641             GATE_IP_ISP0, 13, 0, 0),
0642     GATE(CLK_SMMU_FIMC_ODC, "smmu_fimc_odc", "mout_aclk_266_isp_sub",
0643             GATE_IP_ISP1, 4, 0, 0),
0644     GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub",
0645             GATE_IP_ISP1, 5, 0, 0),
0646     GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub",
0647             GATE_IP_ISP1, 6, 0, 0),
0648     GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub",
0649             GATE_IP_ISP1, 7, 0, 0),
0650 };
0651 
0652 static const struct samsung_gate_clock exynos5250_disp_gate_clks[] __initconst = {
0653     GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
0654         0),
0655     GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0,
0656         0),
0657     GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0,
0658         0),
0659     GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
0660     GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0,
0661         0),
0662     GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0,
0663         0),
0664     GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
0665             GATE_IP_DISP1, 9, 0, 0),
0666     GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
0667             GATE_IP_DISP1, 8, 0, 0),
0668 };
0669 
0670 static struct exynos5_subcmu_reg_dump exynos5250_disp_suspend_regs[] = {
0671     { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
0672     { SRC_TOP3, 0, BIT(4) },    /* MUX mout_aclk200_disp1_sub */
0673     { SRC_TOP3, 0, BIT(6) },    /* MUX mout_aclk300_disp1_sub */
0674 };
0675 
0676 static const struct exynos5_subcmu_info exynos5250_disp_subcmu = {
0677     .gate_clks  = exynos5250_disp_gate_clks,
0678     .nr_gate_clks   = ARRAY_SIZE(exynos5250_disp_gate_clks),
0679     .suspend_regs   = exynos5250_disp_suspend_regs,
0680     .nr_suspend_regs = ARRAY_SIZE(exynos5250_disp_suspend_regs),
0681     .pd_name    = "DISP1",
0682 };
0683 
0684 static const struct exynos5_subcmu_info *exynos5250_subcmus[] = {
0685     &exynos5250_disp_subcmu,
0686 };
0687 
0688 static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {
0689     /* sorted in descending order */
0690     /* PLL_36XX_RATE(rate, m, p, s, k) */
0691     PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
0692     /* Not in UM, but need for eDP on snow */
0693     PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
0694     { },
0695 };
0696 
0697 static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = {
0698     /* sorted in descending order */
0699     /* PLL_36XX_RATE(rate, m, p, s, k) */
0700     PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0),
0701     PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762),
0702     PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0),
0703     PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
0704     PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762),
0705     PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923),
0706     PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762),
0707     PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719),
0708     { },
0709 };
0710 
0711 static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {
0712     /* sorted in descending order */
0713     /* PLL_35XX_RATE(fin, rate, m, p, s) */
0714     PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
0715     PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
0716     PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
0717     PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
0718     PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
0719     PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
0720     PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
0721     PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
0722     PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
0723     PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
0724     PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
0725     PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
0726     PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
0727     PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
0728     PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
0729     PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
0730 };
0731 
0732 static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
0733     [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
0734         APLL_CON0, NULL),
0735     [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
0736         MPLL_CON0, NULL),
0737     [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
0738         BPLL_CON0, NULL),
0739     [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
0740         GPLL_CON0, NULL),
0741     [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
0742         CPLL_CON0, NULL),
0743     [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
0744         EPLL_CON0, NULL),
0745     [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
0746         VPLL_LOCK, VPLL_CON0, NULL),
0747 };
0748 
0749 #define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud)      \
0750         ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
0751          ((periph) << 12) | ((acp) << 8) | ((cpud) << 4)))
0752 #define E5250_CPU_DIV1(hpm, copy)                   \
0753         (((hpm) << 4) | (copy))
0754 
0755 static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
0756     { 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
0757     { 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
0758     { 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
0759     { 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
0760     { 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
0761     { 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
0762     { 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
0763     { 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
0764     {  900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
0765     {  800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
0766     {  700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
0767     {  600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
0768     {  500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
0769     {  400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
0770     {  300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
0771     {  200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
0772     {  0 },
0773 };
0774 
0775 static const struct samsung_cpu_clock exynos5250_cpu_clks[] __initconst = {
0776     CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL, CLK_CPU_HAS_DIV1, 0x200,
0777             exynos5250_armclk_d),
0778 };
0779 
0780 static const struct of_device_id ext_clk_match[] __initconst = {
0781     { .compatible = "samsung,clock-xxti", .data = (void *)0, },
0782     { },
0783 };
0784 
0785 /* register exynox5250 clocks */
0786 static void __init exynos5250_clk_init(struct device_node *np)
0787 {
0788     struct samsung_clk_provider *ctx;
0789     unsigned int tmp;
0790     struct clk_hw **hws;
0791 
0792     if (np) {
0793         reg_base = of_iomap(np, 0);
0794         if (!reg_base)
0795             panic("%s: failed to map registers\n", __func__);
0796     } else {
0797         panic("%s: unable to determine soc\n", __func__);
0798     }
0799 
0800     ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
0801     hws = ctx->clk_data.hws;
0802 
0803     samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
0804             ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
0805             ext_clk_match);
0806     samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
0807                 ARRAY_SIZE(exynos5250_pll_pmux_clks));
0808 
0809     if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) {
0810         exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
0811         exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
0812     }
0813 
0814     if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24 * MHZ)
0815         exynos5250_plls[vpll].rate_table =  vpll_24mhz_tbl;
0816 
0817     samsung_clk_register_pll(ctx, exynos5250_plls,
0818             ARRAY_SIZE(exynos5250_plls),
0819             reg_base);
0820     samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
0821             ARRAY_SIZE(exynos5250_fixed_rate_clks));
0822     samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,
0823             ARRAY_SIZE(exynos5250_fixed_factor_clks));
0824     samsung_clk_register_mux(ctx, exynos5250_mux_clks,
0825             ARRAY_SIZE(exynos5250_mux_clks));
0826     samsung_clk_register_div(ctx, exynos5250_div_clks,
0827             ARRAY_SIZE(exynos5250_div_clks));
0828     samsung_clk_register_gate(ctx, exynos5250_gate_clks,
0829             ARRAY_SIZE(exynos5250_gate_clks));
0830     samsung_clk_register_cpu(ctx, exynos5250_cpu_clks,
0831             ARRAY_SIZE(exynos5250_cpu_clks));
0832 
0833     /*
0834      * Enable arm clock down (in idle) and set arm divider
0835      * ratios in WFI/WFE state.
0836      */
0837     tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
0838         PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
0839         PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
0840         PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
0841     __raw_writel(tmp, reg_base + PWR_CTRL1);
0842 
0843     /*
0844      * Enable arm clock up (on exiting idle). Set arm divider
0845      * ratios when not in idle along with the standby duration
0846      * ratios.
0847      */
0848     tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
0849         PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
0850         PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
0851     __raw_writel(tmp, reg_base + PWR_CTRL2);
0852 
0853     samsung_clk_sleep_init(reg_base, exynos5250_clk_regs,
0854                    ARRAY_SIZE(exynos5250_clk_regs));
0855     exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5250_subcmus),
0856                  exynos5250_subcmus);
0857 
0858     samsung_clk_of_add_provider(np, ctx);
0859 
0860     pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
0861         clk_hw_get_rate(hws[CLK_DIV_ARM2]));
0862 }
0863 CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
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