clk/samsung/clk-exynos4412-isp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2017 Samsung Electronics Co., Ltd.
0004  * Author: Marek Szyprowski <m.szyprowski@samsung.com>
0005  *
0006  * Common Clock Framework support for Exynos4412 ISP module.
0007 */
0008
0009 #include <dt-bindings/clock/exynos4.h>
0010 #include <linux/slab.h>
0011 #include <linux/clk.h>
0012 #include <linux/clk-provider.h>
0013 #include <linux/of.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/pm_runtime.h>
0016
0017 #include "clk.h"
0018
0019 /* Exynos4x12 specific registers, which belong to ISP power domain */
0020 #define E4X12_DIV_ISP0      0x0300
0021 #define E4X12_DIV_ISP1      0x0304
0022 #define E4X12_GATE_ISP0     0x0800
0023 #define E4X12_GATE_ISP1     0x0804
0024
0025 /*
0026  * Support for CMU save/restore across system suspends
0027  */
0028 static struct samsung_clk_reg_dump *exynos4x12_save_isp;
0029
0030 static const unsigned long exynos4x12_clk_isp_save[] __initconst = {
0031     E4X12_DIV_ISP0,
0032     E4X12_DIV_ISP1,
0033     E4X12_GATE_ISP0,
0034     E4X12_GATE_ISP1,
0035 };
0036
0037 static struct samsung_div_clock exynos4x12_isp_div_clks[] = {
0038     DIV(CLK_ISP_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
0039     DIV(CLK_ISP_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
0040     DIV(CLK_ISP_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp",
0041         E4X12_DIV_ISP1, 4, 3),
0042     DIV(CLK_ISP_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0",
0043         E4X12_DIV_ISP1, 8, 3),
0044     DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
0045 };
0046
0047 static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = {
0048     GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0),
0049     GATE(CLK_ISP_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 0, 0),
0050     GATE(CLK_ISP_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 0, 0),
0051     GATE(CLK_ISP_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 0, 0),
0052     GATE(CLK_ISP_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 0, 0),
0053     GATE(CLK_ISP_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 0, 0),
0054     GATE(CLK_ISP_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 0, 0),
0055     GATE(CLK_ISP_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 0, 0),
0056     GATE(CLK_ISP_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 0, 0),
0057     GATE(CLK_ISP_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 0, 0),
0058     GATE(CLK_ISP_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
0059          0, 0),
0060     GATE(CLK_ISP_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
0061          0, 0),
0062     GATE(CLK_ISP_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
0063          0, 0),
0064     GATE(CLK_ISP_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
0065          0, 0),
0066     GATE(CLK_ISP_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
0067          0, 0),
0068     GATE(CLK_ISP_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
0069          0, 0),
0070     GATE(CLK_ISP_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
0071          0, 0),
0072     GATE(CLK_ISP_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
0073          0, 0),
0074     GATE(CLK_ISP_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
0075          0, 0),
0076     GATE(CLK_ISP_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 0, 0),
0077     GATE(CLK_ISP_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 0, 0),
0078     GATE(CLK_ISP_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
0079          0, 0),
0080     GATE(CLK_ISP_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
0081          0, 0),
0082     GATE(CLK_ISP_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
0083          0, 0),
0084     GATE(CLK_ISP_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
0085          0, 0),
0086     GATE(CLK_ISP_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
0087          0, 0),
0088 };
0089
0090 static int __maybe_unused exynos4x12_isp_clk_suspend(struct device *dev)
0091 {
0092     struct samsung_clk_provider *ctx = dev_get_drvdata(dev);
0093
0094     samsung_clk_save(ctx->reg_base, exynos4x12_save_isp,
0095              ARRAY_SIZE(exynos4x12_clk_isp_save));
0096     return 0;
0097 }
0098
0099 static int __maybe_unused exynos4x12_isp_clk_resume(struct device *dev)
0100 {
0101     struct samsung_clk_provider *ctx = dev_get_drvdata(dev);
0102
0103     samsung_clk_restore(ctx->reg_base, exynos4x12_save_isp,
0104                 ARRAY_SIZE(exynos4x12_clk_isp_save));
0105     return 0;
0106 }
0107
0108 static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev)
0109 {
0110     struct samsung_clk_provider *ctx;
0111     struct device *dev = &pdev->dev;
0112     struct device_node *np = dev->of_node;
0113     void __iomem *reg_base;
0114
0115     reg_base = devm_platform_ioremap_resource(pdev, 0);
0116     if (IS_ERR(reg_base))
0117         return PTR_ERR(reg_base);
0118
0119     exynos4x12_save_isp = samsung_clk_alloc_reg_dump(exynos4x12_clk_isp_save,
0120                     ARRAY_SIZE(exynos4x12_clk_isp_save));
0121     if (!exynos4x12_save_isp)
0122         return -ENOMEM;
0123
0124     ctx = samsung_clk_init(np, reg_base, CLK_NR_ISP_CLKS);
0125     ctx->dev = dev;
0126
0127     platform_set_drvdata(pdev, ctx);
0128
0129     pm_runtime_set_active(dev);
0130     pm_runtime_enable(dev);
0131     pm_runtime_get_sync(dev);
0132
0133     samsung_clk_register_div(ctx, exynos4x12_isp_div_clks,
0134                  ARRAY_SIZE(exynos4x12_isp_div_clks));
0135     samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks,
0136                   ARRAY_SIZE(exynos4x12_isp_gate_clks));
0137
0138     samsung_clk_of_add_provider(np, ctx);
0139     pm_runtime_put(dev);
0140
0141     return 0;
0142 }
0143
0144 static const struct of_device_id exynos4x12_isp_clk_of_match[] = {
0145     { .compatible = "samsung,exynos4412-isp-clock", },
0146     { },
0147 };
0148
0149 static const struct dev_pm_ops exynos4x12_isp_pm_ops = {
0150     SET_RUNTIME_PM_OPS(exynos4x12_isp_clk_suspend,
0151                exynos4x12_isp_clk_resume, NULL)
0152     SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0153                      pm_runtime_force_resume)
0154 };
0155
0156 static struct platform_driver exynos4x12_isp_clk_driver __refdata = {
0157     .driver = {
0158         .name = "exynos4x12-isp-clk",
0159         .of_match_table = exynos4x12_isp_clk_of_match,
0160         .suppress_bind_attrs = true,
0161         .pm = &exynos4x12_isp_pm_ops,
0162     },
0163     .probe = exynos4x12_isp_clk_probe,
0164 };
0165
0166 static int __init exynos4x12_isp_clk_init(void)
0167 {
0168     return platform_driver_register(&exynos4x12_isp_clk_driver);
0169 }
0170 core_initcall(exynos4x12_isp_clk_init);