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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
0004  * Copyright (c) 2013 Linaro Ltd.
0005  * Author: Thomas Abraham <thomas.ab@samsung.com>
0006  *
0007  * Common Clock Framework support for all Exynos4 SoCs.
0008 */
0009 
0010 #include <dt-bindings/clock/exynos4.h>
0011 #include <linux/slab.h>
0012 #include <linux/clk.h>
0013 #include <linux/clk-provider.h>
0014 #include <linux/io.h>
0015 #include <linux/of.h>
0016 #include <linux/of_address.h>
0017 
0018 #include "clk.h"
0019 #include "clk-cpu.h"
0020 
0021 /* Exynos4 clock controller register offsets */
0022 #define SRC_LEFTBUS     0x4200
0023 #define DIV_LEFTBUS     0x4500
0024 #define GATE_IP_LEFTBUS     0x4800
0025 #define E4X12_GATE_IP_IMAGE 0x4930
0026 #define CLKOUT_CMU_LEFTBUS  0x4a00
0027 #define SRC_RIGHTBUS        0x8200
0028 #define DIV_RIGHTBUS        0x8500
0029 #define GATE_IP_RIGHTBUS    0x8800
0030 #define E4X12_GATE_IP_PERIR 0x8960
0031 #define CLKOUT_CMU_RIGHTBUS 0x8a00
0032 #define EPLL_LOCK       0xc010
0033 #define VPLL_LOCK       0xc020
0034 #define EPLL_CON0       0xc110
0035 #define EPLL_CON1       0xc114
0036 #define EPLL_CON2       0xc118
0037 #define VPLL_CON0       0xc120
0038 #define VPLL_CON1       0xc124
0039 #define VPLL_CON2       0xc128
0040 #define SRC_TOP0        0xc210
0041 #define SRC_TOP1        0xc214
0042 #define SRC_CAM         0xc220
0043 #define SRC_TV          0xc224
0044 #define SRC_MFC         0xc228
0045 #define SRC_G3D         0xc22c
0046 #define E4210_SRC_IMAGE     0xc230
0047 #define SRC_LCD0        0xc234
0048 #define E4210_SRC_LCD1      0xc238
0049 #define E4X12_SRC_ISP       0xc238
0050 #define SRC_MAUDIO      0xc23c
0051 #define SRC_FSYS        0xc240
0052 #define SRC_PERIL0      0xc250
0053 #define SRC_PERIL1      0xc254
0054 #define E4X12_SRC_CAM1      0xc258
0055 #define SRC_MASK_TOP        0xc310
0056 #define SRC_MASK_CAM        0xc320
0057 #define SRC_MASK_TV     0xc324
0058 #define SRC_MASK_LCD0       0xc334
0059 #define E4210_SRC_MASK_LCD1 0xc338
0060 #define E4X12_SRC_MASK_ISP  0xc338
0061 #define SRC_MASK_MAUDIO     0xc33c
0062 #define SRC_MASK_FSYS       0xc340
0063 #define SRC_MASK_PERIL0     0xc350
0064 #define SRC_MASK_PERIL1     0xc354
0065 #define DIV_TOP         0xc510
0066 #define DIV_CAM         0xc520
0067 #define DIV_TV          0xc524
0068 #define DIV_MFC         0xc528
0069 #define DIV_G3D         0xc52c
0070 #define DIV_IMAGE       0xc530
0071 #define DIV_LCD0        0xc534
0072 #define E4210_DIV_LCD1      0xc538
0073 #define E4X12_DIV_ISP       0xc538
0074 #define DIV_MAUDIO      0xc53c
0075 #define DIV_FSYS0       0xc540
0076 #define DIV_FSYS1       0xc544
0077 #define DIV_FSYS2       0xc548
0078 #define DIV_FSYS3       0xc54c
0079 #define DIV_PERIL0      0xc550
0080 #define DIV_PERIL1      0xc554
0081 #define DIV_PERIL2      0xc558
0082 #define DIV_PERIL3      0xc55c
0083 #define DIV_PERIL4      0xc560
0084 #define DIV_PERIL5      0xc564
0085 #define E4X12_DIV_CAM1      0xc568
0086 #define E4X12_GATE_BUS_FSYS1    0xc744
0087 #define GATE_SCLK_CAM       0xc820
0088 #define GATE_IP_CAM     0xc920
0089 #define GATE_IP_TV      0xc924
0090 #define GATE_IP_MFC     0xc928
0091 #define GATE_IP_G3D     0xc92c
0092 #define E4210_GATE_IP_IMAGE 0xc930
0093 #define GATE_IP_LCD0        0xc934
0094 #define E4210_GATE_IP_LCD1  0xc938
0095 #define E4X12_GATE_IP_ISP   0xc938
0096 #define E4X12_GATE_IP_MAUDIO    0xc93c
0097 #define GATE_IP_FSYS        0xc940
0098 #define GATE_IP_GPS     0xc94c
0099 #define GATE_IP_PERIL       0xc950
0100 #define E4210_GATE_IP_PERIR 0xc960
0101 #define GATE_BLOCK      0xc970
0102 #define CLKOUT_CMU_TOP      0xca00
0103 #define E4X12_MPLL_LOCK     0x10008
0104 #define E4X12_MPLL_CON0     0x10108
0105 #define SRC_DMC         0x10200
0106 #define SRC_MASK_DMC        0x10300
0107 #define DIV_DMC0        0x10500
0108 #define DIV_DMC1        0x10504
0109 #define GATE_IP_DMC     0x10900
0110 #define CLKOUT_CMU_DMC      0x10a00
0111 #define APLL_LOCK       0x14000
0112 #define E4210_MPLL_LOCK     0x14008
0113 #define APLL_CON0       0x14100
0114 #define E4210_MPLL_CON0     0x14108
0115 #define SRC_CPU         0x14200
0116 #define DIV_CPU0        0x14500
0117 #define DIV_CPU1        0x14504
0118 #define GATE_SCLK_CPU       0x14800
0119 #define GATE_IP_CPU     0x14900
0120 #define CLKOUT_CMU_CPU      0x14a00
0121 #define PWR_CTRL1       0x15020
0122 #define E4X12_PWR_CTRL2     0x15024
0123 
0124 /* Below definitions are used for PWR_CTRL settings */
0125 #define PWR_CTRL1_CORE2_DOWN_RATIO(x)       (((x) & 0x7) << 28)
0126 #define PWR_CTRL1_CORE1_DOWN_RATIO(x)       (((x) & 0x7) << 16)
0127 #define PWR_CTRL1_DIV2_DOWN_EN          (1 << 9)
0128 #define PWR_CTRL1_DIV1_DOWN_EN          (1 << 8)
0129 #define PWR_CTRL1_USE_CORE3_WFE         (1 << 7)
0130 #define PWR_CTRL1_USE_CORE2_WFE         (1 << 6)
0131 #define PWR_CTRL1_USE_CORE1_WFE         (1 << 5)
0132 #define PWR_CTRL1_USE_CORE0_WFE         (1 << 4)
0133 #define PWR_CTRL1_USE_CORE3_WFI         (1 << 3)
0134 #define PWR_CTRL1_USE_CORE2_WFI         (1 << 2)
0135 #define PWR_CTRL1_USE_CORE1_WFI         (1 << 1)
0136 #define PWR_CTRL1_USE_CORE0_WFI         (1 << 0)
0137 
0138 /* the exynos4 soc type */
0139 enum exynos4_soc {
0140     EXYNOS4210,
0141     EXYNOS4X12,
0142 };
0143 
0144 /* list of PLLs to be registered */
0145 enum exynos4_plls {
0146     apll, mpll, epll, vpll,
0147     nr_plls         /* number of PLLs */
0148 };
0149 
0150 static void __iomem *reg_base;
0151 static enum exynos4_soc exynos4_soc;
0152 
0153 /*
0154  * list of controller registers to be saved and restored during a
0155  * suspend/resume cycle.
0156  */
0157 static const unsigned long exynos4210_clk_save[] __initconst = {
0158     E4210_SRC_IMAGE,
0159     E4210_SRC_LCD1,
0160     E4210_SRC_MASK_LCD1,
0161     E4210_DIV_LCD1,
0162     E4210_GATE_IP_IMAGE,
0163     E4210_GATE_IP_LCD1,
0164     E4210_GATE_IP_PERIR,
0165     E4210_MPLL_CON0,
0166     PWR_CTRL1,
0167 };
0168 
0169 static const unsigned long exynos4x12_clk_save[] __initconst = {
0170     E4X12_GATE_IP_IMAGE,
0171     E4X12_GATE_IP_PERIR,
0172     E4X12_SRC_CAM1,
0173     E4X12_DIV_ISP,
0174     E4X12_DIV_CAM1,
0175     E4X12_MPLL_CON0,
0176     PWR_CTRL1,
0177     E4X12_PWR_CTRL2,
0178 };
0179 
0180 static const unsigned long exynos4_clk_regs[] __initconst = {
0181     EPLL_LOCK,
0182     VPLL_LOCK,
0183     EPLL_CON0,
0184     EPLL_CON1,
0185     EPLL_CON2,
0186     VPLL_CON0,
0187     VPLL_CON1,
0188     VPLL_CON2,
0189     SRC_LEFTBUS,
0190     DIV_LEFTBUS,
0191     GATE_IP_LEFTBUS,
0192     SRC_RIGHTBUS,
0193     DIV_RIGHTBUS,
0194     GATE_IP_RIGHTBUS,
0195     SRC_TOP0,
0196     SRC_TOP1,
0197     SRC_CAM,
0198     SRC_TV,
0199     SRC_MFC,
0200     SRC_G3D,
0201     SRC_LCD0,
0202     SRC_MAUDIO,
0203     SRC_FSYS,
0204     SRC_PERIL0,
0205     SRC_PERIL1,
0206     SRC_MASK_TOP,
0207     SRC_MASK_CAM,
0208     SRC_MASK_TV,
0209     SRC_MASK_LCD0,
0210     SRC_MASK_MAUDIO,
0211     SRC_MASK_FSYS,
0212     SRC_MASK_PERIL0,
0213     SRC_MASK_PERIL1,
0214     DIV_TOP,
0215     DIV_CAM,
0216     DIV_TV,
0217     DIV_MFC,
0218     DIV_G3D,
0219     DIV_IMAGE,
0220     DIV_LCD0,
0221     DIV_MAUDIO,
0222     DIV_FSYS0,
0223     DIV_FSYS1,
0224     DIV_FSYS2,
0225     DIV_FSYS3,
0226     DIV_PERIL0,
0227     DIV_PERIL1,
0228     DIV_PERIL2,
0229     DIV_PERIL3,
0230     DIV_PERIL4,
0231     DIV_PERIL5,
0232     GATE_SCLK_CAM,
0233     GATE_IP_CAM,
0234     GATE_IP_TV,
0235     GATE_IP_MFC,
0236     GATE_IP_G3D,
0237     GATE_IP_LCD0,
0238     GATE_IP_FSYS,
0239     GATE_IP_GPS,
0240     GATE_IP_PERIL,
0241     GATE_BLOCK,
0242     SRC_MASK_DMC,
0243     SRC_DMC,
0244     DIV_DMC0,
0245     DIV_DMC1,
0246     GATE_IP_DMC,
0247     APLL_CON0,
0248     SRC_CPU,
0249     DIV_CPU0,
0250     DIV_CPU1,
0251     GATE_SCLK_CPU,
0252     GATE_IP_CPU,
0253     CLKOUT_CMU_LEFTBUS,
0254     CLKOUT_CMU_RIGHTBUS,
0255     CLKOUT_CMU_TOP,
0256     CLKOUT_CMU_DMC,
0257     CLKOUT_CMU_CPU,
0258 };
0259 
0260 static const struct samsung_clk_reg_dump src_mask_suspend[] = {
0261     { .offset = VPLL_CON0,          .value = 0x80600302, },
0262     { .offset = EPLL_CON0,          .value = 0x806F0302, },
0263     { .offset = SRC_MASK_TOP,       .value = 0x00000001, },
0264     { .offset = SRC_MASK_CAM,       .value = 0x11111111, },
0265     { .offset = SRC_MASK_TV,        .value = 0x00000111, },
0266     { .offset = SRC_MASK_LCD0,      .value = 0x00001111, },
0267     { .offset = SRC_MASK_MAUDIO,        .value = 0x00000001, },
0268     { .offset = SRC_MASK_FSYS,      .value = 0x01011111, },
0269     { .offset = SRC_MASK_PERIL0,        .value = 0x01111111, },
0270     { .offset = SRC_MASK_PERIL1,        .value = 0x01110111, },
0271     { .offset = SRC_MASK_DMC,       .value = 0x00010000, },
0272 };
0273 
0274 static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = {
0275     { .offset = E4210_SRC_MASK_LCD1,    .value = 0x00001111, },
0276 };
0277 
0278 /* list of all parent clock list */
0279 PNAME(mout_apll_p)  = { "fin_pll", "fout_apll", };
0280 PNAME(mout_mpll_p)  = { "fin_pll", "fout_mpll", };
0281 PNAME(mout_epll_p)  = { "fin_pll", "fout_epll", };
0282 PNAME(mout_vpllsrc_p)   = { "fin_pll", "sclk_hdmi24m", };
0283 PNAME(mout_vpll_p)  = { "fin_pll", "fout_vpll", };
0284 PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
0285 PNAME(mout_mfc_p)   = { "mout_mfc0", "mout_mfc1", };
0286 PNAME(mout_g3d_p)   = { "mout_g3d0", "mout_g3d1", };
0287 PNAME(mout_g2d_p)   = { "mout_g2d0", "mout_g2d1", };
0288 PNAME(mout_hdmi_p)  = { "sclk_pixel", "sclk_hdmiphy", };
0289 PNAME(mout_jpeg_p)  = { "mout_jpeg0", "mout_jpeg1", };
0290 PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
0291                 "spdif_extclk", };
0292 PNAME(mout_onenand_p)  = {"aclk133", "aclk160", };
0293 PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
0294 
0295 /* Exynos 4210-specific parent groups */
0296 PNAME(sclk_vpll_p4210)  = { "mout_vpllsrc", "fout_vpll", };
0297 PNAME(mout_core_p4210)  = { "mout_apll", "sclk_mpll", };
0298 PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", };
0299 PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m",
0300                 "sclk_usbphy0", "none", "sclk_hdmiphy",
0301                 "sclk_mpll", "sclk_epll", "sclk_vpll", };
0302 PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
0303                 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
0304                 "sclk_epll", "sclk_vpll" };
0305 PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
0306                 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
0307                 "sclk_epll", "sclk_vpll", };
0308 PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
0309                 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
0310                 "sclk_epll", "sclk_vpll", };
0311 PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
0312 PNAME(mout_dac_p4210)   = { "sclk_vpll", "sclk_hdmiphy", };
0313 PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
0314                 "sclk_usbphy1", "sclk_hdmiphy", "none",
0315                 "sclk_epll", "sclk_vpll" };
0316 PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
0317                 "div_gdl", "div_gpl" };
0318 PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
0319                 "div_gdr", "div_gpr" };
0320 PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
0321                 "sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy",
0322                 "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
0323                 "aclk160", "aclk133", "aclk200", "aclk100",
0324                 "sclk_mfc", "sclk_g3d", "sclk_g2d",
0325                 "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
0326                 "s_rxbyteclkhs0_4l" };
0327 PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc",
0328                 "div_dphy", "none", "div_pwi" };
0329 PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2",
0330                 "none", "arm_clk_div_2", "div_corem0",
0331                 "div_corem1", "div_corem0", "div_atb",
0332                 "div_periph", "div_pclk_dbg", "div_hpm" };
0333 
0334 /* Exynos 4x12-specific parent groups */
0335 PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
0336 PNAME(mout_core_p4x12)  = { "mout_apll", "mout_mpll_user_c", };
0337 PNAME(mout_gdl_p4x12)   = { "mout_mpll_user_l", "sclk_apll", };
0338 PNAME(mout_gdr_p4x12)   = { "mout_mpll_user_r", "sclk_apll", };
0339 PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
0340 PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
0341                 "none", "sclk_hdmiphy", "mout_mpll_user_t",
0342                 "sclk_epll", "sclk_vpll", };
0343 PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
0344                 "sclk_usbphy0", "xxti", "xusbxti",
0345                 "mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
0346 PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
0347                 "sclk_usbphy0", "xxti", "xusbxti",
0348                 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
0349 PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
0350                 "sclk_usbphy0", "xxti", "xusbxti",
0351                 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
0352 PNAME(aclk_p4412)   = { "mout_mpll_user_t", "sclk_apll", };
0353 PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
0354 PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
0355 PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
0356 PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
0357                 "none", "sclk_hdmiphy", "sclk_mpll",
0358                 "sclk_epll", "sclk_vpll" };
0359 PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2",
0360                 "div_gdl", "div_gpl" };
0361 PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2",
0362                 "div_gdr", "div_gpr" };
0363 PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
0364                 "sclk_usbphy0", "none", "sclk_hdmiphy",
0365                 "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
0366                 "aclk160", "aclk133", "aclk200", "aclk100",
0367                 "sclk_mfc", "sclk_g3d", "aclk400_mcuisp",
0368                 "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
0369                 "s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0",
0370                 "rx_half_byte_clk_csis1", "div_jpeg",
0371                 "sclk_pwm_isp", "sclk_spi0_isp",
0372                 "sclk_spi1_isp", "sclk_uart_isp",
0373                 "sclk_mipihsi", "sclk_hdmi", "sclk_fimd0",
0374                 "sclk_pcm0" };
0375 PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk",
0376                 "div_dmc", "div_dphy", "fout_mpll_div_2",
0377                 "div_pwi", "none", "div_c2c", "div_c2c_aclk" };
0378 PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none",
0379                 "arm_clk_div_2", "div_corem0", "div_corem1",
0380                 "div_cores", "div_atb", "div_periph",
0381                 "div_pclk_dbg", "div_hpm" };
0382 
0383 /* fixed rate clocks generated outside the soc */
0384 static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
0385     FRATE(CLK_XXTI, "xxti", NULL, 0, 0),
0386     FRATE(CLK_XUSBXTI, "xusbxti", NULL, 0, 0),
0387 };
0388 
0389 /* fixed rate clocks generated inside the soc */
0390 static const struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initconst = {
0391     FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000),
0392     FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
0393     FRATE(0, "sclk_usbphy0", NULL, 0, 48000000),
0394 };
0395 
0396 static const struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initconst = {
0397     FRATE(0, "sclk_usbphy1", NULL, 0, 48000000),
0398 };
0399 
0400 static const struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initconst = {
0401     FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
0402     FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
0403     FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
0404     FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0),
0405 };
0406 
0407 static const struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initconst = {
0408     FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),
0409 };
0410 
0411 static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initconst = {
0412     FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),
0413     FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),
0414     FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
0415     FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0),
0416 };
0417 
0418 /* list of mux clocks supported in all exynos4 soc's */
0419 static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
0420     MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
0421             CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
0422     MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
0423     MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
0424     MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
0425     MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
0426             CLK_SET_RATE_PARENT, 0),
0427     MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
0428             CLK_SET_RATE_PARENT, 0),
0429     MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
0430     MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
0431     MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
0432     MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
0433 
0434     MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
0435     MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
0436 };
0437 
0438 /* list of mux clocks supported in exynos4210 soc */
0439 static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = {
0440     MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
0441 };
0442 
0443 static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = {
0444     MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),
0445     MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
0446             CLKOUT_CMU_LEFTBUS, 0, 5),
0447 
0448     MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1),
0449     MUX(0, "mout_clkout_rightbus", clkout_right_p4210,
0450             CLKOUT_CMU_RIGHTBUS, 0, 5),
0451 
0452     MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
0453     MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
0454     MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
0455     MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
0456     MUX(CLK_MOUT_MIXER, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
0457     MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
0458     MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
0459     MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
0460     MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
0461     MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
0462     MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
0463     MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
0464     MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
0465     MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
0466     MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
0467     MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
0468     MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
0469     MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
0470     MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
0471     MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
0472     MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
0473     MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
0474     MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
0475     MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
0476     MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
0477             CLK_SET_RATE_PARENT, 0),
0478     MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
0479     MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
0480     MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
0481     MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
0482     MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
0483     MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
0484     MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
0485     MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
0486     MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
0487     MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
0488     MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
0489     MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
0490     MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
0491     MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
0492     MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
0493     MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
0494     MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
0495     MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
0496     MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
0497     MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
0498 
0499     MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4),
0500     MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
0501 
0502     MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
0503 };
0504 
0505 /* list of mux clocks supported in exynos4x12 soc */
0506 static const struct samsung_mux_clock exynos4x12_mux_clks[] __initconst = {
0507     MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),
0508     MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),
0509     MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
0510             CLKOUT_CMU_LEFTBUS, 0, 5),
0511 
0512     MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1),
0513     MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1),
0514     MUX(0, "mout_clkout_rightbus", clkout_right_p4x12,
0515             CLKOUT_CMU_RIGHTBUS, 0, 5),
0516 
0517     MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
0518             SRC_CPU, 24, 1),
0519     MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
0520 
0521     MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
0522     MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
0523     MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
0524             SRC_TOP1, 12, 1),
0525     MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
0526             SRC_TOP1, 16, 1),
0527     MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
0528     MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp",
0529         mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1),
0530     MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
0531     MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
0532     MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
0533     MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
0534     MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
0535     MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
0536     MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
0537     MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
0538     MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
0539     MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
0540     MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
0541     MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
0542     MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
0543     MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1),
0544     MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
0545     MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
0546     MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
0547     MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
0548     MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
0549     MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
0550     MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
0551     MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
0552     MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
0553     MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
0554             CLK_SET_RATE_PARENT, 0),
0555     MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
0556     MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
0557     MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
0558     MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
0559     MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
0560     MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
0561     MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
0562     MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
0563     MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
0564     MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
0565     MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
0566     MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
0567     MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
0568     MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
0569     MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
0570     MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
0571     MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
0572     MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
0573     MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
0574     MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
0575     MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
0576     MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
0577     MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
0578     MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
0579 
0580     MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1),
0581     MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4),
0582     MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
0583     MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
0584     MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
0585     MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5),
0586 };
0587 
0588 /* list of divider clocks supported in all exynos4 soc's */
0589 static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
0590     DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
0591     DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
0592     DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
0593             CLKOUT_CMU_LEFTBUS, 8, 6),
0594 
0595     DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
0596     DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
0597     DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
0598             CLKOUT_CMU_RIGHTBUS, 8, 6),
0599 
0600     DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
0601     DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
0602     DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
0603     DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
0604     DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
0605     DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
0606     DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
0607     DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
0608     DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
0609     DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
0610 
0611     DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
0612     DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
0613     DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
0614     DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
0615     DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
0616     DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
0617     DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
0618     DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
0619     DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
0620     DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4),
0621     DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
0622     DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
0623     DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
0624     DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
0625     DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
0626     DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
0627     DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
0628     DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
0629     DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
0630     DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
0631     DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
0632     DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
0633     DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
0634     DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
0635     DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
0636     DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
0637     DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
0638     DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
0639     DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
0640     DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
0641             CLK_SET_RATE_PARENT, 0),
0642     DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
0643     DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
0644     DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
0645     DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
0646     DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
0647     DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
0648     DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
0649     DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
0650     DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
0651     DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
0652     DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
0653     DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
0654     DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
0655     DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
0656     DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
0657             CLK_SET_RATE_PARENT, 0),
0658     DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
0659             CLK_SET_RATE_PARENT, 0),
0660     DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
0661             CLK_SET_RATE_PARENT, 0),
0662     DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
0663             CLK_SET_RATE_PARENT, 0),
0664     DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
0665             CLK_SET_RATE_PARENT, 0),
0666     DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
0667 
0668     DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
0669     DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
0670     DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
0671     DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
0672     DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
0673     DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
0674     DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
0675     DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6),
0676 };
0677 
0678 /* list of divider clocks supported in exynos4210 soc */
0679 static const struct samsung_div_clock exynos4210_div_clks[] __initconst = {
0680     DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
0681     DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
0682     DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
0683     DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
0684     DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
0685     DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
0686             CLK_SET_RATE_PARENT, 0),
0687 };
0688 
0689 /* list of divider clocks supported in exynos4x12 soc */
0690 static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
0691     DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
0692     DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
0693     DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
0694     DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
0695     DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
0696     DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
0697     DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
0698     DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
0699                         DIV_TOP, 24, 3),
0700     DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
0701     DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
0702     DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
0703     DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
0704     DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
0705     DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
0706     DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
0707     DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
0708     DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
0709 };
0710 
0711 /* list of gate clocks supported in all exynos4 soc's */
0712 static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
0713     GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
0714     GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
0715     GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
0716     GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
0717         0),
0718     GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
0719     GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
0720     GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
0721     GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
0722     GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
0723     GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
0724     GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0,
0725         0),
0726     GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
0727     GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
0728     GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
0729     GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
0730     GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
0731     GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
0732     GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
0733     GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
0734     GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
0735     GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0),
0736     GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
0737     GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
0738             CLK_SET_RATE_PARENT, 0),
0739     GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
0740             CLK_SET_RATE_PARENT, 0),
0741     GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0",
0742             SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
0743     GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
0744             CLK_SET_RATE_PARENT, 0),
0745     GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
0746             CLK_SET_RATE_PARENT, 0),
0747     GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
0748     GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
0749     GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
0750     GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
0751     GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0),
0752     GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0),
0753     GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0,
0754             CLK_SET_RATE_PARENT, 0),
0755     GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4,
0756             CLK_SET_RATE_PARENT, 0),
0757     GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8,
0758             CLK_SET_RATE_PARENT, 0),
0759     GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12,
0760             CLK_SET_RATE_PARENT, 0),
0761     GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24,
0762             CLK_SET_RATE_PARENT, 0),
0763     GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28,
0764             CLK_SET_RATE_PARENT, 0),
0765     GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0,
0766             CLK_SET_RATE_PARENT, 0),
0767     GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
0768             CLK_SET_RATE_PARENT, 0),
0769     GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
0770             CLK_SET_RATE_PARENT, 0),
0771     GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
0772             CLK_SET_RATE_PARENT, 0),
0773     GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
0774             CLK_SET_RATE_PARENT, 0),
0775     GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
0776             CLK_SET_RATE_PARENT, 0),
0777     GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
0778             CLK_SET_RATE_PARENT, 0),
0779     GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
0780             CLK_SET_RATE_PARENT, 0),
0781     GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
0782             CLK_SET_RATE_PARENT, 0),
0783     GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12,
0784             CLK_SET_RATE_PARENT, 0),
0785     GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16,
0786             CLK_SET_RATE_PARENT, 0),
0787     GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
0788             CLK_SET_RATE_PARENT, 0),
0789     GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,
0790             CLK_SET_RATE_PARENT, 0),
0791     GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20,
0792             CLK_SET_RATE_PARENT, 0),
0793     GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24,
0794             CLK_SET_RATE_PARENT, 0),
0795     GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0,
0796             0, 0),
0797     GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1,
0798             0, 0),
0799     GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2,
0800             0, 0),
0801     GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3,
0802             0, 0),
0803     GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4,
0804             0, 0),
0805     GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5,
0806             0, 0),
0807     GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7,
0808             0, 0),
0809     GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8,
0810             0, 0),
0811     GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9,
0812             0, 0),
0813     GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10,
0814             0, 0),
0815     GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
0816             0, 0),
0817     GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0),
0818     GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
0819     GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
0820     GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
0821             0, 0),
0822     GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0),
0823     GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
0824     GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
0825             0, 0),
0826     GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
0827             0, 0),
0828     GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0),
0829     GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0),
0830     GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
0831             0, 0),
0832     GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
0833             0, 0),
0834     GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0),
0835     GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
0836             0, 0),
0837     GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
0838             0, 0),
0839     GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
0840             0, 0),
0841     GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6,
0842             0, 0),
0843     GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7,
0844             0, 0),
0845     GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
0846             0, 0),
0847     GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0),
0848     GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
0849             0, 0),
0850     GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
0851             0, 0),
0852     GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
0853             0, 0),
0854     GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3,
0855             0, 0),
0856     GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4,
0857             0, 0),
0858     GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6,
0859             0, 0),
0860     GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7,
0861             0, 0),
0862     GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8,
0863             0, 0),
0864     GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9,
0865             0, 0),
0866     GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10,
0867             0, 0),
0868     GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11,
0869             0, 0),
0870     GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12,
0871             0, 0),
0872     GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13,
0873             0, 0),
0874     GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
0875             0, 0),
0876     GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16,
0877             0, 0),
0878     GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17,
0879             0, 0),
0880     GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18,
0881             0, 0),
0882     GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20,
0883             0, 0),
0884     GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21,
0885             0, 0),
0886     GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22,
0887             0, 0),
0888     GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23,
0889             0, 0),
0890     GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26,
0891             0, 0),
0892     GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
0893             0, 0),
0894     GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0),
0895     GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
0896     GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
0897     GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),
0898     GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0),
0899 
0900     GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus",
0901             CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0),
0902     GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus",
0903             CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0),
0904     GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top",
0905             CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0),
0906     GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc",
0907             CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0),
0908     GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu",
0909             CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0),
0910 };
0911 
0912 /* list of gate clocks supported in exynos4210 soc */
0913 static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = {
0914     GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
0915     GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
0916     GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
0917     GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
0918     GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
0919     GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
0920         0),
0921     GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0,
0922         0),
0923     GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
0924     GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
0925     GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
0926     GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
0927     GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
0928     GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
0929     GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
0930     GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
0931     GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
0932             CLK_IGNORE_UNUSED, 0),
0933     GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0,
0934         0),
0935     GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
0936             E4210_GATE_IP_IMAGE, 4, 0, 0),
0937     GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1",
0938             E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
0939     GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
0940             SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
0941     GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
0942     GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
0943     GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15,
0944             0, 0),
0945     GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
0946             0, 0),
0947     GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14,
0948             0, 0),
0949     GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15,
0950             0, 0),
0951     GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16,
0952             0, 0),
0953     GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,
0954             CLK_SET_RATE_PARENT, 0),
0955     GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0,
0956         0),
0957 };
0958 
0959 /* list of gate clocks supported in exynos4x12 soc */
0960 static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
0961     GATE(CLK_ASYNC_G3D, "async_g3d", "aclk200", GATE_IP_LEFTBUS, 6, 0, 0),
0962     GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
0963     GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
0964     GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
0965     GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
0966     GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
0967         0),
0968     GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
0969         0),
0970     GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0),
0971     GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
0972     GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0),
0973     GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
0974             CLK_IGNORE_UNUSED, 0),
0975     GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0,
0976         0),
0977     GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0",
0978             SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
0979     GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
0980             SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
0981     GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi",
0982             SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
0983     GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
0984             E4X12_GATE_IP_IMAGE, 4, 0, 0),
0985     GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
0986             0, 0),
0987     GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,
0988             0, 0),
0989     GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
0990     GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp",
0991             E4X12_GATE_IP_ISP, 0, 0, 0),
0992     GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre",
0993             E4X12_GATE_IP_ISP, 1, 0, 0),
0994     GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre",
0995             E4X12_GATE_IP_ISP, 2, 0, 0),
0996     GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp",
0997             E4X12_GATE_IP_ISP, 3, 0, 0),
0998     GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
0999     GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,
1000             0, 0),
1001     GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
1002             0, 0),
1003     GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
1004     GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
1005     GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
1006         0),
1007 };
1008 
1009 /*
1010  * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
1011  * resides in chipid register space, outside of the clock controller memory
1012  * mapped space. So to determine the parent of fin_pll clock, the chipid
1013  * controller is first remapped and the value of XOM[0] bit is read to
1014  * determine the parent clock.
1015  */
1016 static unsigned long __init exynos4_get_xom(void)
1017 {
1018     unsigned long xom = 0;
1019     void __iomem *chipid_base;
1020     struct device_node *np;
1021 
1022     np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
1023     if (np) {
1024         chipid_base = of_iomap(np, 0);
1025 
1026         if (chipid_base)
1027             xom = readl(chipid_base + 8);
1028 
1029         iounmap(chipid_base);
1030         of_node_put(np);
1031     }
1032 
1033     return xom;
1034 }
1035 
1036 static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
1037 {
1038     struct samsung_fixed_rate_clock fclk;
1039     struct clk *clk;
1040     unsigned long finpll_f = 24000000;
1041     char *parent_name;
1042     unsigned int xom = exynos4_get_xom();
1043 
1044     parent_name = xom & 1 ? "xusbxti" : "xxti";
1045     clk = clk_get(NULL, parent_name);
1046     if (IS_ERR(clk)) {
1047         pr_err("%s: failed to lookup parent clock %s, assuming "
1048             "fin_pll clock frequency is 24MHz\n", __func__,
1049             parent_name);
1050     } else {
1051         finpll_f = clk_get_rate(clk);
1052     }
1053 
1054     fclk.id = CLK_FIN_PLL;
1055     fclk.name = "fin_pll";
1056     fclk.parent_name = NULL;
1057     fclk.flags = 0;
1058     fclk.fixed_rate = finpll_f;
1059     samsung_clk_register_fixed_rate(ctx, &fclk, 1);
1060 
1061 }
1062 
1063 static const struct of_device_id ext_clk_match[] __initconst = {
1064     { .compatible = "samsung,clock-xxti", .data = (void *)0, },
1065     { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
1066     {},
1067 };
1068 
1069 /* PLLs PMS values */
1070 static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = {
1071     PLL_4508_RATE(24 * MHZ, 1200000000, 150,  3, 1, 28),
1072     PLL_4508_RATE(24 * MHZ, 1000000000, 250,  6, 1, 28),
1073     PLL_4508_RATE(24 * MHZ,  800000000, 200,  6, 1, 28),
1074     PLL_4508_RATE(24 * MHZ,  666857142, 389, 14, 1, 13),
1075     PLL_4508_RATE(24 * MHZ,  600000000, 100,  4, 1, 13),
1076     PLL_4508_RATE(24 * MHZ,  533000000, 533, 24, 1,  5),
1077     PLL_4508_RATE(24 * MHZ,  500000000, 250,  6, 2, 28),
1078     PLL_4508_RATE(24 * MHZ,  400000000, 200,  6, 2, 28),
1079     PLL_4508_RATE(24 * MHZ,  200000000, 200,  6, 3, 28),
1080     { /* sentinel */ }
1081 };
1082 
1083 static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = {
1084     PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1,     0, 0),
1085     PLL_4600_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381, 0),
1086     PLL_4600_RATE(24 * MHZ, 180000000, 45, 3, 1,     0, 0),
1087     PLL_4600_RATE(24 * MHZ,  73727996, 73, 3, 3, 47710, 1),
1088     PLL_4600_RATE(24 * MHZ,  67737602, 90, 4, 3, 20762, 1),
1089     PLL_4600_RATE(24 * MHZ,  49151992, 49, 3, 3,  9961, 0),
1090     PLL_4600_RATE(24 * MHZ,  45158401, 45, 3, 3, 10381, 0),
1091     { /* sentinel */ }
1092 };
1093 
1094 static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = {
1095     PLL_4650_RATE(24 * MHZ, 360000000, 44, 3, 0, 1024, 0, 14, 0),
1096     PLL_4650_RATE(24 * MHZ, 324000000, 53, 2, 1, 1024, 1,  1, 1),
1097     PLL_4650_RATE(24 * MHZ, 259617187, 63, 3, 1, 1950, 0, 20, 1),
1098     PLL_4650_RATE(24 * MHZ, 110000000, 53, 3, 2, 2048, 0, 17, 0),
1099     PLL_4650_RATE(24 * MHZ,  55360351, 53, 3, 3, 2417, 0, 17, 0),
1100     { /* sentinel */ }
1101 };
1102 
1103 static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {
1104     PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0),
1105     PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1106     PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1107     PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1108     PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1109     PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
1110     PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
1111     PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
1112     PLL_35XX_RATE(24 * MHZ,  900000000, 150, 4, 0),
1113     PLL_35XX_RATE(24 * MHZ,  800000000, 100, 3, 0),
1114     PLL_35XX_RATE(24 * MHZ,  700000000, 175, 3, 1),
1115     PLL_35XX_RATE(24 * MHZ,  600000000, 200, 4, 1),
1116     PLL_35XX_RATE(24 * MHZ,  500000000, 125, 3, 1),
1117     PLL_35XX_RATE(24 * MHZ,  400000000, 100, 3, 1),
1118     PLL_35XX_RATE(24 * MHZ,  300000000, 200, 4, 2),
1119     PLL_35XX_RATE(24 * MHZ,  200000000, 100, 3, 2),
1120     { /* sentinel */ }
1121 };
1122 
1123 static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = {
1124     PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690),
1125     PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1,     0),
1126     PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381),
1127     PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1,     0),
1128     PLL_36XX_RATE(24 * MHZ,  73727996, 73, 3, 3, 47710),
1129     PLL_36XX_RATE(24 * MHZ,  67737602, 90, 4, 3, 20762),
1130     PLL_36XX_RATE(24 * MHZ,  49151992, 49, 3, 3,  9961),
1131     PLL_36XX_RATE(24 * MHZ,  45158401, 45, 3, 3, 10381),
1132     { /* sentinel */ }
1133 };
1134 
1135 static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = {
1136     PLL_36XX_RATE(24 * MHZ, 533000000, 133, 3, 1, 16384),
1137     PLL_36XX_RATE(24 * MHZ, 440000000, 110, 3, 1,     0),
1138     PLL_36XX_RATE(24 * MHZ, 350000000, 175, 3, 2,     0),
1139     PLL_36XX_RATE(24 * MHZ, 266000000, 133, 3, 2,     0),
1140     PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3,     0),
1141     PLL_36XX_RATE(24 * MHZ, 106031250,  53, 3, 2,  1024),
1142     PLL_36XX_RATE(24 * MHZ,  53015625,  53, 3, 3,  1024),
1143     { /* sentinel */ }
1144 };
1145 
1146 static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
1147     [apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1148         APLL_LOCK, APLL_CON0, NULL),
1149     [mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1150         E4210_MPLL_LOCK, E4210_MPLL_CON0, NULL),
1151     [epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1152         EPLL_LOCK, EPLL_CON0, NULL),
1153     [vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
1154         VPLL_LOCK, VPLL_CON0, NULL),
1155 };
1156 
1157 static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
1158     [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1159             APLL_LOCK, APLL_CON0, NULL),
1160     [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1161             E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL),
1162     [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1163             EPLL_LOCK, EPLL_CON0, NULL),
1164     [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
1165             VPLL_LOCK, VPLL_CON0, NULL),
1166 };
1167 
1168 static void __init exynos4x12_core_down_clock(void)
1169 {
1170     unsigned int tmp;
1171 
1172     /*
1173      * Enable arm clock down (in idle) and set arm divider
1174      * ratios in WFI/WFE state.
1175      */
1176     tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
1177         PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
1178         PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
1179         PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
1180     /* On Exynos4412 enable it also on core 2 and 3 */
1181     if (num_possible_cpus() == 4)
1182         tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
1183                PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
1184     writel_relaxed(tmp, reg_base + PWR_CTRL1);
1185 
1186     /*
1187      * Disable the clock up feature in case it was enabled by bootloader.
1188      */
1189     writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2);
1190 }
1191 
1192 #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \
1193         (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) |  \
1194         ((periph) << 12) | ((corem1) << 8) | ((corem0) <<  4))
1195 #define E4210_CPU_DIV1(hpm, copy)                   \
1196         (((hpm) << 4) | ((copy) << 0))
1197 
1198 static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
1199     { 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
1200     { 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
1201     {  800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
1202     {  500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
1203     {  400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
1204     {  200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
1205     {  0 },
1206 };
1207 
1208 #define E4412_CPU_DIV1(cores, hpm, copy)                \
1209         (((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
1210 
1211 static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
1212     { 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), },
1213     { 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
1214     { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
1215     { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },
1216     { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
1217     { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },
1218     { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },
1219     { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },
1220     {  900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },
1221     {  800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },
1222     {  700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },
1223     {  600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
1224     {  500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
1225     {  400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
1226     {  300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
1227     {  200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },
1228     {  0 },
1229 };
1230 
1231 static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = {
1232     CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_SCLK_MPLL,
1233             CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4210_armclk_d),
1234 };
1235 
1236 static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {
1237     CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
1238             CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4412_armclk_d),
1239 };
1240 
1241 /* register exynos4 clocks */
1242 static void __init exynos4_clk_init(struct device_node *np,
1243                     enum exynos4_soc soc)
1244 {
1245     struct samsung_clk_provider *ctx;
1246     struct clk_hw **hws;
1247 
1248     exynos4_soc = soc;
1249 
1250     reg_base = of_iomap(np, 0);
1251     if (!reg_base)
1252         panic("%s: failed to map registers\n", __func__);
1253 
1254     ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1255     hws = ctx->clk_data.hws;
1256 
1257     samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
1258             ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
1259             ext_clk_match);
1260 
1261     exynos4_clk_register_finpll(ctx);
1262 
1263     if (exynos4_soc == EXYNOS4210) {
1264         samsung_clk_register_mux(ctx, exynos4210_mux_early,
1265                     ARRAY_SIZE(exynos4210_mux_early));
1266 
1267         if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
1268             exynos4210_plls[apll].rate_table =
1269                             exynos4210_apll_rates;
1270             exynos4210_plls[epll].rate_table =
1271                             exynos4210_epll_rates;
1272         }
1273 
1274         if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24000000)
1275             exynos4210_plls[vpll].rate_table =
1276                             exynos4210_vpll_rates;
1277 
1278         samsung_clk_register_pll(ctx, exynos4210_plls,
1279                     ARRAY_SIZE(exynos4210_plls), reg_base);
1280     } else {
1281         if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
1282             exynos4x12_plls[apll].rate_table =
1283                             exynos4x12_apll_rates;
1284             exynos4x12_plls[epll].rate_table =
1285                             exynos4x12_epll_rates;
1286             exynos4x12_plls[vpll].rate_table =
1287                             exynos4x12_vpll_rates;
1288         }
1289 
1290         samsung_clk_register_pll(ctx, exynos4x12_plls,
1291                     ARRAY_SIZE(exynos4x12_plls), reg_base);
1292     }
1293 
1294     samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
1295             ARRAY_SIZE(exynos4_fixed_rate_clks));
1296     samsung_clk_register_mux(ctx, exynos4_mux_clks,
1297             ARRAY_SIZE(exynos4_mux_clks));
1298     samsung_clk_register_div(ctx, exynos4_div_clks,
1299             ARRAY_SIZE(exynos4_div_clks));
1300     samsung_clk_register_gate(ctx, exynos4_gate_clks,
1301             ARRAY_SIZE(exynos4_gate_clks));
1302     samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
1303             ARRAY_SIZE(exynos4_fixed_factor_clks));
1304 
1305     if (exynos4_soc == EXYNOS4210) {
1306         samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
1307             ARRAY_SIZE(exynos4210_fixed_rate_clks));
1308         samsung_clk_register_mux(ctx, exynos4210_mux_clks,
1309             ARRAY_SIZE(exynos4210_mux_clks));
1310         samsung_clk_register_div(ctx, exynos4210_div_clks,
1311             ARRAY_SIZE(exynos4210_div_clks));
1312         samsung_clk_register_gate(ctx, exynos4210_gate_clks,
1313             ARRAY_SIZE(exynos4210_gate_clks));
1314         samsung_clk_register_fixed_factor(ctx,
1315             exynos4210_fixed_factor_clks,
1316             ARRAY_SIZE(exynos4210_fixed_factor_clks));
1317         samsung_clk_register_cpu(ctx, exynos4210_cpu_clks,
1318                 ARRAY_SIZE(exynos4210_cpu_clks));
1319     } else {
1320         samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
1321             ARRAY_SIZE(exynos4x12_mux_clks));
1322         samsung_clk_register_div(ctx, exynos4x12_div_clks,
1323             ARRAY_SIZE(exynos4x12_div_clks));
1324         samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
1325             ARRAY_SIZE(exynos4x12_gate_clks));
1326         samsung_clk_register_fixed_factor(ctx,
1327             exynos4x12_fixed_factor_clks,
1328             ARRAY_SIZE(exynos4x12_fixed_factor_clks));
1329         samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,
1330                 ARRAY_SIZE(exynos4412_cpu_clks));
1331     }
1332 
1333     if (soc == EXYNOS4X12)
1334         exynos4x12_core_down_clock();
1335 
1336     samsung_clk_extended_sleep_init(reg_base,
1337             exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1338             src_mask_suspend, ARRAY_SIZE(src_mask_suspend));
1339     if (exynos4_soc == EXYNOS4210)
1340         samsung_clk_extended_sleep_init(reg_base,
1341             exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save),
1342             src_mask_suspend_e4210, ARRAY_SIZE(src_mask_suspend_e4210));
1343     else
1344         samsung_clk_sleep_init(reg_base, exynos4x12_clk_save,
1345                        ARRAY_SIZE(exynos4x12_clk_save));
1346 
1347     samsung_clk_of_add_provider(np, ctx);
1348 
1349     pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
1350         "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
1351         exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
1352         clk_hw_get_rate(hws[CLK_SCLK_APLL]),
1353         clk_hw_get_rate(hws[CLK_SCLK_MPLL]),
1354         clk_hw_get_rate(hws[CLK_SCLK_EPLL]),
1355         clk_hw_get_rate(hws[CLK_SCLK_VPLL]),
1356         clk_hw_get_rate(hws[CLK_DIV_CORE2]));
1357 }
1358 
1359 
1360 static void __init exynos4210_clk_init(struct device_node *np)
1361 {
1362     exynos4_clk_init(np, EXYNOS4210);
1363 }
1364 CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
1365 
1366 static void __init exynos4412_clk_init(struct device_node *np)
1367 {
1368     exynos4_clk_init(np, EXYNOS4X12);
1369 }
1370 CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);
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