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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
0004  *
0005  * Common Clock Framework support for Exynos3250 SoC.
0006  */
0007 
0008 #include <linux/clk-provider.h>
0009 #include <linux/io.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/platform_device.h>
0013 
0014 #include <dt-bindings/clock/exynos3250.h>
0015 
0016 #include "clk.h"
0017 #include "clk-cpu.h"
0018 #include "clk-pll.h"
0019 
0020 #define SRC_LEFTBUS     0x4200
0021 #define DIV_LEFTBUS     0x4500
0022 #define GATE_IP_LEFTBUS     0x4800
0023 #define SRC_RIGHTBUS        0x8200
0024 #define DIV_RIGHTBUS        0x8500
0025 #define GATE_IP_RIGHTBUS    0x8800
0026 #define GATE_IP_PERIR       0x8960
0027 #define MPLL_LOCK       0xc010
0028 #define MPLL_CON0       0xc110
0029 #define VPLL_LOCK       0xc020
0030 #define VPLL_CON0       0xc120
0031 #define UPLL_LOCK       0xc030
0032 #define UPLL_CON0       0xc130
0033 #define SRC_TOP0        0xc210
0034 #define SRC_TOP1        0xc214
0035 #define SRC_CAM         0xc220
0036 #define SRC_MFC         0xc228
0037 #define SRC_G3D         0xc22c
0038 #define SRC_LCD         0xc234
0039 #define SRC_ISP         0xc238
0040 #define SRC_FSYS        0xc240
0041 #define SRC_PERIL0      0xc250
0042 #define SRC_PERIL1      0xc254
0043 #define SRC_MASK_TOP        0xc310
0044 #define SRC_MASK_CAM        0xc320
0045 #define SRC_MASK_LCD        0xc334
0046 #define SRC_MASK_ISP        0xc338
0047 #define SRC_MASK_FSYS       0xc340
0048 #define SRC_MASK_PERIL0     0xc350
0049 #define SRC_MASK_PERIL1     0xc354
0050 #define DIV_TOP         0xc510
0051 #define DIV_CAM         0xc520
0052 #define DIV_MFC         0xc528
0053 #define DIV_G3D         0xc52c
0054 #define DIV_LCD         0xc534
0055 #define DIV_ISP         0xc538
0056 #define DIV_FSYS0       0xc540
0057 #define DIV_FSYS1       0xc544
0058 #define DIV_FSYS2       0xc548
0059 #define DIV_PERIL0      0xc550
0060 #define DIV_PERIL1      0xc554
0061 #define DIV_PERIL3      0xc55c
0062 #define DIV_PERIL4      0xc560
0063 #define DIV_PERIL5      0xc564
0064 #define DIV_CAM1        0xc568
0065 #define CLKDIV2_RATIO       0xc580
0066 #define GATE_SCLK_CAM       0xc820
0067 #define GATE_SCLK_MFC       0xc828
0068 #define GATE_SCLK_G3D       0xc82c
0069 #define GATE_SCLK_LCD       0xc834
0070 #define GATE_SCLK_ISP_TOP   0xc838
0071 #define GATE_SCLK_FSYS      0xc840
0072 #define GATE_SCLK_PERIL     0xc850
0073 #define GATE_IP_CAM     0xc920
0074 #define GATE_IP_MFC     0xc928
0075 #define GATE_IP_G3D     0xc92c
0076 #define GATE_IP_LCD     0xc934
0077 #define GATE_IP_ISP     0xc938
0078 #define GATE_IP_FSYS        0xc940
0079 #define GATE_IP_PERIL       0xc950
0080 #define GATE_BLOCK      0xc970
0081 #define APLL_LOCK       0x14000
0082 #define APLL_CON0       0x14100
0083 #define SRC_CPU         0x14200
0084 #define DIV_CPU0        0x14500
0085 #define DIV_CPU1        0x14504
0086 #define PWR_CTRL1       0x15020
0087 #define PWR_CTRL2       0x15024
0088 
0089 /* Below definitions are used for PWR_CTRL settings */
0090 #define PWR_CTRL1_CORE2_DOWN_RATIO(x)       (((x) & 0x7) << 28)
0091 #define PWR_CTRL1_CORE1_DOWN_RATIO(x)       (((x) & 0x7) << 16)
0092 #define PWR_CTRL1_DIV2_DOWN_EN          (1 << 9)
0093 #define PWR_CTRL1_DIV1_DOWN_EN          (1 << 8)
0094 #define PWR_CTRL1_USE_CORE3_WFE         (1 << 7)
0095 #define PWR_CTRL1_USE_CORE2_WFE         (1 << 6)
0096 #define PWR_CTRL1_USE_CORE1_WFE         (1 << 5)
0097 #define PWR_CTRL1_USE_CORE0_WFE         (1 << 4)
0098 #define PWR_CTRL1_USE_CORE3_WFI         (1 << 3)
0099 #define PWR_CTRL1_USE_CORE2_WFI         (1 << 2)
0100 #define PWR_CTRL1_USE_CORE1_WFI         (1 << 1)
0101 #define PWR_CTRL1_USE_CORE0_WFI         (1 << 0)
0102 
0103 static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {
0104     SRC_LEFTBUS,
0105     DIV_LEFTBUS,
0106     GATE_IP_LEFTBUS,
0107     SRC_RIGHTBUS,
0108     DIV_RIGHTBUS,
0109     GATE_IP_RIGHTBUS,
0110     GATE_IP_PERIR,
0111     MPLL_LOCK,
0112     MPLL_CON0,
0113     VPLL_LOCK,
0114     VPLL_CON0,
0115     UPLL_LOCK,
0116     UPLL_CON0,
0117     SRC_TOP0,
0118     SRC_TOP1,
0119     SRC_CAM,
0120     SRC_MFC,
0121     SRC_G3D,
0122     SRC_LCD,
0123     SRC_ISP,
0124     SRC_FSYS,
0125     SRC_PERIL0,
0126     SRC_PERIL1,
0127     SRC_MASK_TOP,
0128     SRC_MASK_CAM,
0129     SRC_MASK_LCD,
0130     SRC_MASK_ISP,
0131     SRC_MASK_FSYS,
0132     SRC_MASK_PERIL0,
0133     SRC_MASK_PERIL1,
0134     DIV_TOP,
0135     DIV_CAM,
0136     DIV_MFC,
0137     DIV_G3D,
0138     DIV_LCD,
0139     DIV_ISP,
0140     DIV_FSYS0,
0141     DIV_FSYS1,
0142     DIV_FSYS2,
0143     DIV_PERIL0,
0144     DIV_PERIL1,
0145     DIV_PERIL3,
0146     DIV_PERIL4,
0147     DIV_PERIL5,
0148     DIV_CAM1,
0149     CLKDIV2_RATIO,
0150     GATE_SCLK_CAM,
0151     GATE_SCLK_MFC,
0152     GATE_SCLK_G3D,
0153     GATE_SCLK_LCD,
0154     GATE_SCLK_ISP_TOP,
0155     GATE_SCLK_FSYS,
0156     GATE_SCLK_PERIL,
0157     GATE_IP_CAM,
0158     GATE_IP_MFC,
0159     GATE_IP_G3D,
0160     GATE_IP_LCD,
0161     GATE_IP_ISP,
0162     GATE_IP_FSYS,
0163     GATE_IP_PERIL,
0164     GATE_BLOCK,
0165     APLL_LOCK,
0166     SRC_CPU,
0167     DIV_CPU0,
0168     DIV_CPU1,
0169     PWR_CTRL1,
0170     PWR_CTRL2,
0171 };
0172 
0173 /* list of all parent clock list */
0174 PNAME(mout_vpllsrc_p)       = { "fin_pll", };
0175 
0176 PNAME(mout_apll_p)      = { "fin_pll", "fout_apll", };
0177 PNAME(mout_mpll_p)      = { "fin_pll", "fout_mpll", };
0178 PNAME(mout_vpll_p)      = { "fin_pll", "fout_vpll", };
0179 PNAME(mout_upll_p)      = { "fin_pll", "fout_upll", };
0180 
0181 PNAME(mout_mpll_user_p)     = { "fin_pll", "div_mpll_pre", };
0182 PNAME(mout_epll_user_p)     = { "fin_pll", "mout_epll", };
0183 PNAME(mout_core_p)      = { "mout_apll", "mout_mpll_user_c", };
0184 PNAME(mout_hpm_p)       = { "mout_apll", "mout_mpll_user_c", };
0185 
0186 PNAME(mout_ebi_p)       = { "div_aclk_200", "div_aclk_160", };
0187 PNAME(mout_ebi_1_p)     = { "mout_ebi", "mout_vpll", };
0188 
0189 PNAME(mout_gdl_p)       = { "mout_mpll_user_l", };
0190 PNAME(mout_gdr_p)       = { "mout_mpll_user_r", };
0191 
0192 PNAME(mout_aclk_400_mcuisp_sub_p)
0193                 = { "fin_pll", "div_aclk_400_mcuisp", };
0194 PNAME(mout_aclk_266_0_p)    = { "div_mpll_pre", "mout_vpll", };
0195 PNAME(mout_aclk_266_1_p)    = { "mout_epll_user", };
0196 PNAME(mout_aclk_266_p)      = { "mout_aclk_266_0", "mout_aclk_266_1", };
0197 PNAME(mout_aclk_266_sub_p)  = { "fin_pll", "div_aclk_266", };
0198 
0199 PNAME(group_div_mpll_pre_p) = { "div_mpll_pre", };
0200 PNAME(group_epll_vpll_p)    = { "mout_epll_user", "mout_vpll" };
0201 PNAME(group_sclk_p)     = { "xxti", "xusbxti",
0202                     "none", "none",
0203                     "none", "none", "div_mpll_pre",
0204                     "mout_epll_user", "mout_vpll", };
0205 PNAME(group_sclk_audio_p)   = { "audiocdclk", "none",
0206                     "none", "none",
0207                     "xxti", "xusbxti",
0208                     "div_mpll_pre", "mout_epll_user",
0209                     "mout_vpll", };
0210 PNAME(group_sclk_cam_blk_p) = { "xxti", "xusbxti",
0211                     "none", "none", "none",
0212                     "none", "div_mpll_pre",
0213                     "mout_epll_user", "mout_vpll",
0214                     "none", "none", "none",
0215                     "div_cam_blk_320", };
0216 PNAME(group_sclk_fimd0_p)   = { "xxti", "xusbxti",
0217                     "m_bitclkhsdiv4_2l", "none",
0218                     "none", "none", "div_mpll_pre",
0219                     "mout_epll_user", "mout_vpll",
0220                     "none", "none", "none",
0221                     "div_lcd_blk_145", };
0222 
0223 PNAME(mout_mfc_p)       = { "mout_mfc_0", "mout_mfc_1" };
0224 PNAME(mout_g3d_p)       = { "mout_g3d_0", "mout_g3d_1" };
0225 
0226 static const struct samsung_fixed_factor_clock fixed_factor_clks[] __initconst = {
0227     FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
0228     FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
0229     FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
0230     FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
0231     FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),
0232 
0233     /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
0234     FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
0235 };
0236 
0237 static const struct samsung_mux_clock mux_clks[] __initconst = {
0238     /*
0239      * NOTE: Following table is sorted by register address in ascending
0240      * order and then bitfield shift in descending order, as it is done
0241      * in the User's Manual. When adding new entries, please make sure
0242      * that the order is preserved, to avoid merge conflicts and make
0243      * further work with defined data easier.
0244      */
0245 
0246     /* SRC_LEFTBUS */
0247     MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
0248         SRC_LEFTBUS, 4, 1),
0249     MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
0250 
0251     /* SRC_RIGHTBUS */
0252     MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
0253         SRC_RIGHTBUS, 4, 1),
0254     MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
0255 
0256     /* SRC_TOP0 */
0257     MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
0258     MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
0259     MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
0260     MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
0261     MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
0262     MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
0263     MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),
0264     MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
0265     MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
0266     MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
0267 
0268     /* SRC_TOP1 */
0269     MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
0270     MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p,
0271         SRC_TOP1, 24, 1),
0272     MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),
0273     MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
0274     MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
0275     MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
0276 
0277     /* SRC_CAM */
0278     MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
0279     MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),
0280 
0281     /* SRC_MFC */
0282     MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
0283     MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
0284     MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),
0285 
0286     /* SRC_G3D */
0287     MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
0288     MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
0289     MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),
0290 
0291     /* SRC_LCD */
0292     MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),
0293     MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
0294 
0295     /* SRC_ISP */
0296     MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4),
0297     MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),
0298     MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4),
0299 
0300     /* SRC_FSYS */
0301     MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
0302     MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
0303     MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
0304     MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
0305 
0306     /* SRC_PERIL0 */
0307     MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
0308     MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
0309     MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
0310 
0311     /* SRC_PERIL1 */
0312     MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
0313     MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
0314     MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4),
0315 
0316     /* SRC_CPU */
0317     MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
0318         SRC_CPU, 24, 1),
0319     MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
0320     MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1,
0321             CLK_SET_RATE_PARENT, 0),
0322     MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
0323             CLK_SET_RATE_PARENT, 0),
0324 };
0325 
0326 static const struct samsung_div_clock div_clks[] __initconst = {
0327     /*
0328      * NOTE: Following table is sorted by register address in ascending
0329      * order and then bitfield shift in descending order, as it is done
0330      * in the User's Manual. When adding new entries, please make sure
0331      * that the order is preserved, to avoid merge conflicts and make
0332      * further work with defined data easier.
0333      */
0334 
0335     /* DIV_LEFTBUS */
0336     DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
0337     DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
0338 
0339     /* DIV_RIGHTBUS */
0340     DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
0341     DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
0342 
0343     /* DIV_TOP */
0344     DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
0345     DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
0346         "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
0347     DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
0348     DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
0349     DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
0350     DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
0351     DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
0352 
0353     /* DIV_CAM */
0354     DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
0355     DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4),
0356 
0357     /* DIV_MFC */
0358     DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
0359 
0360     /* DIV_G3D */
0361     DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
0362 
0363     /* DIV_LCD */
0364     DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
0365         CLK_SET_RATE_PARENT, 0),
0366     DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
0367     DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
0368 
0369     /* DIV_ISP */
0370     DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
0371     DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
0372         DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
0373     DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
0374     DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
0375         DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
0376     DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
0377 
0378     /* DIV_FSYS0 */
0379     DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
0380         CLK_SET_RATE_PARENT, 0),
0381     DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
0382 
0383     /* DIV_FSYS1 */
0384     DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
0385         CLK_SET_RATE_PARENT, 0),
0386     DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
0387     DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
0388         CLK_SET_RATE_PARENT, 0),
0389     DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
0390 
0391     /* DIV_FSYS2 */
0392     DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
0393         CLK_SET_RATE_PARENT, 0),
0394     DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
0395 
0396     /* DIV_PERIL0 */
0397     DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
0398     DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
0399     DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
0400 
0401     /* DIV_PERIL1 */
0402     DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
0403         CLK_SET_RATE_PARENT, 0),
0404     DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
0405     DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
0406         CLK_SET_RATE_PARENT, 0),
0407     DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
0408 
0409     /* DIV_PERIL4 */
0410     DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8),
0411     DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4),
0412 
0413     /* DIV_PERIL5 */
0414     DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6),
0415 
0416     /* DIV_CPU0 */
0417     DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
0418     DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
0419     DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
0420     DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
0421     DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
0422     DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
0423 
0424     /* DIV_CPU1 */
0425     DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
0426     DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
0427 };
0428 
0429 static const struct samsung_gate_clock gate_clks[] __initconst = {
0430     /*
0431      * NOTE: Following table is sorted by register address in ascending
0432      * order and then bitfield shift in descending order, as it is done
0433      * in the User's Manual. When adding new entries, please make sure
0434      * that the order is preserved, to avoid merge conflicts and make
0435      * further work with defined data easier.
0436      */
0437 
0438     /* GATE_IP_LEFTBUS */
0439     GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
0440         CLK_IGNORE_UNUSED, 0),
0441     GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
0442         CLK_IGNORE_UNUSED, 0),
0443     GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
0444         CLK_IGNORE_UNUSED, 0),
0445     GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
0446         CLK_IGNORE_UNUSED, 0),
0447 
0448     /* GATE_IP_RIGHTBUS */
0449     GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
0450         GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
0451     GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
0452         GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
0453     GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
0454         GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
0455     GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
0456         CLK_IGNORE_UNUSED, 0),
0457     GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
0458         CLK_IGNORE_UNUSED, 0),
0459     GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
0460         CLK_IGNORE_UNUSED, 0),
0461 
0462     /* GATE_IP_PERIR */
0463     GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
0464         CLK_IGNORE_UNUSED, 0),
0465     GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
0466         CLK_IGNORE_UNUSED, 0),
0467     GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
0468         GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
0469     GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
0470         GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
0471     GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
0472         CLK_IGNORE_UNUSED, 0),
0473     GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
0474         GATE_IP_PERIR, 17, 0, 0),
0475     GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
0476     GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
0477     GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
0478     GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
0479     GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
0480         CLK_IGNORE_UNUSED, 0),
0481     GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
0482         CLK_IGNORE_UNUSED, 0),
0483     GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
0484         CLK_IGNORE_UNUSED, 0),
0485     GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
0486         CLK_IGNORE_UNUSED, 0),
0487     GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
0488         CLK_IGNORE_UNUSED, 0),
0489     GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
0490         CLK_IGNORE_UNUSED, 0),
0491     GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
0492         CLK_IGNORE_UNUSED, 0),
0493     GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
0494         CLK_IGNORE_UNUSED, 0),
0495     GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
0496         CLK_IGNORE_UNUSED, 0),
0497     GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
0498         CLK_IGNORE_UNUSED, 0),
0499     GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
0500         CLK_IGNORE_UNUSED, 0),
0501     GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
0502         CLK_IGNORE_UNUSED, 0),
0503 
0504     /* GATE_SCLK_CAM */
0505     GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
0506         GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
0507     GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
0508         GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
0509     GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
0510         GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
0511     GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
0512         GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
0513 
0514     /* GATE_SCLK_MFC */
0515     GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
0516         GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
0517 
0518     /* GATE_SCLK_G3D */
0519     GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
0520         GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
0521 
0522     /* GATE_SCLK_LCD */
0523     GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
0524         GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
0525     GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
0526         GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
0527     GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
0528         GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
0529 
0530     /* GATE_SCLK_ISP_TOP */
0531     GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
0532         GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
0533     GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
0534         GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
0535     GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
0536         GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
0537     GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
0538         GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
0539 
0540     /* GATE_SCLK_FSYS */
0541     GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
0542     GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
0543         GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
0544     GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
0545         GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
0546     GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
0547         GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
0548     GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
0549         GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
0550     GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
0551         GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
0552 
0553     /* GATE_SCLK_PERIL */
0554     GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
0555         GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
0556     GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
0557         GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
0558     GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
0559         GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
0560     GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
0561         GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
0562 
0563     GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
0564         GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
0565     GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
0566         GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
0567     GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
0568         GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
0569 
0570     /* GATE_IP_CAM */
0571     GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
0572         CLK_IGNORE_UNUSED, 0),
0573     GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
0574         GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0),
0575     GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
0576         GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0),
0577     GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
0578         GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0),
0579     GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
0580         GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0),
0581     GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
0582         GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0),
0583     GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
0584         GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0),
0585     GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
0586         GATE_IP_CAM, 11, 0, 0),
0587     GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
0588         GATE_IP_CAM, 9, 0, 0),
0589     GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
0590         GATE_IP_CAM, 8, 0, 0),
0591     GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
0592         GATE_IP_CAM, 7, 0, 0),
0593     GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
0594     GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
0595         GATE_IP_CAM, 2, 0, 0),
0596     GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
0597     GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
0598 
0599     /* GATE_IP_MFC */
0600     GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
0601         CLK_IGNORE_UNUSED, 0),
0602     GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
0603         CLK_IGNORE_UNUSED, 0),
0604     GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
0605     GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
0606 
0607     /* GATE_IP_G3D */
0608     GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
0609     GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
0610         CLK_IGNORE_UNUSED, 0),
0611     GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
0612         CLK_IGNORE_UNUSED, 0),
0613     GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
0614 
0615     /* GATE_IP_LCD */
0616     GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
0617         CLK_IGNORE_UNUSED, 0),
0618     GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
0619         CLK_IGNORE_UNUSED, 0),
0620     GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
0621         CLK_IGNORE_UNUSED, 0),
0622     GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
0623     GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
0624     GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
0625     GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
0626 
0627     /* GATE_IP_ISP */
0628     GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
0629     GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
0630         GATE_IP_ISP, 3, 0, 0),
0631     GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
0632         GATE_IP_ISP, 2, 0, 0),
0633     GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
0634         GATE_IP_ISP, 1, 0, 0),
0635 
0636     /* GATE_IP_FSYS */
0637     GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
0638     GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
0639         CLK_IGNORE_UNUSED, 0),
0640     GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
0641     GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
0642     GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
0643     GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
0644     GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
0645     GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
0646     GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
0647     GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
0648 
0649     /* GATE_IP_PERIL */
0650     GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
0651     GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
0652     GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
0653     GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
0654     GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
0655     GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
0656     GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
0657     GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
0658     GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
0659     GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
0660     GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
0661     GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
0662     GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
0663     GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
0664     GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
0665     GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
0666 };
0667 
0668 /* APLL & MPLL & BPLL & UPLL */
0669 static const struct samsung_pll_rate_table exynos3250_pll_rates[] __initconst = {
0670     PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
0671     PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
0672     PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
0673     PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
0674     PLL_35XX_RATE(24 * MHZ,  960000000, 320, 4, 1),
0675     PLL_35XX_RATE(24 * MHZ,  900000000, 300, 4, 1),
0676     PLL_35XX_RATE(24 * MHZ,  850000000, 425, 6, 1),
0677     PLL_35XX_RATE(24 * MHZ,  800000000, 200, 3, 1),
0678     PLL_35XX_RATE(24 * MHZ,  700000000, 175, 3, 1),
0679     PLL_35XX_RATE(24 * MHZ,  667000000, 667, 12, 1),
0680     PLL_35XX_RATE(24 * MHZ,  600000000, 400, 4, 2),
0681     PLL_35XX_RATE(24 * MHZ,  533000000, 533, 6, 2),
0682     PLL_35XX_RATE(24 * MHZ,  520000000, 260, 3, 2),
0683     PLL_35XX_RATE(24 * MHZ,  500000000, 250, 3, 2),
0684     PLL_35XX_RATE(24 * MHZ,  400000000, 200, 3, 2),
0685     PLL_35XX_RATE(24 * MHZ,  200000000, 200, 3, 3),
0686     PLL_35XX_RATE(24 * MHZ,  100000000, 200, 3, 4),
0687     { /* sentinel */ }
0688 };
0689 
0690 /* EPLL */
0691 static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst = {
0692     PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1,     0),
0693     PLL_36XX_RATE(24 * MHZ, 288000000,  96, 2, 2,     0),
0694     PLL_36XX_RATE(24 * MHZ, 192000000, 128, 2, 3,     0),
0695     PLL_36XX_RATE(24 * MHZ, 144000000,  96, 2, 3,     0),
0696     PLL_36XX_RATE(24 * MHZ,  96000000, 128, 2, 4,     0),
0697     PLL_36XX_RATE(24 * MHZ,  84000000, 112, 2, 4,     0),
0698     PLL_36XX_RATE(24 * MHZ,  80000003, 106, 2, 4, 43691),
0699     PLL_36XX_RATE(24 * MHZ,  73728000,  98, 2, 4, 19923),
0700     PLL_36XX_RATE(24 * MHZ,  67737598, 270, 3, 5, 62285),
0701     PLL_36XX_RATE(24 * MHZ,  65535999, 174, 2, 5, 49982),
0702     PLL_36XX_RATE(24 * MHZ,  50000000, 200, 3, 5,     0),
0703     PLL_36XX_RATE(24 * MHZ,  49152002, 131, 2, 5,  4719),
0704     PLL_36XX_RATE(24 * MHZ,  48000000, 128, 2, 5,     0),
0705     PLL_36XX_RATE(24 * MHZ,  45158401, 180, 3, 5, 41524),
0706     { /* sentinel */ }
0707 };
0708 
0709 /* VPLL */
0710 static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst = {
0711     PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1,     0),
0712     PLL_36XX_RATE(24 * MHZ, 533000000, 266, 3, 2, 32768),
0713     PLL_36XX_RATE(24 * MHZ, 519230987, 173, 2, 2,  5046),
0714     PLL_36XX_RATE(24 * MHZ, 500000000, 250, 3, 2,     0),
0715     PLL_36XX_RATE(24 * MHZ, 445500000, 148, 2, 2, 32768),
0716     PLL_36XX_RATE(24 * MHZ, 445055007, 148, 2, 2, 23047),
0717     PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2,     0),
0718     PLL_36XX_RATE(24 * MHZ, 371250000, 123, 2, 2, 49152),
0719     PLL_36XX_RATE(24 * MHZ, 370878997, 185, 3, 2, 28803),
0720     PLL_36XX_RATE(24 * MHZ, 340000000, 170, 3, 2,     0),
0721     PLL_36XX_RATE(24 * MHZ, 335000015, 111, 2, 2, 43691),
0722     PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2,     0),
0723     PLL_36XX_RATE(24 * MHZ, 330000000, 110, 2, 2,     0),
0724     PLL_36XX_RATE(24 * MHZ, 320000015, 106, 2, 2, 43691),
0725     PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2,     0),
0726     PLL_36XX_RATE(24 * MHZ, 275000000, 275, 3, 3,     0),
0727     PLL_36XX_RATE(24 * MHZ, 222750000, 148, 2, 3, 32768),
0728     PLL_36XX_RATE(24 * MHZ, 222528007, 148, 2, 3, 23069),
0729     PLL_36XX_RATE(24 * MHZ, 160000000, 160, 3, 3,     0),
0730     PLL_36XX_RATE(24 * MHZ, 148500000,  99, 2, 3,     0),
0731     PLL_36XX_RATE(24 * MHZ, 148352005,  98, 2, 3, 59070),
0732     PLL_36XX_RATE(24 * MHZ, 108000000, 144, 2, 4,     0),
0733     PLL_36XX_RATE(24 * MHZ,  74250000,  99, 2, 4,     0),
0734     PLL_36XX_RATE(24 * MHZ,  74176002,  98, 2, 4, 59070),
0735     PLL_36XX_RATE(24 * MHZ,  54054000, 216, 3, 5, 14156),
0736     PLL_36XX_RATE(24 * MHZ,  54000000, 144, 2, 5,     0),
0737     { /* sentinel */ }
0738 };
0739 
0740 static const struct samsung_pll_clock exynos3250_plls[] __initconst = {
0741     PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
0742         APLL_LOCK, APLL_CON0, exynos3250_pll_rates),
0743     PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
0744             MPLL_LOCK, MPLL_CON0, exynos3250_pll_rates),
0745     PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
0746             VPLL_LOCK, VPLL_CON0, exynos3250_vpll_rates),
0747     PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
0748             UPLL_LOCK, UPLL_CON0, exynos3250_pll_rates),
0749 };
0750 
0751 #define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem)          \
0752         (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) |  \
0753         ((corem) << 4))
0754 #define E3250_CPU_DIV1(hpm, copy)                   \
0755         (((hpm) << 4) | ((copy) << 0))
0756 
0757 static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
0758     { 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
0759     {  900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
0760     {  800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
0761     {  700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
0762     {  600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
0763     {  500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
0764     {  400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
0765     {  300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
0766     {  200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
0767     {  100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
0768     {  0 },
0769 };
0770 
0771 static const struct samsung_cpu_clock exynos3250_cpu_clks[] __initconst = {
0772     CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
0773             CLK_CPU_HAS_DIV1, 0x14200, e3250_armclk_d),
0774 };
0775 
0776 static void __init exynos3_core_down_clock(void __iomem *reg_base)
0777 {
0778     unsigned int tmp;
0779 
0780     /*
0781      * Enable arm clock down (in idle) and set arm divider
0782      * ratios in WFI/WFE state.
0783      */
0784     tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
0785         PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
0786         PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
0787         PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
0788     __raw_writel(tmp, reg_base + PWR_CTRL1);
0789 
0790     /*
0791      * Disable the clock up feature on Exynos4x12, in case it was
0792      * enabled by bootloader.
0793      */
0794     __raw_writel(0x0, reg_base + PWR_CTRL2);
0795 }
0796 
0797 static const struct samsung_cmu_info cmu_info __initconst = {
0798     .pll_clks       = exynos3250_plls,
0799     .nr_pll_clks        = ARRAY_SIZE(exynos3250_plls),
0800     .mux_clks       = mux_clks,
0801     .nr_mux_clks        = ARRAY_SIZE(mux_clks),
0802     .div_clks       = div_clks,
0803     .nr_div_clks        = ARRAY_SIZE(div_clks),
0804     .gate_clks      = gate_clks,
0805     .nr_gate_clks       = ARRAY_SIZE(gate_clks),
0806     .fixed_factor_clks  = fixed_factor_clks,
0807     .nr_fixed_factor_clks   = ARRAY_SIZE(fixed_factor_clks),
0808     .cpu_clks       = exynos3250_cpu_clks,
0809     .nr_cpu_clks        = ARRAY_SIZE(exynos3250_cpu_clks),
0810     .nr_clk_ids     = CLK_NR_CLKS,
0811     .clk_regs       = exynos3250_cmu_clk_regs,
0812     .nr_clk_regs        = ARRAY_SIZE(exynos3250_cmu_clk_regs),
0813 };
0814 
0815 static void __init exynos3250_cmu_init(struct device_node *np)
0816 {
0817     struct samsung_clk_provider *ctx;
0818 
0819     ctx = samsung_cmu_register_one(np, &cmu_info);
0820     if (!ctx)
0821         return;
0822 
0823     exynos3_core_down_clock(ctx->reg_base);
0824 }
0825 CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
0826 
0827 /*
0828  * CMU DMC
0829  */
0830 
0831 #define BPLL_LOCK       0x0118
0832 #define BPLL_CON0       0x0218
0833 #define BPLL_CON1       0x021c
0834 #define BPLL_CON2       0x0220
0835 #define SRC_DMC         0x0300
0836 #define DIV_DMC1        0x0504
0837 #define GATE_BUS_DMC0       0x0700
0838 #define GATE_BUS_DMC1       0x0704
0839 #define GATE_BUS_DMC2       0x0708
0840 #define GATE_BUS_DMC3       0x070c
0841 #define GATE_SCLK_DMC       0x0800
0842 #define GATE_IP_DMC0        0x0900
0843 #define GATE_IP_DMC1        0x0904
0844 #define EPLL_LOCK       0x1110
0845 #define EPLL_CON0       0x1114
0846 #define EPLL_CON1       0x1118
0847 #define EPLL_CON2       0x111c
0848 #define SRC_EPLL        0x1120
0849 
0850 static const unsigned long exynos3250_cmu_dmc_clk_regs[] __initconst = {
0851     BPLL_LOCK,
0852     BPLL_CON0,
0853     BPLL_CON1,
0854     BPLL_CON2,
0855     SRC_DMC,
0856     DIV_DMC1,
0857     GATE_BUS_DMC0,
0858     GATE_BUS_DMC1,
0859     GATE_BUS_DMC2,
0860     GATE_BUS_DMC3,
0861     GATE_SCLK_DMC,
0862     GATE_IP_DMC0,
0863     GATE_IP_DMC1,
0864     EPLL_LOCK,
0865     EPLL_CON0,
0866     EPLL_CON1,
0867     EPLL_CON2,
0868     SRC_EPLL,
0869 };
0870 
0871 PNAME(mout_epll_p)  = { "fin_pll", "fout_epll", };
0872 PNAME(mout_bpll_p)  = { "fin_pll", "fout_bpll", };
0873 PNAME(mout_mpll_mif_p)  = { "fin_pll", "sclk_mpll_mif", };
0874 PNAME(mout_dphy_p)  = { "mout_mpll_mif", "mout_bpll", };
0875 
0876 static const struct samsung_mux_clock dmc_mux_clks[] __initconst = {
0877     /*
0878      * NOTE: Following table is sorted by register address in ascending
0879      * order and then bitfield shift in descending order, as it is done
0880      * in the User's Manual. When adding new entries, please make sure
0881      * that the order is preserved, to avoid merge conflicts and make
0882      * further work with defined data easier.
0883      */
0884 
0885     /* SRC_DMC */
0886     MUX(CLK_MOUT_MPLL_MIF, "mout_mpll_mif", mout_mpll_mif_p, SRC_DMC, 12, 1),
0887     MUX(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
0888     MUX(CLK_MOUT_DPHY, "mout_dphy", mout_dphy_p, SRC_DMC, 8, 1),
0889     MUX(CLK_MOUT_DMC_BUS, "mout_dmc_bus", mout_dphy_p, SRC_DMC,  4, 1),
0890 
0891     /* SRC_EPLL */
0892     MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_EPLL, 4, 1),
0893 };
0894 
0895 static const struct samsung_div_clock dmc_div_clks[] __initconst = {
0896     /*
0897      * NOTE: Following table is sorted by register address in ascending
0898      * order and then bitfield shift in descending order, as it is done
0899      * in the User's Manual. When adding new entries, please make sure
0900      * that the order is preserved, to avoid merge conflicts and make
0901      * further work with defined data easier.
0902      */
0903 
0904     /* DIV_DMC1 */
0905     DIV(CLK_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
0906     DIV(CLK_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
0907     DIV(CLK_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus", DIV_DMC1, 19, 2),
0908     DIV(CLK_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
0909     DIV(CLK_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
0910 };
0911 
0912 static const struct samsung_pll_clock exynos3250_dmc_plls[] __initconst = {
0913     PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
0914         BPLL_LOCK, BPLL_CON0, exynos3250_pll_rates),
0915     PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
0916         EPLL_LOCK, EPLL_CON0, exynos3250_epll_rates),
0917 };
0918 
0919 static const struct samsung_cmu_info dmc_cmu_info __initconst = {
0920     .pll_clks       = exynos3250_dmc_plls,
0921     .nr_pll_clks        = ARRAY_SIZE(exynos3250_dmc_plls),
0922     .mux_clks       = dmc_mux_clks,
0923     .nr_mux_clks        = ARRAY_SIZE(dmc_mux_clks),
0924     .div_clks       = dmc_div_clks,
0925     .nr_div_clks        = ARRAY_SIZE(dmc_div_clks),
0926     .nr_clk_ids     = NR_CLKS_DMC,
0927     .clk_regs       = exynos3250_cmu_dmc_clk_regs,
0928     .nr_clk_regs        = ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),
0929 };
0930 
0931 static void __init exynos3250_cmu_dmc_init(struct device_node *np)
0932 {
0933     samsung_cmu_register_one(np, &dmc_cmu_info);
0934 }
0935 CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",
0936         exynos3250_cmu_dmc_init);
0937 
0938 
0939 /*
0940  * CMU ISP
0941  */
0942 
0943 #define DIV_ISP0        0x300
0944 #define DIV_ISP1        0x304
0945 #define GATE_IP_ISP0        0x800
0946 #define GATE_IP_ISP1        0x804
0947 #define GATE_SCLK_ISP       0x900
0948 
0949 static const struct samsung_div_clock isp_div_clks[] __initconst = {
0950     /*
0951      * NOTE: Following table is sorted by register address in ascending
0952      * order and then bitfield shift in descending order, as it is done
0953      * in the User's Manual. When adding new entries, please make sure
0954      * that the order is preserved, to avoid merge conflicts and make
0955      * further work with defined data easier.
0956      */
0957     /* DIV_ISP0 */
0958     DIV(CLK_DIV_ISP1, "div_isp1", "mout_aclk_266_sub", DIV_ISP0, 4, 3),
0959     DIV(CLK_DIV_ISP0, "div_isp0", "mout_aclk_266_sub", DIV_ISP0, 0, 3),
0960 
0961     /* DIV_ISP1 */
0962     DIV(CLK_DIV_MCUISP1, "div_mcuisp1", "mout_aclk_400_mcuisp_sub",
0963         DIV_ISP1, 8, 3),
0964     DIV(CLK_DIV_MCUISP0, "div_mcuisp0", "mout_aclk_400_mcuisp_sub",
0965         DIV_ISP1, 4, 3),
0966     DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3),
0967 };
0968 
0969 static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
0970     /*
0971      * NOTE: Following table is sorted by register address in ascending
0972      * order and then bitfield shift in descending order, as it is done
0973      * in the User's Manual. When adding new entries, please make sure
0974      * that the order is preserved, to avoid merge conflicts and make
0975      * further work with defined data easier.
0976      */
0977 
0978     /* GATE_IP_ISP0 */
0979     GATE(CLK_UART_ISP, "uart_isp", "uart_isp_top",
0980         GATE_IP_ISP0, 31, CLK_IGNORE_UNUSED, 0),
0981     GATE(CLK_WDT_ISP, "wdt_isp", "mout_aclk_266_sub",
0982         GATE_IP_ISP0, 30, CLK_IGNORE_UNUSED, 0),
0983     GATE(CLK_PWM_ISP, "pwm_isp", "mout_aclk_266_sub",
0984         GATE_IP_ISP0, 28, CLK_IGNORE_UNUSED, 0),
0985     GATE(CLK_I2C1_ISP, "i2c1_isp", "mout_aclk_266_sub",
0986         GATE_IP_ISP0, 26, CLK_IGNORE_UNUSED, 0),
0987     GATE(CLK_I2C0_ISP, "i2c0_isp", "mout_aclk_266_sub",
0988         GATE_IP_ISP0, 25, CLK_IGNORE_UNUSED, 0),
0989     GATE(CLK_MPWM_ISP, "mpwm_isp", "mout_aclk_266_sub",
0990         GATE_IP_ISP0, 24, CLK_IGNORE_UNUSED, 0),
0991     GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "mout_aclk_266_sub",
0992         GATE_IP_ISP0, 23, CLK_IGNORE_UNUSED, 0),
0993     GATE(CLK_PPMUISPX, "ppmuispx", "mout_aclk_266_sub",
0994         GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
0995     GATE(CLK_PPMUISPMX, "ppmuispmx", "mout_aclk_266_sub",
0996         GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
0997     GATE(CLK_QE_LITE1, "qe_lite1", "mout_aclk_266_sub",
0998         GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
0999     GATE(CLK_QE_LITE0, "qe_lite0", "mout_aclk_266_sub",
1000         GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
1001     GATE(CLK_QE_FD, "qe_fd", "mout_aclk_266_sub",
1002         GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
1003     GATE(CLK_QE_DRC, "qe_drc", "mout_aclk_266_sub",
1004         GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
1005     GATE(CLK_QE_ISP, "qe_isp", "mout_aclk_266_sub",
1006         GATE_IP_ISP0, 14, CLK_IGNORE_UNUSED, 0),
1007     GATE(CLK_CSIS1, "csis1", "mout_aclk_266_sub",
1008         GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
1009     GATE(CLK_SMMU_LITE1, "smmu_lite1", "mout_aclk_266_sub",
1010         GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
1011     GATE(CLK_SMMU_LITE0, "smmu_lite0", "mout_aclk_266_sub",
1012         GATE_IP_ISP0, 11, CLK_IGNORE_UNUSED, 0),
1013     GATE(CLK_SMMU_FD, "smmu_fd", "mout_aclk_266_sub",
1014         GATE_IP_ISP0, 10, CLK_IGNORE_UNUSED, 0),
1015     GATE(CLK_SMMU_DRC, "smmu_drc", "mout_aclk_266_sub",
1016         GATE_IP_ISP0, 9, CLK_IGNORE_UNUSED, 0),
1017     GATE(CLK_SMMU_ISP, "smmu_isp", "mout_aclk_266_sub",
1018         GATE_IP_ISP0, 8, CLK_IGNORE_UNUSED, 0),
1019     GATE(CLK_GICISP, "gicisp", "mout_aclk_266_sub",
1020         GATE_IP_ISP0, 7, CLK_IGNORE_UNUSED, 0),
1021     GATE(CLK_CSIS0, "csis0", "mout_aclk_266_sub",
1022         GATE_IP_ISP0, 6, CLK_IGNORE_UNUSED, 0),
1023     GATE(CLK_MCUISP, "mcuisp", "mout_aclk_266_sub",
1024         GATE_IP_ISP0, 5, CLK_IGNORE_UNUSED, 0),
1025     GATE(CLK_LITE1, "lite1", "mout_aclk_266_sub",
1026         GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
1027     GATE(CLK_LITE0, "lite0", "mout_aclk_266_sub",
1028         GATE_IP_ISP0, 3, CLK_IGNORE_UNUSED, 0),
1029     GATE(CLK_FD, "fd", "mout_aclk_266_sub",
1030         GATE_IP_ISP0, 2, CLK_IGNORE_UNUSED, 0),
1031     GATE(CLK_DRC, "drc", "mout_aclk_266_sub",
1032         GATE_IP_ISP0, 1, CLK_IGNORE_UNUSED, 0),
1033     GATE(CLK_ISP, "isp", "mout_aclk_266_sub",
1034         GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
1035 
1036     /* GATE_IP_ISP1 */
1037     GATE(CLK_QE_ISPCX, "qe_ispcx", "uart_isp_top",
1038         GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
1039     GATE(CLK_QE_SCALERP, "qe_scalerp", "uart_isp_top",
1040         GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
1041     GATE(CLK_QE_SCALERC, "qe_scalerc", "uart_isp_top",
1042         GATE_IP_ISP0, 19, CLK_IGNORE_UNUSED, 0),
1043     GATE(CLK_SMMU_SCALERP, "smmu_scalerp", "uart_isp_top",
1044         GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
1045     GATE(CLK_SMMU_SCALERC, "smmu_scalerc", "uart_isp_top",
1046         GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
1047     GATE(CLK_SCALERP, "scalerp", "uart_isp_top",
1048         GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
1049     GATE(CLK_SCALERC, "scalerc", "uart_isp_top",
1050         GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
1051     GATE(CLK_SPI1_ISP, "spi1_isp", "uart_isp_top",
1052         GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
1053     GATE(CLK_SPI0_ISP, "spi0_isp", "uart_isp_top",
1054         GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
1055     GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "uart_isp_top",
1056         GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
1057     GATE(CLK_ASYNCAXIM, "asyncaxim", "uart_isp_top",
1058         GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
1059 
1060     /* GATE_SCLK_ISP */
1061     GATE(CLK_SCLK_MPWM_ISP, "sclk_mpwm_isp", "div_mpwm",
1062         GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
1063 };
1064 
1065 static const struct samsung_cmu_info isp_cmu_info __initconst = {
1066     .div_clks   = isp_div_clks,
1067     .nr_div_clks    = ARRAY_SIZE(isp_div_clks),
1068     .gate_clks  = isp_gate_clks,
1069     .nr_gate_clks   = ARRAY_SIZE(isp_gate_clks),
1070     .nr_clk_ids = NR_CLKS_ISP,
1071 };
1072 
1073 static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)
1074 {
1075     struct device_node *np = pdev->dev.of_node;
1076 
1077     samsung_cmu_register_one(np, &isp_cmu_info);
1078     return 0;
1079 }
1080 
1081 static const struct of_device_id exynos3250_cmu_isp_of_match[] __initconst = {
1082     { .compatible = "samsung,exynos3250-cmu-isp", },
1083     { /* sentinel */ }
1084 };
1085 
1086 static struct platform_driver exynos3250_cmu_isp_driver __initdata = {
1087     .driver = {
1088         .name = "exynos3250-cmu-isp",
1089         .suppress_bind_attrs = true,
1090         .of_match_table = exynos3250_cmu_isp_of_match,
1091     },
1092 };
1093 
1094 static int __init exynos3250_cmu_platform_init(void)
1095 {
1096     return platform_driver_probe(&exynos3250_cmu_isp_driver,
1097                     exynos3250_cmu_isp_probe);
1098 }
1099 subsys_initcall(exynos3250_cmu_platform_init);
1100
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