clk/samsung/clk-exynos-audss.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
0004  * Author: Padmavathi Venna <padma.v@samsung.com>
0005  *
0006  * Common Clock Framework support for Audio Subsystem Clock Controller.
0007 */
0008
0009 #include <linux/slab.h>
0010 #include <linux/io.h>
0011 #include <linux/clk.h>
0012 #include <linux/clk-provider.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_device.h>
0015 #include <linux/module.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm_runtime.h>
0018
0019 #include <dt-bindings/clock/exynos-audss-clk.h>
0020
0021 static DEFINE_SPINLOCK(lock);
0022 static void __iomem *reg_base;
0023 static struct clk_hw_onecell_data *clk_data;
0024 /*
0025  * On Exynos5420 this will be a clock which has to be enabled before any
0026  * access to audss registers. Typically a child of EPLL.
0027  *
0028  * On other platforms this will be -ENODEV.
0029  */
0030 static struct clk *epll;
0031
0032 #define ASS_CLK_SRC 0x0
0033 #define ASS_CLK_DIV 0x4
0034 #define ASS_CLK_GATE 0x8
0035
0036 static unsigned long reg_save[][2] = {
0037     { ASS_CLK_SRC,  0 },
0038     { ASS_CLK_DIV,  0 },
0039     { ASS_CLK_GATE, 0 },
0040 };
0041
0042 static int __maybe_unused exynos_audss_clk_suspend(struct device *dev)
0043 {
0044     int i;
0045
0046     for (i = 0; i < ARRAY_SIZE(reg_save); i++)
0047         reg_save[i][1] = readl(reg_base + reg_save[i][0]);
0048
0049     return 0;
0050 }
0051
0052 static int __maybe_unused exynos_audss_clk_resume(struct device *dev)
0053 {
0054     int i;
0055
0056     for (i = 0; i < ARRAY_SIZE(reg_save); i++)
0057         writel(reg_save[i][1], reg_base + reg_save[i][0]);
0058
0059     return 0;
0060 }
0061
0062 struct exynos_audss_clk_drvdata {
0063     unsigned int has_adma_clk:1;
0064     unsigned int has_mst_clk:1;
0065     unsigned int enable_epll:1;
0066     unsigned int num_clks;
0067 };
0068
0069 static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
0070     .num_clks   = EXYNOS_AUDSS_MAX_CLKS - 1,
0071     .enable_epll    = 1,
0072 };
0073
0074 static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
0075     .num_clks   = EXYNOS_AUDSS_MAX_CLKS - 1,
0076     .has_mst_clk    = 1,
0077 };
0078
0079 static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
0080     .num_clks   = EXYNOS_AUDSS_MAX_CLKS,
0081     .has_adma_clk   = 1,
0082     .enable_epll    = 1,
0083 };
0084
0085 static const struct of_device_id exynos_audss_clk_of_match[] = {
0086     {
0087         .compatible = "samsung,exynos4210-audss-clock",
0088         .data       = &exynos4210_drvdata,
0089     }, {
0090         .compatible = "samsung,exynos5250-audss-clock",
0091         .data       = &exynos4210_drvdata,
0092     }, {
0093         .compatible = "samsung,exynos5410-audss-clock",
0094         .data       = &exynos5410_drvdata,
0095     }, {
0096         .compatible = "samsung,exynos5420-audss-clock",
0097         .data       = &exynos5420_drvdata,
0098     },
0099     { },
0100 };
0101 MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
0102
0103 static void exynos_audss_clk_teardown(void)
0104 {
0105     int i;
0106
0107     for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
0108         if (!IS_ERR(clk_data->hws[i]))
0109             clk_hw_unregister_mux(clk_data->hws[i]);
0110     }
0111
0112     for (; i < EXYNOS_SRP_CLK; i++) {
0113         if (!IS_ERR(clk_data->hws[i]))
0114             clk_hw_unregister_divider(clk_data->hws[i]);
0115     }
0116
0117     for (; i < clk_data->num; i++) {
0118         if (!IS_ERR(clk_data->hws[i]))
0119             clk_hw_unregister_gate(clk_data->hws[i]);
0120     }
0121 }
0122
0123 /* register exynos_audss clocks */
0124 static int exynos_audss_clk_probe(struct platform_device *pdev)
0125 {
0126     const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
0127     const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
0128     const char *sclk_pcm_p = "sclk_pcm0";
0129     struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
0130     const struct exynos_audss_clk_drvdata *variant;
0131     struct clk_hw **clk_table;
0132     struct device *dev = &pdev->dev;
0133     int i, ret = 0;
0134
0135     variant = of_device_get_match_data(&pdev->dev);
0136     if (!variant)
0137         return -EINVAL;
0138
0139     reg_base = devm_platform_ioremap_resource(pdev, 0);
0140     if (IS_ERR(reg_base))
0141         return PTR_ERR(reg_base);
0142
0143     epll = ERR_PTR(-ENODEV);
0144
0145     clk_data = devm_kzalloc(dev,
0146                 struct_size(clk_data, hws,
0147                         EXYNOS_AUDSS_MAX_CLKS),
0148                 GFP_KERNEL);
0149     if (!clk_data)
0150         return -ENOMEM;
0151
0152     clk_data->num = variant->num_clks;
0153     clk_table = clk_data->hws;
0154
0155     pll_ref = devm_clk_get(dev, "pll_ref");
0156     pll_in = devm_clk_get(dev, "pll_in");
0157     if (!IS_ERR(pll_ref))
0158         mout_audss_p[0] = __clk_get_name(pll_ref);
0159     if (!IS_ERR(pll_in)) {
0160         mout_audss_p[1] = __clk_get_name(pll_in);
0161
0162         if (variant->enable_epll) {
0163             epll = pll_in;
0164
0165             ret = clk_prepare_enable(epll);
0166             if (ret) {
0167                 dev_err(dev,
0168                     "failed to prepare the epll clock\n");
0169                 return ret;
0170             }
0171         }
0172     }
0173
0174     /*
0175      * Enable runtime PM here to allow the clock core using runtime PM
0176      * for the registered clocks. Additionally, we increase the runtime
0177      * PM usage count before registering the clocks, to prevent the
0178      * clock core from runtime suspending the device.
0179      */
0180     pm_runtime_get_noresume(dev);
0181     pm_runtime_set_active(dev);
0182     pm_runtime_enable(dev);
0183
0184     clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss",
0185                 mout_audss_p, ARRAY_SIZE(mout_audss_p),
0186                 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
0187                 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
0188
0189     cdclk = devm_clk_get(dev, "cdclk");
0190     sclk_audio = devm_clk_get(dev, "sclk_audio");
0191     if (!IS_ERR(cdclk))
0192         mout_i2s_p[1] = __clk_get_name(cdclk);
0193     if (!IS_ERR(sclk_audio))
0194         mout_i2s_p[2] = __clk_get_name(sclk_audio);
0195     clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s",
0196                 mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
0197                 CLK_SET_RATE_NO_REPARENT,
0198                 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
0199
0200     clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp",
0201                 "mout_audss", CLK_SET_RATE_PARENT,
0202                 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
0203
0204     clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev,
0205                 "dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT,
0206                 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
0207
0208     clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
0209                 "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
0210                 &lock);
0211
0212     clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk",
0213                 "dout_srp", CLK_SET_RATE_PARENT,
0214                 reg_base + ASS_CLK_GATE, 0, 0, &lock);
0215
0216     clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus",
0217                 "dout_aud_bus", CLK_SET_RATE_PARENT,
0218                 reg_base + ASS_CLK_GATE, 2, 0, &lock);
0219
0220     clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s",
0221                 "dout_i2s", CLK_SET_RATE_PARENT,
0222                 reg_base + ASS_CLK_GATE, 3, 0, &lock);
0223
0224     clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus",
0225                  "sclk_pcm", CLK_SET_RATE_PARENT,
0226                 reg_base + ASS_CLK_GATE, 4, 0, &lock);
0227
0228     sclk_pcm_in = devm_clk_get(dev, "sclk_pcm_in");
0229     if (!IS_ERR(sclk_pcm_in))
0230         sclk_pcm_p = __clk_get_name(sclk_pcm_in);
0231     clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(dev, "sclk_pcm",
0232                 sclk_pcm_p, CLK_SET_RATE_PARENT,
0233                 reg_base + ASS_CLK_GATE, 5, 0, &lock);
0234
0235     if (variant->has_adma_clk) {
0236         clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma",
0237                 "dout_srp", CLK_SET_RATE_PARENT,
0238                 reg_base + ASS_CLK_GATE, 9, 0, &lock);
0239     }
0240
0241     for (i = 0; i < clk_data->num; i++) {
0242         if (IS_ERR(clk_table[i])) {
0243             dev_err(dev, "failed to register clock %d\n", i);
0244             ret = PTR_ERR(clk_table[i]);
0245             goto unregister;
0246         }
0247     }
0248
0249     ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
0250                      clk_data);
0251     if (ret) {
0252         dev_err(dev, "failed to add clock provider\n");
0253         goto unregister;
0254     }
0255
0256     pm_runtime_put_sync(dev);
0257
0258     return 0;
0259
0260 unregister:
0261     exynos_audss_clk_teardown();
0262     pm_runtime_put_sync(dev);
0263     pm_runtime_disable(dev);
0264
0265     if (!IS_ERR(epll))
0266         clk_disable_unprepare(epll);
0267
0268     return ret;
0269 }
0270
0271 static int exynos_audss_clk_remove(struct platform_device *pdev)
0272 {
0273     of_clk_del_provider(pdev->dev.of_node);
0274
0275     exynos_audss_clk_teardown();
0276     pm_runtime_disable(&pdev->dev);
0277
0278     if (!IS_ERR(epll))
0279         clk_disable_unprepare(epll);
0280
0281     return 0;
0282 }
0283
0284 static const struct dev_pm_ops exynos_audss_clk_pm_ops = {
0285     SET_RUNTIME_PM_OPS(exynos_audss_clk_suspend, exynos_audss_clk_resume,
0286                NULL)
0287     SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0288                      pm_runtime_force_resume)
0289 };
0290
0291 static struct platform_driver exynos_audss_clk_driver = {
0292     .driver = {
0293         .name = "exynos-audss-clk",
0294         .of_match_table = exynos_audss_clk_of_match,
0295         .pm = &exynos_audss_clk_pm_ops,
0296     },
0297     .probe = exynos_audss_clk_probe,
0298     .remove = exynos_audss_clk_remove,
0299 };
0300
0301 module_platform_driver(exynos_audss_clk_driver);
0302
0303 MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
0304 MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
0305 MODULE_LICENSE("GPL v2");
0306 MODULE_ALIAS("platform:exynos-audss-clk");