clk/samsung/clk-cpu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
0004  *
0005  * Common Clock Framework support for all PLL's in Samsung platforms
0006 */
0007
0008 #ifndef __SAMSUNG_CLK_CPU_H
0009 #define __SAMSUNG_CLK_CPU_H
0010
0011 #include "clk.h"
0012
0013 /**
0014  * struct exynos_cpuclk_data: config data to setup cpu clocks.
0015  * @prate: frequency of the primary parent clock (in KHz).
0016  * @div0: value to be programmed in the div_cpu0 register.
0017  * @div1: value to be programmed in the div_cpu1 register.
0018  *
0019  * This structure holds the divider configuration data for dividers in the CPU
0020  * clock domain. The parent frequency at which these divider values are valid is
0021  * specified in @prate. The @prate is the frequency of the primary parent clock.
0022  * For CPU clock domains that do not have a DIV1 register, the @div1 member
0023  * value is not used.
0024  */
0025 struct exynos_cpuclk_cfg_data {
0026     unsigned long   prate;
0027     unsigned long   div0;
0028     unsigned long   div1;
0029 };
0030
0031 /**
0032  * struct exynos_cpuclk: information about clock supplied to a CPU core.
0033  * @hw: handle between CCF and CPU clock.
0034  * @alt_parent: alternate parent clock to use when switching the speed
0035  *  of the primary parent clock.
0036  * @ctrl_base:  base address of the clock controller.
0037  * @lock: cpu clock domain register access lock.
0038  * @cfg: cpu clock rate configuration data.
0039  * @num_cfgs: number of array elements in @cfg array.
0040  * @clk_nb: clock notifier registered for changes in clock speed of the
0041  *  primary parent clock.
0042  * @flags: configuration flags for the CPU clock.
0043  *
0044  * This structure holds information required for programming the CPU clock for
0045  * various clock speeds.
0046  */
0047 struct exynos_cpuclk {
0048     struct clk_hw               hw;
0049     const struct clk_hw         *alt_parent;
0050     void __iomem                *ctrl_base;
0051     spinlock_t              *lock;
0052     const struct exynos_cpuclk_cfg_data *cfg;
0053     const unsigned long         num_cfgs;
0054     struct notifier_block           clk_nb;
0055     unsigned long               flags;
0056
0057 /* The CPU clock registers have DIV1 configuration register */
0058 #define CLK_CPU_HAS_DIV1        (1 << 0)
0059 /* When ALT parent is active, debug clocks need safe divider values */
0060 #define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1)
0061 /* The CPU clock registers have Exynos5433-compatible layout */
0062 #define CLK_CPU_HAS_E5433_REGS_LAYOUT   (1 << 2)
0063 };
0064
0065 #endif /* __SAMSUNG_CLK_CPU_H */