clk/rockchip/clk-rk3568.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
0004  * Author: Elaine Zhang <zhangqing@rock-chips.com>
0005  */
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/module.h>
0009 #include <linux/of.h>
0010 #include <linux/of_device.h>
0011 #include <linux/of_address.h>
0012 #include <linux/syscore_ops.h>
0013 #include <dt-bindings/clock/rk3568-cru.h>
0014 #include "clk.h"
0015
0016 #define RK3568_GRF_SOC_STATUS0  0x580
0017
0018 enum rk3568_pmu_plls {
0019     ppll, hpll,
0020 };
0021
0022 enum rk3568_plls {
0023     apll, dpll, gpll, cpll, npll, vpll,
0024 };
0025
0026 static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
0027     /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
0028     RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
0029     RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
0030     RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
0031     RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
0032     RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
0033     RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
0034     RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
0035     RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
0036     RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
0037     RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
0038     RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
0039     RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
0040     RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
0041     RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
0042     RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
0043     RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
0044     RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
0045     RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
0046     RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
0047     RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
0048     RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
0049     RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
0050     RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
0051     RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
0052     RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
0053     RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
0054     RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
0055     RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
0056     RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
0057     RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
0058     RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
0059     RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
0060     RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
0061     RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
0062     RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
0063     RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
0064     RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
0065     RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
0066     RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
0067     RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
0068     RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
0069     RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
0070     RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
0071     RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
0072     RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
0073     RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
0074     RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0),
0075     RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0),
0076     RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
0077     RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
0078     RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
0079     RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
0080     RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
0081     RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
0082     RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
0083     RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
0084     RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
0085     RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
0086     { /* sentinel */ },
0087 };
0088
0089 #define RK3568_DIV_ATCLK_CORE_MASK  0x1f
0090 #define RK3568_DIV_ATCLK_CORE_SHIFT 0
0091 #define RK3568_DIV_GICCLK_CORE_MASK 0x1f
0092 #define RK3568_DIV_GICCLK_CORE_SHIFT    8
0093 #define RK3568_DIV_PCLK_CORE_MASK   0x1f
0094 #define RK3568_DIV_PCLK_CORE_SHIFT  0
0095 #define RK3568_DIV_PERIPHCLK_CORE_MASK  0x1f
0096 #define RK3568_DIV_PERIPHCLK_CORE_SHIFT 8
0097 #define RK3568_DIV_ACLK_CORE_MASK   0x1f
0098 #define RK3568_DIV_ACLK_CORE_SHIFT  8
0099
0100 #define RK3568_DIV_SCLK_CORE_MASK   0xf
0101 #define RK3568_DIV_SCLK_CORE_SHIFT  0
0102 #define RK3568_MUX_SCLK_CORE_MASK   0x3
0103 #define RK3568_MUX_SCLK_CORE_SHIFT  8
0104 #define RK3568_MUX_SCLK_CORE_NPLL_MASK  0x1
0105 #define RK3568_MUX_SCLK_CORE_NPLL_SHIFT 15
0106 #define RK3568_MUX_CLK_CORE_APLL_MASK   0x1
0107 #define RK3568_MUX_CLK_CORE_APLL_SHIFT  7
0108 #define RK3568_MUX_CLK_PVTPLL_MASK  0x1
0109 #define RK3568_MUX_CLK_PVTPLL_SHIFT 15
0110
0111 #define RK3568_CLKSEL1(_sclk_core)                  \
0112 {                               \
0113     .reg = RK3568_CLKSEL_CON(2),                \
0114     .val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, \
0115             RK3568_MUX_SCLK_CORE_NPLL_SHIFT) |      \
0116            HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, \
0117             RK3568_MUX_SCLK_CORE_SHIFT) |       \
0118         HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, \
0119             RK3568_DIV_SCLK_CORE_SHIFT),        \
0120 }
0121
0122 #define RK3568_CLKSEL2(_aclk_core)                  \
0123 {                               \
0124     .reg = RK3568_CLKSEL_CON(5),                \
0125     .val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, \
0126             RK3568_DIV_ACLK_CORE_SHIFT),        \
0127 }
0128
0129 #define RK3568_CLKSEL3(_atclk_core, _gic_core)  \
0130 {                               \
0131     .reg = RK3568_CLKSEL_CON(3),                \
0132     .val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, \
0133             RK3568_DIV_ATCLK_CORE_SHIFT) |      \
0134            HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, \
0135             RK3568_DIV_GICCLK_CORE_SHIFT),      \
0136 }
0137
0138 #define RK3568_CLKSEL4(_pclk_core, _periph_core)    \
0139 {                               \
0140     .reg = RK3568_CLKSEL_CON(4),                \
0141     .val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, \
0142             RK3568_DIV_PCLK_CORE_SHIFT) |       \
0143            HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, \
0144             RK3568_DIV_PERIPHCLK_CORE_SHIFT),       \
0145 }
0146
0147 #define RK3568_CPUCLK_RATE(_prate, _sclk, _acore, _atcore, _gicclk, _pclk, _periph) \
0148 {                               \
0149     .prate = _prate##U,                 \
0150     .divs = {                       \
0151         RK3568_CLKSEL1(_sclk),              \
0152         RK3568_CLKSEL2(_acore),             \
0153         RK3568_CLKSEL3(_atcore, _gicclk),       \
0154         RK3568_CLKSEL4(_pclk, _periph),         \
0155     },                          \
0156 }
0157
0158 static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = {
0159     RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7),
0160     RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7),
0161     RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5),
0162     RK3568_CPUCLK_RATE(1584000000, 0, 1, 5, 5, 5, 5),
0163     RK3568_CPUCLK_RATE(1560000000, 0, 1, 5, 5, 5, 5),
0164     RK3568_CPUCLK_RATE(1536000000, 0, 1, 5, 5, 5, 5),
0165     RK3568_CPUCLK_RATE(1512000000, 0, 1, 5, 5, 5, 5),
0166     RK3568_CPUCLK_RATE(1488000000, 0, 1, 5, 5, 5, 5),
0167     RK3568_CPUCLK_RATE(1464000000, 0, 1, 5, 5, 5, 5),
0168     RK3568_CPUCLK_RATE(1440000000, 0, 1, 5, 5, 5, 5),
0169     RK3568_CPUCLK_RATE(1416000000, 0, 1, 5, 5, 5, 5),
0170     RK3568_CPUCLK_RATE(1392000000, 0, 1, 5, 5, 5, 5),
0171     RK3568_CPUCLK_RATE(1368000000, 0, 1, 5, 5, 5, 5),
0172     RK3568_CPUCLK_RATE(1344000000, 0, 1, 5, 5, 5, 5),
0173     RK3568_CPUCLK_RATE(1320000000, 0, 1, 5, 5, 5, 5),
0174     RK3568_CPUCLK_RATE(1296000000, 0, 1, 5, 5, 5, 5),
0175     RK3568_CPUCLK_RATE(1272000000, 0, 1, 5, 5, 5, 5),
0176     RK3568_CPUCLK_RATE(1248000000, 0, 1, 5, 5, 5, 5),
0177     RK3568_CPUCLK_RATE(1224000000, 0, 1, 5, 5, 5, 5),
0178     RK3568_CPUCLK_RATE(1200000000, 0, 1, 3, 3, 3, 3),
0179     RK3568_CPUCLK_RATE(1104000000, 0, 1, 3, 3, 3, 3),
0180     RK3568_CPUCLK_RATE(1008000000, 0, 1, 3, 3, 3, 3),
0181     RK3568_CPUCLK_RATE(912000000, 0, 1, 3, 3, 3, 3),
0182     RK3568_CPUCLK_RATE(816000000, 0, 1, 3, 3, 3, 3),
0183     RK3568_CPUCLK_RATE(696000000, 0, 1, 3, 3, 3, 3),
0184     RK3568_CPUCLK_RATE(600000000, 0, 1, 3, 3, 3, 3),
0185     RK3568_CPUCLK_RATE(408000000, 0, 1, 3, 3, 3, 3),
0186     RK3568_CPUCLK_RATE(312000000, 0, 1, 3, 3, 3, 3),
0187     RK3568_CPUCLK_RATE(216000000, 0, 1, 3, 3, 3, 3),
0188     RK3568_CPUCLK_RATE(96000000, 0, 1, 3, 3, 3, 3),
0189 };
0190
0191 static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {
0192     .core_reg[0] = RK3568_CLKSEL_CON(0),
0193     .div_core_shift[0] = 0,
0194     .div_core_mask[0] = 0x1f,
0195     .core_reg[1] = RK3568_CLKSEL_CON(0),
0196     .div_core_shift[1] = 8,
0197     .div_core_mask[1] = 0x1f,
0198     .core_reg[2] = RK3568_CLKSEL_CON(1),
0199     .div_core_shift[2] = 0,
0200     .div_core_mask[2] = 0x1f,
0201     .core_reg[3] = RK3568_CLKSEL_CON(1),
0202     .div_core_shift[3] = 8,
0203     .div_core_mask[3] = 0x1f,
0204     .num_cores = 4,
0205     .mux_core_alt = 1,
0206     .mux_core_main = 0,
0207     .mux_core_shift = 6,
0208     .mux_core_mask = 0x1,
0209 };
0210
0211 PNAME(mux_pll_p)            = { "xin24m" };
0212 PNAME(mux_usb480m_p)            = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
0213 PNAME(mux_armclk_p)         = { "apll", "gpll" };
0214 PNAME(clk_i2s0_8ch_tx_p)        = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
0215 PNAME(clk_i2s0_8ch_rx_p)        = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
0216 PNAME(clk_i2s1_8ch_tx_p)        = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" };
0217 PNAME(clk_i2s1_8ch_rx_p)        = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_osc0_half" };
0218 PNAME(clk_i2s2_2ch_p)           = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half "};
0219 PNAME(clk_i2s3_2ch_tx_p)        = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_osc0_half" };
0220 PNAME(clk_i2s3_2ch_rx_p)        = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_osc0_half" };
0221 PNAME(mclk_spdif_8ch_p)         = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" };
0222 PNAME(sclk_audpwm_p)            = { "sclk_audpwm_src", "sclk_audpwm_frac" };
0223 PNAME(sclk_uart1_p)         = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
0224 PNAME(sclk_uart2_p)         = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
0225 PNAME(sclk_uart3_p)         = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
0226 PNAME(sclk_uart4_p)         = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
0227 PNAME(sclk_uart5_p)         = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
0228 PNAME(sclk_uart6_p)         = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
0229 PNAME(sclk_uart7_p)         = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
0230 PNAME(sclk_uart8_p)         = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
0231 PNAME(sclk_uart9_p)         = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
0232 PNAME(sclk_uart0_p)         = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
0233 PNAME(clk_rtc32k_pmu_p)         = { "clk_32k_pvtm", "xin32k", "clk_rtc32k_frac" };
0234 PNAME(mpll_gpll_cpll_npll_p)        = { "mpll", "gpll", "cpll", "npll" };
0235 PNAME(gpll_cpll_npll_p)         = { "gpll", "cpll", "npll" };
0236 PNAME(npll_gpll_p)          = { "npll", "gpll" };
0237 PNAME(cpll_gpll_p)          = { "cpll", "gpll" };
0238 PNAME(gpll_cpll_p)          = { "gpll", "cpll" };
0239 PNAME(gpll_cpll_npll_vpll_p)        = { "gpll", "cpll", "npll", "vpll" };
0240 PNAME(apll_gpll_npll_p)         = { "apll", "gpll", "npll" };
0241 PNAME(sclk_core_pre_p)          = { "sclk_core_src", "npll" };
0242 PNAME(gpll150_gpll100_gpll75_xin24m_p)  = { "gpll_150m", "gpll_100m", "gpll_75m", "xin24m" };
0243 PNAME(clk_gpu_pre_mux_p)        = { "clk_gpu_src", "gpu_pvtpll_out" };
0244 PNAME(clk_npu_pre_ndft_p)       = { "clk_npu_src", "dummy"};
0245 PNAME(clk_npu_p)            = { "clk_npu_pre_ndft", "npu_pvtpll_out" };
0246 PNAME(dpll_gpll_cpll_p)         = { "dpll", "gpll", "cpll" };
0247 PNAME(clk_ddr1x_p)          = { "clk_ddrphy1x_src", "dpll" };
0248 PNAME(gpll200_gpll150_gpll100_xin24m_p) = { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" };
0249 PNAME(gpll100_gpll75_gpll50_p)      = { "gpll_100m", "gpll_75m", "cpll_50m" };
0250 PNAME(i2s0_mclkout_tx_p)        = { "clk_i2s0_8ch_tx", "xin_osc0_half" };
0251 PNAME(i2s0_mclkout_rx_p)        = { "clk_i2s0_8ch_rx", "xin_osc0_half" };
0252 PNAME(i2s1_mclkout_tx_p)        = { "clk_i2s1_8ch_tx", "xin_osc0_half" };
0253 PNAME(i2s1_mclkout_rx_p)        = { "clk_i2s1_8ch_rx", "xin_osc0_half" };
0254 PNAME(i2s2_mclkout_p)           = { "clk_i2s2_2ch", "xin_osc0_half" };
0255 PNAME(i2s3_mclkout_tx_p)        = { "clk_i2s3_2ch_tx", "xin_osc0_half" };
0256 PNAME(i2s3_mclkout_rx_p)        = { "clk_i2s3_2ch_rx", "xin_osc0_half" };
0257 PNAME(mclk_pdm_p)           = { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" };
0258 PNAME(clk_i2c_p)            = { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" };
0259 PNAME(gpll200_gpll150_gpll100_p)    = { "gpll_200m", "gpll_150m", "gpll_100m" };
0260 PNAME(gpll300_gpll200_gpll100_p)    = { "gpll_300m", "gpll_200m", "gpll_100m" };
0261 PNAME(clk_nandc_p)          = { "gpll_200m", "gpll_150m", "cpll_100m", "xin24m" };
0262 PNAME(sclk_sfc_p)           = { "xin24m", "cpll_50m", "gpll_75m", "gpll_100m", "cpll_125m", "gpll_150m" };
0263 PNAME(gpll200_gpll150_cpll125_p)    = { "gpll_200m", "gpll_150m", "cpll_125m" };
0264 PNAME(cclk_emmc_p)          = { "xin24m", "gpll_200m", "gpll_150m", "cpll_100m", "cpll_50m", "clk_osc0_div_375k" };
0265 PNAME(aclk_pipe_p)          = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" };
0266 PNAME(gpll200_cpll125_p)        = { "gpll_200m", "cpll_125m" };
0267 PNAME(gpll300_gpll200_gpll100_xin24m_p) = { "gpll_300m", "gpll_200m", "gpll_100m", "xin24m" };
0268 PNAME(clk_sdmmc_p)          = { "xin24m", "gpll_400m", "gpll_300m", "cpll_100m", "cpll_50m", "clk_osc0_div_750k" };
0269 PNAME(cpll125_cpll50_cpll25_xin24m_p)   = { "cpll_125m", "cpll_50m", "cpll_25m", "xin24m" };
0270 PNAME(clk_gmac_ptp_p)           = { "cpll_62p5", "gpll_100m", "cpll_50m", "xin24m" };
0271 PNAME(cpll333_gpll300_gpll200_p)    = { "cpll_333m", "gpll_300m", "gpll_200m" };
0272 PNAME(cpll_gpll_hpll_p)         = { "cpll", "gpll", "hpll" };
0273 PNAME(gpll_usb480m_xin24m_p)        = { "gpll", "usb480m", "xin24m", "xin24m" };
0274 PNAME(gpll300_cpll250_gpll100_xin24m_p) = { "gpll_300m", "cpll_250m", "gpll_100m", "xin24m" };
0275 PNAME(cpll_gpll_hpll_vpll_p)        = { "cpll", "gpll", "hpll", "vpll" };
0276 PNAME(hpll_vpll_gpll_cpll_p)        = { "hpll", "vpll", "gpll", "cpll" };
0277 PNAME(gpll400_cpll333_gpll200_p)    = { "gpll_400m", "cpll_333m", "gpll_200m" };
0278 PNAME(gpll100_gpll75_cpll50_xin24m_p)   = { "gpll_100m", "gpll_75m", "cpll_50m", "xin24m" };
0279 PNAME(xin24m_gpll100_cpll100_p)     = { "xin24m", "gpll_100m", "cpll_100m" };
0280 PNAME(gpll_cpll_usb480m_p)      = { "gpll", "cpll", "usb480m" };
0281 PNAME(gpll100_xin24m_cpll100_p)     = { "gpll_100m", "xin24m", "cpll_100m" };
0282 PNAME(gpll200_xin24m_cpll100_p)     = { "gpll_200m", "xin24m", "cpll_100m" };
0283 PNAME(xin24m_32k_p)         = { "xin24m", "clk_rtc_32k" };
0284 PNAME(cpll500_gpll400_gpll300_xin24m_p) = { "cpll_500m", "gpll_400m", "gpll_300m", "xin24m" };
0285 PNAME(gpll400_gpll300_gpll200_xin24m_p) = { "gpll_400m", "gpll_300m", "gpll_200m", "xin24m" };
0286 PNAME(xin24m_cpll100_p)         = { "xin24m", "cpll_100m" };
0287 PNAME(ppll_usb480m_cpll_gpll_p)     = { "ppll", "usb480m", "cpll", "gpll"};
0288 PNAME(clk_usbphy0_ref_p)        = { "clk_ref24m", "xin_osc0_usbphy0_g" };
0289 PNAME(clk_usbphy1_ref_p)        = { "clk_ref24m", "xin_osc0_usbphy1_g" };
0290 PNAME(clk_mipidsiphy0_ref_p)        = { "clk_ref24m", "xin_osc0_mipidsiphy0_g" };
0291 PNAME(clk_mipidsiphy1_ref_p)        = { "clk_ref24m", "xin_osc0_mipidsiphy1_g" };
0292 PNAME(clk_wifi_p)           = { "clk_wifi_osc0", "clk_wifi_div" };
0293 PNAME(clk_pciephy0_ref_p)       = { "clk_pciephy0_osc0", "clk_pciephy0_div" };
0294 PNAME(clk_pciephy1_ref_p)       = { "clk_pciephy1_osc0", "clk_pciephy1_div" };
0295 PNAME(clk_pciephy2_ref_p)       = { "clk_pciephy2_osc0", "clk_pciephy2_div" };
0296 PNAME(mux_gmac0_p)          = { "clk_mac0_2top", "gmac0_clkin" };
0297 PNAME(mux_gmac0_rgmii_speed_p)      = { "clk_gmac0", "clk_gmac0", "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" };
0298 PNAME(mux_gmac0_rmii_speed_p)       = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" };
0299 PNAME(mux_gmac0_rx_tx_p)        = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", "clk_gmac0_xpcs_mii" };
0300 PNAME(mux_gmac1_p)          = { "clk_mac1_2top", "gmac1_clkin" };
0301 PNAME(mux_gmac1_rgmii_speed_p)      = { "clk_gmac1", "clk_gmac1", "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" };
0302 PNAME(mux_gmac1_rmii_speed_p)       = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" };
0303 PNAME(mux_gmac1_rx_tx_p)        = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", "clk_gmac1_xpcs_mii" };
0304 PNAME(clk_hdmi_ref_p)           = { "hpll", "hpll_ph0" };
0305 PNAME(clk_pdpmu_p)          = { "ppll", "gpll" };
0306 PNAME(clk_mac_2top_p)           = { "cpll_125m", "cpll_50m", "cpll_25m", "ppll" };
0307 PNAME(clk_pwm0_p)           = { "xin24m", "clk_pdpmu" };
0308 PNAME(aclk_rkvdec_pre_p)        = { "gpll", "cpll" };
0309 PNAME(clk_rkvdec_core_p)        = { "gpll", "cpll", "dummy_npll", "dummy_vpll" };
0310
0311 static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = {
0312     [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll",  mux_pll_p,
0313              0, RK3568_PMU_PLL_CON(0),
0314              RK3568_PMU_MODE_CON0, 0, 4, 0, rk3568_pll_rates),
0315     [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll",  mux_pll_p,
0316              0, RK3568_PMU_PLL_CON(16),
0317              RK3568_PMU_MODE_CON0, 2, 7, 0, rk3568_pll_rates),
0318 };
0319
0320 static struct rockchip_pll_clock rk3568_pll_clks[] __initdata = {
0321     [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
0322              0, RK3568_PLL_CON(0),
0323              RK3568_MODE_CON0, 0, 0, 0, rk3568_pll_rates),
0324     [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
0325              0, RK3568_PLL_CON(8),
0326              RK3568_MODE_CON0, 2, 1, 0, NULL),
0327     [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
0328              0, RK3568_PLL_CON(24),
0329              RK3568_MODE_CON0, 4, 2, 0, rk3568_pll_rates),
0330     [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
0331              0, RK3568_PLL_CON(16),
0332              RK3568_MODE_CON0, 6, 3, 0, rk3568_pll_rates),
0333     [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
0334              0, RK3568_PLL_CON(32),
0335              RK3568_MODE_CON0, 10, 5, 0, rk3568_pll_rates),
0336     [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p,
0337              0, RK3568_PLL_CON(40),
0338              RK3568_MODE_CON0, 12, 6, 0, rk3568_pll_rates),
0339 };
0340
0341 #define MFLAGS CLK_MUX_HIWORD_MASK
0342 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
0343 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
0344
0345 static struct rockchip_clk_branch rk3568_i2s0_8ch_tx_fracmux __initdata =
0346     MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
0347             RK3568_CLKSEL_CON(11), 10, 2, MFLAGS);
0348
0349 static struct rockchip_clk_branch rk3568_i2s0_8ch_rx_fracmux __initdata =
0350     MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
0351             RK3568_CLKSEL_CON(13), 10, 2, MFLAGS);
0352
0353 static struct rockchip_clk_branch rk3568_i2s1_8ch_tx_fracmux __initdata =
0354     MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
0355             RK3568_CLKSEL_CON(15), 10, 2, MFLAGS);
0356
0357 static struct rockchip_clk_branch rk3568_i2s1_8ch_rx_fracmux __initdata =
0358     MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
0359             RK3568_CLKSEL_CON(17), 10, 2, MFLAGS);
0360
0361 static struct rockchip_clk_branch rk3568_i2s2_2ch_fracmux __initdata =
0362     MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT,
0363             RK3568_CLKSEL_CON(19), 10, 2, MFLAGS);
0364
0365 static struct rockchip_clk_branch rk3568_i2s3_2ch_tx_fracmux __initdata =
0366     MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT,
0367             RK3568_CLKSEL_CON(21), 10, 2, MFLAGS);
0368
0369 static struct rockchip_clk_branch rk3568_i2s3_2ch_rx_fracmux __initdata =
0370     MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT,
0371             RK3568_CLKSEL_CON(83), 10, 2, MFLAGS);
0372
0373 static struct rockchip_clk_branch rk3568_spdif_8ch_fracmux __initdata =
0374     MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT,
0375             RK3568_CLKSEL_CON(23), 15, 1, MFLAGS);
0376
0377 static struct rockchip_clk_branch rk3568_audpwm_fracmux __initdata =
0378     MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT,
0379             RK3568_CLKSEL_CON(25), 15, 1, MFLAGS);
0380
0381 static struct rockchip_clk_branch rk3568_uart1_fracmux __initdata =
0382     MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT,
0383             RK3568_CLKSEL_CON(52), 12, 2, MFLAGS);
0384
0385 static struct rockchip_clk_branch rk3568_uart2_fracmux __initdata =
0386     MUX(0, "sclk_uart2_mux", sclk_uart2_p, CLK_SET_RATE_PARENT,
0387             RK3568_CLKSEL_CON(54), 12, 2, MFLAGS);
0388
0389 static struct rockchip_clk_branch rk3568_uart3_fracmux __initdata =
0390     MUX(0, "sclk_uart3_mux", sclk_uart3_p, CLK_SET_RATE_PARENT,
0391             RK3568_CLKSEL_CON(56), 12, 2, MFLAGS);
0392
0393 static struct rockchip_clk_branch rk3568_uart4_fracmux __initdata =
0394     MUX(0, "sclk_uart4_mux", sclk_uart4_p, CLK_SET_RATE_PARENT,
0395             RK3568_CLKSEL_CON(58), 12, 2, MFLAGS);
0396
0397 static struct rockchip_clk_branch rk3568_uart5_fracmux __initdata =
0398     MUX(0, "sclk_uart5_mux", sclk_uart5_p, CLK_SET_RATE_PARENT,
0399             RK3568_CLKSEL_CON(60), 12, 2, MFLAGS);
0400
0401 static struct rockchip_clk_branch rk3568_uart6_fracmux __initdata =
0402     MUX(0, "sclk_uart6_mux", sclk_uart6_p, CLK_SET_RATE_PARENT,
0403             RK3568_CLKSEL_CON(62), 12, 2, MFLAGS);
0404
0405 static struct rockchip_clk_branch rk3568_uart7_fracmux __initdata =
0406     MUX(0, "sclk_uart7_mux", sclk_uart7_p, CLK_SET_RATE_PARENT,
0407             RK3568_CLKSEL_CON(64), 12, 2, MFLAGS);
0408
0409 static struct rockchip_clk_branch rk3568_uart8_fracmux __initdata =
0410     MUX(0, "sclk_uart8_mux", sclk_uart8_p, CLK_SET_RATE_PARENT,
0411             RK3568_CLKSEL_CON(66), 12, 2, MFLAGS);
0412
0413 static struct rockchip_clk_branch rk3568_uart9_fracmux __initdata =
0414     MUX(0, "sclk_uart9_mux", sclk_uart9_p, CLK_SET_RATE_PARENT,
0415             RK3568_CLKSEL_CON(68), 12, 2, MFLAGS);
0416
0417 static struct rockchip_clk_branch rk3568_uart0_fracmux __initdata =
0418     MUX(0, "sclk_uart0_mux", sclk_uart0_p, CLK_SET_RATE_PARENT,
0419             RK3568_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
0420
0421 static struct rockchip_clk_branch rk3568_rtc32k_pmu_fracmux __initdata =
0422     MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0423             RK3568_PMU_CLKSEL_CON(0), 6, 2, MFLAGS);
0424
0425 static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
0426     /*
0427      * Clock-Architecture Diagram 1
0428      */
0429      /* SRC_CLK */
0430     COMPOSITE_NOMUX(0, "gpll_400m", "gpll", CLK_IGNORE_UNUSED,
0431             RK3568_CLKSEL_CON(75), 0, 5, DFLAGS,
0432             RK3568_CLKGATE_CON(35), 0, GFLAGS),
0433     COMPOSITE_NOMUX(0, "gpll_300m", "gpll", CLK_IGNORE_UNUSED,
0434             RK3568_CLKSEL_CON(75), 8, 5, DFLAGS,
0435             RK3568_CLKGATE_CON(35), 1, GFLAGS),
0436     COMPOSITE_NOMUX(0, "gpll_200m", "gpll", CLK_IGNORE_UNUSED,
0437             RK3568_CLKSEL_CON(76), 0, 5, DFLAGS,
0438             RK3568_CLKGATE_CON(35), 2, GFLAGS),
0439     COMPOSITE_NOMUX(0, "gpll_150m", "gpll", CLK_IGNORE_UNUSED,
0440             RK3568_CLKSEL_CON(76), 8, 5, DFLAGS,
0441             RK3568_CLKGATE_CON(35), 3, GFLAGS),
0442     COMPOSITE_NOMUX(0, "gpll_100m", "gpll", CLK_IGNORE_UNUSED,
0443             RK3568_CLKSEL_CON(77), 0, 5, DFLAGS,
0444             RK3568_CLKGATE_CON(35), 4, GFLAGS),
0445     COMPOSITE_NOMUX(0, "gpll_75m", "gpll", CLK_IGNORE_UNUSED,
0446             RK3568_CLKSEL_CON(77), 8, 5, DFLAGS,
0447             RK3568_CLKGATE_CON(35), 5, GFLAGS),
0448     COMPOSITE_NOMUX(0, "gpll_20m", "gpll", CLK_IGNORE_UNUSED,
0449             RK3568_CLKSEL_CON(78), 0, 6, DFLAGS,
0450             RK3568_CLKGATE_CON(35), 6, GFLAGS),
0451     COMPOSITE_NOMUX(CPLL_500M, "cpll_500m", "cpll", CLK_IGNORE_UNUSED,
0452             RK3568_CLKSEL_CON(78), 8, 5, DFLAGS,
0453             RK3568_CLKGATE_CON(35), 7, GFLAGS),
0454     COMPOSITE_NOMUX(CPLL_333M, "cpll_333m", "cpll", CLK_IGNORE_UNUSED,
0455             RK3568_CLKSEL_CON(79), 0, 5, DFLAGS,
0456             RK3568_CLKGATE_CON(35), 8, GFLAGS),
0457     COMPOSITE_NOMUX(CPLL_250M, "cpll_250m", "cpll", CLK_IGNORE_UNUSED,
0458             RK3568_CLKSEL_CON(79), 8, 5, DFLAGS,
0459             RK3568_CLKGATE_CON(35), 9, GFLAGS),
0460     COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED,
0461             RK3568_CLKSEL_CON(80), 0, 5, DFLAGS,
0462             RK3568_CLKGATE_CON(35), 10, GFLAGS),
0463     COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED,
0464             RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
0465             RK3568_CLKGATE_CON(35), 11, GFLAGS),
0466     COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED,
0467             RK3568_CLKSEL_CON(80), 8, 5, DFLAGS,
0468             RK3568_CLKGATE_CON(35), 12, GFLAGS),
0469     COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED,
0470             RK3568_CLKSEL_CON(81), 0, 5, DFLAGS,
0471             RK3568_CLKGATE_CON(35), 13, GFLAGS),
0472     COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED,
0473             RK3568_CLKSEL_CON(81), 8, 6, DFLAGS,
0474             RK3568_CLKGATE_CON(35), 14, GFLAGS),
0475     COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED,
0476             RK3568_CLKSEL_CON(82), 8, 6, DFLAGS,
0477             RK3568_CLKGATE_CON(35), 15, GFLAGS),
0478     FACTOR(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 0, 1, 2),
0479     FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
0480     MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
0481             RK3568_MODE_CON0, 14, 2, MFLAGS),
0482
0483     /* PD_CORE */
0484     COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED,
0485             RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
0486             RK3568_CLKGATE_CON(0), 5, GFLAGS),
0487     COMPOSITE_NODIV(0, "sclk_core", sclk_core_pre_p, CLK_IGNORE_UNUSED,
0488             RK3568_CLKSEL_CON(2), 15, 1, MFLAGS,
0489             RK3568_CLKGATE_CON(0), 7, GFLAGS),
0490
0491     COMPOSITE_NOMUX(0, "atclk_core", "armclk", CLK_IGNORE_UNUSED,
0492             RK3568_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
0493             RK3568_CLKGATE_CON(0), 8, GFLAGS),
0494     COMPOSITE_NOMUX(0, "gicclk_core", "armclk", CLK_IGNORE_UNUSED,
0495             RK3568_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
0496             RK3568_CLKGATE_CON(0), 9, GFLAGS),
0497     COMPOSITE_NOMUX(0, "pclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
0498             RK3568_CLKSEL_CON(4), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
0499             RK3568_CLKGATE_CON(0), 10, GFLAGS),
0500     COMPOSITE_NOMUX(0, "periphclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
0501             RK3568_CLKSEL_CON(4), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
0502             RK3568_CLKGATE_CON(0), 11, GFLAGS),
0503     COMPOSITE_NOMUX(0, "tsclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED,
0504             RK3568_CLKSEL_CON(5), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
0505             RK3568_CLKGATE_CON(0), 14, GFLAGS),
0506     COMPOSITE_NOMUX(0, "cntclk_core", "periphclk_core_pre", CLK_IGNORE_UNUSED,
0507             RK3568_CLKSEL_CON(5), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
0508             RK3568_CLKGATE_CON(0), 15, GFLAGS),
0509     COMPOSITE_NOMUX(0, "aclk_core", "sclk_core", CLK_IGNORE_UNUSED,
0510             RK3568_CLKSEL_CON(5), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
0511             RK3568_CLKGATE_CON(1), 0, GFLAGS),
0512
0513     COMPOSITE_NODIV(ACLK_CORE_NIU2BUS, "aclk_core_niu2bus", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
0514             RK3568_CLKSEL_CON(5), 14, 2, MFLAGS,
0515             RK3568_CLKGATE_CON(1), 2, GFLAGS),
0516
0517     GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 0,
0518             RK3568_CLKGATE_CON(1), 10, GFLAGS),
0519     GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 0,
0520             RK3568_CLKGATE_CON(1), 11, GFLAGS),
0521     GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", CLK_IGNORE_UNUSED,
0522             RK3568_CLKGATE_CON(1), 12, GFLAGS),
0523     GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0,
0524             RK3568_CLKGATE_CON(1), 9, GFLAGS),
0525
0526     /* PD_GPU */
0527     COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0,
0528             RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
0529             RK3568_CLKGATE_CON(2), 0, GFLAGS),
0530     MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux", clk_gpu_pre_mux_p, CLK_SET_RATE_PARENT,
0531             RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY),
0532     DIV(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre_mux", 0,
0533             RK3568_CLKSEL_CON(6), 8, 2, DFLAGS),
0534     DIV(PCLK_GPU_PRE, "pclk_gpu_pre", "clk_gpu_pre_mux", 0,
0535             RK3568_CLKSEL_CON(6), 12, 4, DFLAGS),
0536     GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_mux", 0,
0537             RK3568_CLKGATE_CON(2), 3, GFLAGS),
0538
0539     GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 0,
0540             RK3568_CLKGATE_CON(2), 6, GFLAGS),
0541     GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
0542             RK3568_CLKGATE_CON(2), 7, GFLAGS),
0543     GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 0,
0544             RK3568_CLKGATE_CON(2), 8, GFLAGS),
0545     GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", CLK_IGNORE_UNUSED,
0546             RK3568_CLKGATE_CON(2), 9, GFLAGS),
0547
0548     /* PD_NPU */
0549     COMPOSITE(CLK_NPU_SRC, "clk_npu_src", npll_gpll_p, 0,
0550             RK3568_CLKSEL_CON(7), 6, 1, MFLAGS, 0, 4, DFLAGS,
0551             RK3568_CLKGATE_CON(3), 0, GFLAGS),
0552     MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
0553             RK3568_CLKSEL_CON(7), 8, 1, MFLAGS),
0554     MUX(CLK_NPU, "clk_npu", clk_npu_p, CLK_SET_RATE_PARENT,
0555             RK3568_CLKSEL_CON(7), 15, 1, MFLAGS),
0556     COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu", 0,
0557             RK3568_CLKSEL_CON(8), 0, 4, DFLAGS,
0558             RK3568_CLKGATE_CON(3), 2, GFLAGS),
0559     COMPOSITE_NOMUX(PCLK_NPU_PRE, "pclk_npu_pre", "clk_npu", 0,
0560             RK3568_CLKSEL_CON(8), 4, 4, DFLAGS,
0561             RK3568_CLKGATE_CON(3), 3, GFLAGS),
0562     GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 0,
0563             RK3568_CLKGATE_CON(3), 4, GFLAGS),
0564     GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0,
0565             RK3568_CLKGATE_CON(3), 7, GFLAGS),
0566     GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0,
0567             RK3568_CLKGATE_CON(3), 8, GFLAGS),
0568
0569     GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 0,
0570             RK3568_CLKGATE_CON(3), 9, GFLAGS),
0571     GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
0572             RK3568_CLKGATE_CON(3), 10, GFLAGS),
0573     GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft", 0,
0574             RK3568_CLKGATE_CON(3), 11, GFLAGS),
0575     GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", CLK_IGNORE_UNUSED,
0576             RK3568_CLKGATE_CON(3), 12, GFLAGS),
0577
0578     /* PD_DDR */
0579     COMPOSITE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", dpll_gpll_cpll_p, CLK_IGNORE_UNUSED,
0580             RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
0581             RK3568_CLKGATE_CON(4), 0, GFLAGS),
0582     MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT,
0583             RK3568_CLKSEL_CON(9), 15, 1, MFLAGS),
0584
0585     COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED,
0586             RK3568_CLKSEL_CON(10), 0, 2, DFLAGS,
0587             RK3568_CLKGATE_CON(4), 2, GFLAGS),
0588     GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
0589             RK3568_CLKGATE_CON(4), 15, GFLAGS),
0590
0591     /* PD_GIC_AUDIO */
0592     COMPOSITE_NODIV(ACLK_GIC_AUDIO, "aclk_gic_audio", gpll200_gpll150_gpll100_xin24m_p, CLK_IGNORE_UNUSED,
0593             RK3568_CLKSEL_CON(10), 8, 2, MFLAGS,
0594             RK3568_CLKGATE_CON(5), 0, GFLAGS),
0595     COMPOSITE_NODIV(HCLK_GIC_AUDIO, "hclk_gic_audio", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
0596             RK3568_CLKSEL_CON(10), 10, 2, MFLAGS,
0597             RK3568_CLKGATE_CON(5), 1, GFLAGS),
0598     GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 0,
0599             RK3568_CLKGATE_CON(5), 8, GFLAGS),
0600     COMPOSITE_NODIV(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", gpll100_gpll75_gpll50_p, 0,
0601             RK3568_CLKSEL_CON(10), 12, 2, MFLAGS,
0602             RK3568_CLKGATE_CON(5), 9, GFLAGS),
0603     GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", CLK_IGNORE_UNUSED,
0604             RK3568_CLKGATE_CON(5), 4, GFLAGS),
0605     GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", CLK_IGNORE_UNUSED,
0606             RK3568_CLKGATE_CON(5), 7, GFLAGS),
0607     GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 0,
0608             RK3568_CLKGATE_CON(5), 10, GFLAGS),
0609     GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 0,
0610             RK3568_CLKGATE_CON(5), 11, GFLAGS),
0611     GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 0,
0612             RK3568_CLKGATE_CON(5), 12, GFLAGS),
0613     GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 0,
0614             RK3568_CLKGATE_CON(5), 13, GFLAGS),
0615
0616     COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_cpll_npll_p, 0,
0617             RK3568_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 7, DFLAGS,
0618             RK3568_CLKGATE_CON(6), 0, GFLAGS),
0619     COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
0620             RK3568_CLKSEL_CON(12), 0,
0621             RK3568_CLKGATE_CON(6), 1, GFLAGS,
0622             &rk3568_i2s0_8ch_tx_fracmux),
0623     GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
0624             RK3568_CLKGATE_CON(6), 2, GFLAGS),
0625     COMPOSITE_NODIV(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", i2s0_mclkout_tx_p, CLK_SET_RATE_PARENT,
0626             RK3568_CLKSEL_CON(11), 15, 1, MFLAGS,
0627             RK3568_CLKGATE_CON(6), 3, GFLAGS),
0628
0629     COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_cpll_npll_p, 0,
0630             RK3568_CLKSEL_CON(13), 8, 2, MFLAGS, 0, 7, DFLAGS,
0631             RK3568_CLKGATE_CON(6), 4, GFLAGS),
0632     COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
0633             RK3568_CLKSEL_CON(14), 0,
0634             RK3568_CLKGATE_CON(6), 5, GFLAGS,
0635             &rk3568_i2s0_8ch_rx_fracmux),
0636     GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
0637             RK3568_CLKGATE_CON(6), 6, GFLAGS),
0638     COMPOSITE_NODIV(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", i2s0_mclkout_rx_p, CLK_SET_RATE_PARENT,
0639             RK3568_CLKSEL_CON(13), 15, 1, MFLAGS,
0640             RK3568_CLKGATE_CON(6), 7, GFLAGS),
0641
0642     COMPOSITE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", gpll_cpll_npll_p, 0,
0643             RK3568_CLKSEL_CON(15), 8, 2, MFLAGS, 0, 7, DFLAGS,
0644             RK3568_CLKGATE_CON(6), 8, GFLAGS),
0645     COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
0646             RK3568_CLKSEL_CON(16), 0,
0647             RK3568_CLKGATE_CON(6), 9, GFLAGS,
0648             &rk3568_i2s1_8ch_tx_fracmux),
0649     GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0,
0650             RK3568_CLKGATE_CON(6), 10, GFLAGS),
0651     COMPOSITE_NODIV(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", i2s1_mclkout_tx_p, CLK_SET_RATE_PARENT,
0652             RK3568_CLKSEL_CON(15), 15, 1, MFLAGS,
0653             RK3568_CLKGATE_CON(6), 11, GFLAGS),
0654
0655     COMPOSITE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", gpll_cpll_npll_p, 0,
0656             RK3568_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 7, DFLAGS,
0657             RK3568_CLKGATE_CON(6), 12, GFLAGS),
0658     COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
0659             RK3568_CLKSEL_CON(18), 0,
0660             RK3568_CLKGATE_CON(6), 13, GFLAGS,
0661             &rk3568_i2s1_8ch_rx_fracmux),
0662     GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0,
0663             RK3568_CLKGATE_CON(6), 14, GFLAGS),
0664     COMPOSITE_NODIV(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", i2s1_mclkout_rx_p, CLK_SET_RATE_PARENT,
0665             RK3568_CLKSEL_CON(17), 15, 1, MFLAGS,
0666             RK3568_CLKGATE_CON(6), 15, GFLAGS),
0667
0668     COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_cpll_npll_p, 0,
0669             RK3568_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 7, DFLAGS,
0670             RK3568_CLKGATE_CON(7), 0, GFLAGS),
0671     COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
0672             RK3568_CLKSEL_CON(20), 0,
0673             RK3568_CLKGATE_CON(7), 1, GFLAGS,
0674             &rk3568_i2s2_2ch_fracmux),
0675     GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0,
0676             RK3568_CLKGATE_CON(7), 2, GFLAGS),
0677     COMPOSITE_NODIV(I2S2_MCLKOUT, "i2s2_mclkout", i2s2_mclkout_p, CLK_SET_RATE_PARENT,
0678             RK3568_CLKSEL_CON(19), 15, 1, MFLAGS,
0679             RK3568_CLKGATE_CON(7), 3, GFLAGS),
0680
0681     COMPOSITE(CLK_I2S3_2CH_TX_SRC, "clk_i2s3_2ch_tx_src", gpll_cpll_npll_p, 0,
0682             RK3568_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 7, DFLAGS,
0683             RK3568_CLKGATE_CON(7), 4, GFLAGS),
0684     COMPOSITE_FRACMUX(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_src", CLK_SET_RATE_PARENT,
0685             RK3568_CLKSEL_CON(22), 0,
0686             RK3568_CLKGATE_CON(7), 5, GFLAGS,
0687             &rk3568_i2s3_2ch_tx_fracmux),
0688     GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 0,
0689             RK3568_CLKGATE_CON(7), 6, GFLAGS),
0690     COMPOSITE_NODIV(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", i2s3_mclkout_tx_p, CLK_SET_RATE_PARENT,
0691             RK3568_CLKSEL_CON(21), 15, 1, MFLAGS,
0692             RK3568_CLKGATE_CON(7), 7, GFLAGS),
0693
0694     COMPOSITE(CLK_I2S3_2CH_RX_SRC, "clk_i2s3_2ch_rx_src", gpll_cpll_npll_p, 0,
0695             RK3568_CLKSEL_CON(83), 8, 2, MFLAGS, 0, 7, DFLAGS,
0696             RK3568_CLKGATE_CON(7), 8, GFLAGS),
0697     COMPOSITE_FRACMUX(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_src", CLK_SET_RATE_PARENT,
0698             RK3568_CLKSEL_CON(84), 0,
0699             RK3568_CLKGATE_CON(7), 9, GFLAGS,
0700             &rk3568_i2s3_2ch_rx_fracmux),
0701     GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 0,
0702             RK3568_CLKGATE_CON(7), 10, GFLAGS),
0703     COMPOSITE_NODIV(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", i2s3_mclkout_rx_p, CLK_SET_RATE_PARENT,
0704             RK3568_CLKSEL_CON(83), 15, 1, MFLAGS,
0705             RK3568_CLKGATE_CON(7), 11, GFLAGS),
0706
0707     GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0,
0708             RK3568_CLKGATE_CON(5), 14, GFLAGS),
0709     COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0,
0710             RK3568_CLKSEL_CON(23), 8, 2, MFLAGS,
0711             RK3568_CLKGATE_CON(5), 15, GFLAGS),
0712     GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 0,
0713             RK3568_CLKGATE_CON(7), 12, GFLAGS),
0714     GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 0,
0715             RK3568_CLKGATE_CON(7), 13, GFLAGS),
0716
0717     COMPOSITE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", cpll_gpll_p, 0,
0718             RK3568_CLKSEL_CON(23), 14, 1, MFLAGS, 0, 7, DFLAGS,
0719             RK3568_CLKGATE_CON(7), 14, GFLAGS),
0720     COMPOSITE_FRACMUX(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_src", CLK_SET_RATE_PARENT,
0721             RK3568_CLKSEL_CON(24), 0,
0722             RK3568_CLKGATE_CON(7), 15, GFLAGS,
0723             &rk3568_spdif_8ch_fracmux),
0724
0725     GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 0,
0726             RK3568_CLKGATE_CON(8), 0, GFLAGS),
0727     COMPOSITE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", gpll_cpll_p, 0,
0728             RK3568_CLKSEL_CON(25), 14, 1, MFLAGS, 0, 6, DFLAGS,
0729             RK3568_CLKGATE_CON(8), 1, GFLAGS),
0730     COMPOSITE_FRACMUX(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_src", CLK_SET_RATE_PARENT,
0731             RK3568_CLKSEL_CON(26), 0,
0732             RK3568_CLKGATE_CON(8), 2, GFLAGS,
0733             &rk3568_audpwm_fracmux),
0734
0735     GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 0,
0736             RK3568_CLKGATE_CON(8), 3, GFLAGS),
0737     COMPOSITE_NODIV(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", clk_i2c_p, 0,
0738             RK3568_CLKSEL_CON(23), 10, 2, MFLAGS,
0739             RK3568_CLKGATE_CON(8), 4, GFLAGS),
0740     GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 0,
0741             RK3568_CLKGATE_CON(8), 5, GFLAGS),
0742     GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 0,
0743             RK3568_CLKGATE_CON(8), 6, GFLAGS),
0744
0745     /* PD_SECURE_FLASH */
0746     COMPOSITE_NODIV(ACLK_SECURE_FLASH, "aclk_secure_flash", gpll200_gpll150_gpll100_xin24m_p, 0,
0747             RK3568_CLKSEL_CON(27), 0, 2, MFLAGS,
0748             RK3568_CLKGATE_CON(8), 7, GFLAGS),
0749     COMPOSITE_NODIV(HCLK_SECURE_FLASH, "hclk_secure_flash", gpll150_gpll100_gpll75_xin24m_p, 0,
0750             RK3568_CLKSEL_CON(27), 2, 2, MFLAGS,
0751             RK3568_CLKGATE_CON(8), 8, GFLAGS),
0752     GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 0,
0753             RK3568_CLKGATE_CON(8), 11, GFLAGS),
0754     GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 0,
0755             RK3568_CLKGATE_CON(8), 12, GFLAGS),
0756     COMPOSITE_NODIV(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", gpll200_gpll150_gpll100_p, 0,
0757             RK3568_CLKSEL_CON(27), 4, 2, MFLAGS,
0758             RK3568_CLKGATE_CON(8), 13, GFLAGS),
0759     COMPOSITE_NODIV(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", gpll300_gpll200_gpll100_p, 0,
0760             RK3568_CLKSEL_CON(27), 6, 2, MFLAGS,
0761             RK3568_CLKGATE_CON(8), 14, GFLAGS),
0762     GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 0,
0763             RK3568_CLKGATE_CON(8), 15, GFLAGS),
0764     GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED,
0765             RK3568_CLKGATE_CON(9), 10, GFLAGS),
0766     GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", CLK_IGNORE_UNUSED,
0767             RK3568_CLKGATE_CON(9), 11, GFLAGS),
0768     GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 0,
0769             RK3568_CLKGATE_CON(26), 9, GFLAGS),
0770     GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 0,
0771             RK3568_CLKGATE_CON(26), 10, GFLAGS),
0772     GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 0,
0773             RK3568_CLKGATE_CON(26), 11, GFLAGS),
0774     GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0,
0775             RK3568_CLKGATE_CON(9), 0, GFLAGS),
0776     COMPOSITE_NODIV(NCLK_NANDC, "nclk_nandc", clk_nandc_p, 0,
0777             RK3568_CLKSEL_CON(28), 0, 2, MFLAGS,
0778             RK3568_CLKGATE_CON(9), 1, GFLAGS),
0779     GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 0,
0780             RK3568_CLKGATE_CON(9), 2, GFLAGS),
0781     GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 0,
0782             RK3568_CLKGATE_CON(9), 3, GFLAGS),
0783     COMPOSITE_NODIV(SCLK_SFC, "sclk_sfc", sclk_sfc_p, 0,
0784             RK3568_CLKSEL_CON(28), 4, 3, MFLAGS,
0785             RK3568_CLKGATE_CON(9), 4, GFLAGS),
0786     GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 0,
0787             RK3568_CLKGATE_CON(9), 5, GFLAGS),
0788     GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 0,
0789             RK3568_CLKGATE_CON(9), 6, GFLAGS),
0790     COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", gpll200_gpll150_cpll125_p, 0,
0791             RK3568_CLKSEL_CON(28), 8, 2, MFLAGS,
0792             RK3568_CLKGATE_CON(9), 7, GFLAGS),
0793     COMPOSITE_NODIV(CCLK_EMMC, "cclk_emmc", cclk_emmc_p, 0,
0794             RK3568_CLKSEL_CON(28), 12, 3, MFLAGS,
0795             RK3568_CLKGATE_CON(9), 8, GFLAGS),
0796     GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
0797             RK3568_CLKGATE_CON(9), 9, GFLAGS),
0798     MMC(SCLK_EMMC_DRV, "emmc_drv", "cclk_emmc", RK3568_EMMC_CON0, 1),
0799     MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "cclk_emmc", RK3568_EMMC_CON1, 1),
0800
0801     /* PD_PIPE */
0802     COMPOSITE_NODIV(ACLK_PIPE, "aclk_pipe", aclk_pipe_p, 0,
0803             RK3568_CLKSEL_CON(29), 0, 2, MFLAGS,
0804             RK3568_CLKGATE_CON(10), 0, GFLAGS),
0805     COMPOSITE_NOMUX(PCLK_PIPE, "pclk_pipe", "aclk_pipe", 0,
0806             RK3568_CLKSEL_CON(29), 4, 4, DFLAGS,
0807             RK3568_CLKGATE_CON(10), 1, GFLAGS),
0808     GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 0,
0809             RK3568_CLKGATE_CON(12), 0, GFLAGS),
0810     GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 0,
0811             RK3568_CLKGATE_CON(12), 1, GFLAGS),
0812     GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 0,
0813             RK3568_CLKGATE_CON(12), 2, GFLAGS),
0814     GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 0,
0815             RK3568_CLKGATE_CON(12), 3, GFLAGS),
0816     GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,
0817             RK3568_CLKGATE_CON(12), 4, GFLAGS),
0818     GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0,
0819             RK3568_CLKGATE_CON(12), 8, GFLAGS),
0820     GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0,
0821             RK3568_CLKGATE_CON(12), 9, GFLAGS),
0822     GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 0,
0823             RK3568_CLKGATE_CON(12), 10, GFLAGS),
0824     GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 0,
0825             RK3568_CLKGATE_CON(12), 11, GFLAGS),
0826     GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,
0827             RK3568_CLKGATE_CON(12), 12, GFLAGS),
0828     GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0,
0829             RK3568_CLKGATE_CON(13), 0, GFLAGS),
0830     GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0,
0831             RK3568_CLKGATE_CON(13), 1, GFLAGS),
0832     GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 0,
0833             RK3568_CLKGATE_CON(13), 2, GFLAGS),
0834     GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 0,
0835             RK3568_CLKGATE_CON(13), 3, GFLAGS),
0836     GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,
0837             RK3568_CLKGATE_CON(13), 4, GFLAGS),
0838     GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0,
0839             RK3568_CLKGATE_CON(11), 0, GFLAGS),
0840     GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,
0841             RK3568_CLKGATE_CON(11), 1, GFLAGS),
0842     GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "cpll_50m", 0,
0843             RK3568_CLKGATE_CON(11), 2, GFLAGS),
0844     GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 0,
0845             RK3568_CLKGATE_CON(11), 4, GFLAGS),
0846     GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "gpll_20m", 0,
0847             RK3568_CLKGATE_CON(11), 5, GFLAGS),
0848     GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "cpll_50m", 0,
0849             RK3568_CLKGATE_CON(11), 6, GFLAGS),
0850     GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 0,
0851             RK3568_CLKGATE_CON(11), 8, GFLAGS),
0852     GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "gpll_20m", 0,
0853             RK3568_CLKGATE_CON(11), 9, GFLAGS),
0854     GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "cpll_50m", 0,
0855             RK3568_CLKGATE_CON(11), 10, GFLAGS),
0856     GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 0,
0857             RK3568_CLKGATE_CON(10), 8, GFLAGS),
0858     GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
0859             RK3568_CLKGATE_CON(10), 9, GFLAGS),
0860     COMPOSITE_NODIV(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", xin24m_32k_p, 0,
0861             RK3568_CLKSEL_CON(29), 8, 1, MFLAGS,
0862             RK3568_CLKGATE_CON(10), 10, GFLAGS),
0863     GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 0,
0864             RK3568_CLKGATE_CON(10), 12, GFLAGS),
0865     GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
0866             RK3568_CLKGATE_CON(10), 13, GFLAGS),
0867     COMPOSITE_NODIV(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", xin24m_32k_p, 0,
0868             RK3568_CLKSEL_CON(29), 9, 1, MFLAGS,
0869             RK3568_CLKGATE_CON(10), 14, GFLAGS),
0870     COMPOSITE_NODIV(CLK_XPCS_EEE, "clk_xpcs_eee", gpll200_cpll125_p, 0,
0871             RK3568_CLKSEL_CON(29), 13, 1, MFLAGS,
0872             RK3568_CLKGATE_CON(10), 4, GFLAGS),
0873     GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 0,
0874             RK3568_CLKGATE_CON(13), 6, GFLAGS),
0875
0876     /* PD_PHP */
0877     COMPOSITE_NODIV(ACLK_PHP, "aclk_php", gpll300_gpll200_gpll100_xin24m_p, 0,
0878             RK3568_CLKSEL_CON(30), 0, 2, MFLAGS,
0879             RK3568_CLKGATE_CON(14), 8, GFLAGS),
0880     COMPOSITE_NODIV(HCLK_PHP, "hclk_php", gpll150_gpll100_gpll75_xin24m_p, 0,
0881             RK3568_CLKSEL_CON(30), 2, 2, MFLAGS,
0882             RK3568_CLKGATE_CON(14), 9, GFLAGS),
0883     COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0,
0884             RK3568_CLKSEL_CON(30), 4, 4, DFLAGS,
0885             RK3568_CLKGATE_CON(14), 10, GFLAGS),
0886     GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 0,
0887             RK3568_CLKGATE_CON(15), 0, GFLAGS),
0888     COMPOSITE_NODIV(CLK_SDMMC0, "clk_sdmmc0", clk_sdmmc_p, 0,
0889             RK3568_CLKSEL_CON(30), 8, 3, MFLAGS,
0890             RK3568_CLKGATE_CON(15), 1, GFLAGS),
0891     MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "clk_sdmmc0", RK3568_SDMMC0_CON0, 1),
0892     MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "clk_sdmmc0", RK3568_SDMMC0_CON1, 1),
0893
0894     GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 0,
0895             RK3568_CLKGATE_CON(15), 2, GFLAGS),
0896     COMPOSITE_NODIV(CLK_SDMMC1, "clk_sdmmc1", clk_sdmmc_p, 0,
0897             RK3568_CLKSEL_CON(30), 12, 3, MFLAGS,
0898             RK3568_CLKGATE_CON(15), 3, GFLAGS),
0899     MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "clk_sdmmc1", RK3568_SDMMC1_CON0, 1),
0900     MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "clk_sdmmc1", RK3568_SDMMC1_CON1, 1),
0901
0902     GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 0,
0903             RK3568_CLKGATE_CON(15), 5, GFLAGS),
0904     GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 0,
0905             RK3568_CLKGATE_CON(15), 6, GFLAGS),
0906     COMPOSITE_NODIV(CLK_MAC0_2TOP, "clk_mac0_2top", clk_mac_2top_p, 0,
0907             RK3568_CLKSEL_CON(31), 8, 2, MFLAGS,
0908             RK3568_CLKGATE_CON(15), 7, GFLAGS),
0909     COMPOSITE_NODIV(CLK_MAC0_OUT, "clk_mac0_out", cpll125_cpll50_cpll25_xin24m_p, 0,
0910             RK3568_CLKSEL_CON(31), 14, 2, MFLAGS,
0911             RK3568_CLKGATE_CON(15), 8, GFLAGS),
0912     GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 0,
0913             RK3568_CLKGATE_CON(15), 12, GFLAGS),
0914     COMPOSITE_NODIV(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac_ptp_p, 0,
0915             RK3568_CLKSEL_CON(31), 12, 2, MFLAGS,
0916             RK3568_CLKGATE_CON(15), 4, GFLAGS),
0917     MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0918             RK3568_CLKSEL_CON(31), 2, 1, MFLAGS),
0919     FACTOR(0, "clk_gmac0_tx_div5", "clk_gmac0", 0, 1, 5),
0920     FACTOR(0, "clk_gmac0_tx_div50", "clk_gmac0", 0, 1, 50),
0921     FACTOR(0, "clk_gmac0_rx_div2", "clk_gmac0", 0, 1, 2),
0922     FACTOR(0, "clk_gmac0_rx_div20", "clk_gmac0", 0, 1, 20),
0923     MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", mux_gmac0_rgmii_speed_p, 0,
0924             RK3568_CLKSEL_CON(31), 4, 2, MFLAGS),
0925     MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", mux_gmac0_rmii_speed_p, 0,
0926             RK3568_CLKSEL_CON(31), 3, 1, MFLAGS),
0927     MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p,  CLK_SET_RATE_PARENT,
0928             RK3568_CLKSEL_CON(31), 0, 2, MFLAGS),
0929
0930     /* PD_USB */
0931     COMPOSITE_NODIV(ACLK_USB, "aclk_usb", gpll300_gpll200_gpll100_xin24m_p, 0,
0932             RK3568_CLKSEL_CON(32), 0, 2, MFLAGS,
0933             RK3568_CLKGATE_CON(16), 0, GFLAGS),
0934     COMPOSITE_NODIV(HCLK_USB, "hclk_usb", gpll150_gpll100_gpll75_xin24m_p, 0,
0935             RK3568_CLKSEL_CON(32), 2, 2, MFLAGS,
0936             RK3568_CLKGATE_CON(16), 1, GFLAGS),
0937     COMPOSITE_NOMUX(PCLK_USB, "pclk_usb", "aclk_usb", 0,
0938             RK3568_CLKSEL_CON(32), 4, 4, DFLAGS,
0939             RK3568_CLKGATE_CON(16), 2, GFLAGS),
0940     GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 0,
0941             RK3568_CLKGATE_CON(16), 12, GFLAGS),
0942     GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 0,
0943             RK3568_CLKGATE_CON(16), 13, GFLAGS),
0944     GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 0,
0945             RK3568_CLKGATE_CON(16), 14, GFLAGS),
0946     GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 0,
0947             RK3568_CLKGATE_CON(16), 15, GFLAGS),
0948     GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 0,
0949             RK3568_CLKGATE_CON(17), 0, GFLAGS),
0950     COMPOSITE_NODIV(CLK_SDMMC2, "clk_sdmmc2", clk_sdmmc_p, 0,
0951             RK3568_CLKSEL_CON(32), 8, 3, MFLAGS,
0952             RK3568_CLKGATE_CON(17), 1, GFLAGS),
0953     MMC(SCLK_SDMMC2_DRV, "sdmmc2_drv", "clk_sdmmc2", RK3568_SDMMC2_CON0, 1),
0954     MMC(SCLK_SDMMC2_SAMPLE, "sdmmc2_sample", "clk_sdmmc2", RK3568_SDMMC2_CON1, 1),
0955
0956     GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 0,
0957             RK3568_CLKGATE_CON(17), 3, GFLAGS),
0958     GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 0,
0959             RK3568_CLKGATE_CON(17), 4, GFLAGS),
0960     COMPOSITE_NODIV(CLK_MAC1_2TOP, "clk_mac1_2top", clk_mac_2top_p, 0,
0961             RK3568_CLKSEL_CON(33), 8, 2, MFLAGS,
0962             RK3568_CLKGATE_CON(17), 5, GFLAGS),
0963     COMPOSITE_NODIV(CLK_MAC1_OUT, "clk_mac1_out", cpll125_cpll50_cpll25_xin24m_p, 0,
0964             RK3568_CLKSEL_CON(33), 14, 2, MFLAGS,
0965             RK3568_CLKGATE_CON(17), 6, GFLAGS),
0966     GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 0,
0967             RK3568_CLKGATE_CON(17), 10, GFLAGS),
0968     COMPOSITE_NODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac_ptp_p, 0,
0969             RK3568_CLKSEL_CON(33), 12, 2, MFLAGS,
0970             RK3568_CLKGATE_CON(17), 2, GFLAGS),
0971     MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0972             RK3568_CLKSEL_CON(33), 2, 1, MFLAGS),
0973     FACTOR(0, "clk_gmac1_tx_div5", "clk_gmac1", 0, 1, 5),
0974     FACTOR(0, "clk_gmac1_tx_div50", "clk_gmac1", 0, 1, 50),
0975     FACTOR(0, "clk_gmac1_rx_div2", "clk_gmac1", 0, 1, 2),
0976     FACTOR(0, "clk_gmac1_rx_div20", "clk_gmac1", 0, 1, 20),
0977     MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", mux_gmac1_rgmii_speed_p, 0,
0978             RK3568_CLKSEL_CON(33), 4, 2, MFLAGS),
0979     MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", mux_gmac1_rmii_speed_p, 0,
0980             RK3568_CLKSEL_CON(33), 3, 1, MFLAGS),
0981     MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p,  CLK_SET_RATE_PARENT,
0982             RK3568_CLKSEL_CON(33), 0, 2, MFLAGS),
0983
0984     /* PD_PERI */
0985     COMPOSITE_NODIV(ACLK_PERIMID, "aclk_perimid", gpll300_gpll200_gpll100_xin24m_p, CLK_IGNORE_UNUSED,
0986             RK3568_CLKSEL_CON(10), 4, 2, MFLAGS,
0987             RK3568_CLKGATE_CON(14), 0, GFLAGS),
0988     COMPOSITE_NODIV(HCLK_PERIMID, "hclk_perimid", gpll150_gpll100_gpll75_xin24m_p, CLK_IGNORE_UNUSED,
0989             RK3568_CLKSEL_CON(10), 6, 2, MFLAGS,
0990             RK3568_CLKGATE_CON(14), 1, GFLAGS),
0991
0992     /* PD_VI */
0993     COMPOSITE_NODIV(ACLK_VI, "aclk_vi", gpll400_gpll300_gpll200_xin24m_p, 0,
0994             RK3568_CLKSEL_CON(34), 0, 2, MFLAGS,
0995             RK3568_CLKGATE_CON(18), 0, GFLAGS),
0996     COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi", 0,
0997             RK3568_CLKSEL_CON(34), 4, 4, DFLAGS,
0998             RK3568_CLKGATE_CON(18), 1, GFLAGS),
0999     COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi", 0,
1000             RK3568_CLKSEL_CON(34), 8, 4, DFLAGS,
1001             RK3568_CLKGATE_CON(18), 2, GFLAGS),
1002     GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 0,
1003             RK3568_CLKGATE_CON(18), 9, GFLAGS),
1004     GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0,
1005             RK3568_CLKGATE_CON(18), 10, GFLAGS),
1006     COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", cpll333_gpll300_gpll200_p, 0,
1007             RK3568_CLKSEL_CON(34), 14, 2, MFLAGS,
1008             RK3568_CLKGATE_CON(18), 11, GFLAGS),
1009     GATE(ICLK_VICAP_G, "iclk_vicap_g", "iclk_vicap", 0,
1010             RK3568_CLKGATE_CON(18), 13, GFLAGS),
1011     GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0,
1012             RK3568_CLKGATE_CON(19), 0, GFLAGS),
1013     GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0,
1014             RK3568_CLKGATE_CON(19), 1, GFLAGS),
1015     COMPOSITE(CLK_ISP, "clk_isp", cpll_gpll_hpll_p, 0,
1016             RK3568_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
1017             RK3568_CLKGATE_CON(19), 2, GFLAGS),
1018     GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 0,
1019             RK3568_CLKGATE_CON(19), 4, GFLAGS),
1020     COMPOSITE(CLK_CIF_OUT, "clk_cif_out", gpll_usb480m_xin24m_p, 0,
1021             RK3568_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 6, DFLAGS,
1022             RK3568_CLKGATE_CON(19), 8, GFLAGS),
1023     COMPOSITE(CLK_CAM0_OUT, "clk_cam0_out", gpll_usb480m_xin24m_p, 0,
1024             RK3568_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 6, DFLAGS,
1025             RK3568_CLKGATE_CON(19), 9, GFLAGS),
1026     COMPOSITE(CLK_CAM1_OUT, "clk_cam1_out", gpll_usb480m_xin24m_p, 0,
1027             RK3568_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 6, DFLAGS,
1028             RK3568_CLKGATE_CON(19), 10, GFLAGS),
1029
1030     /* PD_VO */
1031     COMPOSITE_NODIV(ACLK_VO, "aclk_vo", gpll300_cpll250_gpll100_xin24m_p, 0,
1032             RK3568_CLKSEL_CON(37), 0, 2, MFLAGS,
1033             RK3568_CLKGATE_CON(20), 0, GFLAGS),
1034     COMPOSITE_NOMUX(HCLK_VO, "hclk_vo", "aclk_vo", 0,
1035             RK3568_CLKSEL_CON(37), 8, 4, DFLAGS,
1036             RK3568_CLKGATE_CON(20), 1, GFLAGS),
1037     COMPOSITE_NOMUX(PCLK_VO, "pclk_vo", "aclk_vo", 0,
1038             RK3568_CLKSEL_CON(37), 12, 4, DFLAGS,
1039             RK3568_CLKGATE_CON(20), 2, GFLAGS),
1040     COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", cpll_gpll_hpll_vpll_p, 0,
1041             RK3568_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
1042             RK3568_CLKGATE_CON(20), 6, GFLAGS),
1043     GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0,
1044             RK3568_CLKGATE_CON(20), 8, GFLAGS),
1045     GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0,
1046             RK3568_CLKGATE_CON(20), 9, GFLAGS),
1047     COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
1048             RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS,
1049             RK3568_CLKGATE_CON(20), 10, GFLAGS),
1050     COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
1051             RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS,
1052             RK3568_CLKGATE_CON(20), 11, GFLAGS),
1053     COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
1054             RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS,
1055             RK3568_CLKGATE_CON(20), 12, GFLAGS),
1056     GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0,
1057             RK3568_CLKGATE_CON(20), 13, GFLAGS),
1058     GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0,
1059             RK3568_CLKGATE_CON(21), 0, GFLAGS),
1060     GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 0,
1061             RK3568_CLKGATE_CON(21), 1, GFLAGS),
1062     GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 0,
1063             RK3568_CLKGATE_CON(21), 2, GFLAGS),
1064     GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 0,
1065             RK3568_CLKGATE_CON(21), 3, GFLAGS),
1066     GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
1067             RK3568_CLKGATE_CON(21), 4, GFLAGS),
1068     GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 0,
1069             RK3568_CLKGATE_CON(21), 5, GFLAGS),
1070     GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 0,
1071             RK3568_CLKGATE_CON(21), 6, GFLAGS),
1072     GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 0,
1073             RK3568_CLKGATE_CON(21), 7, GFLAGS),
1074     GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 0,
1075             RK3568_CLKGATE_CON(21), 8, GFLAGS),
1076     COMPOSITE_NODIV(CLK_EDP_200M, "clk_edp_200m", gpll200_gpll150_cpll125_p, 0,
1077             RK3568_CLKSEL_CON(38), 8, 2, MFLAGS,
1078             RK3568_CLKGATE_CON(21), 9, GFLAGS),
1079
1080     /* PD_VPU */
1081     COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", gpll_cpll_p, 0,
1082             RK3568_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 5, DFLAGS,
1083             RK3568_CLKGATE_CON(22), 0, GFLAGS),
1084     COMPOSITE_NOMUX(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0,
1085             RK3568_CLKSEL_CON(42), 8, 4, DFLAGS,
1086             RK3568_CLKGATE_CON(22), 1, GFLAGS),
1087     GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
1088             RK3568_CLKGATE_CON(22), 4, GFLAGS),
1089     GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0,
1090             RK3568_CLKGATE_CON(22), 5, GFLAGS),
1091
1092     /* PD_RGA */
1093     COMPOSITE_NODIV(ACLK_RGA_PRE, "aclk_rga_pre", gpll300_cpll250_gpll100_xin24m_p, 0,
1094             RK3568_CLKSEL_CON(43), 0, 2, MFLAGS,
1095             RK3568_CLKGATE_CON(23), 0, GFLAGS),
1096     COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_pre", 0,
1097             RK3568_CLKSEL_CON(43), 8, 4, DFLAGS,
1098             RK3568_CLKGATE_CON(23), 1, GFLAGS),
1099     COMPOSITE_NOMUX(PCLK_RGA_PRE, "pclk_rga_pre", "aclk_rga_pre", 0,
1100             RK3568_CLKSEL_CON(43), 12, 4, DFLAGS,
1101             RK3568_CLKGATE_CON(22), 12, GFLAGS),
1102     GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
1103             RK3568_CLKGATE_CON(23), 4, GFLAGS),
1104     GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
1105             RK3568_CLKGATE_CON(23), 5, GFLAGS),
1106     COMPOSITE_NODIV(CLK_RGA_CORE, "clk_rga_core", gpll300_gpll200_gpll100_p, 0,
1107             RK3568_CLKSEL_CON(43), 2, 2, MFLAGS,
1108             RK3568_CLKGATE_CON(23), 6, GFLAGS),
1109     GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 0,
1110             RK3568_CLKGATE_CON(23), 7, GFLAGS),
1111     GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 0,
1112             RK3568_CLKGATE_CON(23), 8, GFLAGS),
1113     COMPOSITE_NODIV(CLK_IEP_CORE, "clk_iep_core", gpll300_gpll200_gpll100_p, 0,
1114             RK3568_CLKSEL_CON(43), 4, 2, MFLAGS,
1115             RK3568_CLKGATE_CON(23), 9, GFLAGS),
1116     GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 0, RK3568_CLKGATE_CON(23), 10, GFLAGS),
1117     COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", gpll400_cpll333_gpll200_p, 0,
1118             RK3568_CLKSEL_CON(43), 6, 2, MFLAGS,
1119             RK3568_CLKGATE_CON(23), 11, GFLAGS),
1120     GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 0,
1121             RK3568_CLKGATE_CON(23), 12, GFLAGS),
1122     GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0,
1123             RK3568_CLKGATE_CON(23), 13, GFLAGS),
1124     GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 0,
1125             RK3568_CLKGATE_CON(23), 14, GFLAGS),
1126     GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 0,
1127             RK3568_CLKGATE_CON(23), 15, GFLAGS),
1128     GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 0,
1129             RK3568_CLKGATE_CON(22), 14, GFLAGS),
1130     GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 0,
1131             RK3568_CLKGATE_CON(22), 15, GFLAGS),
1132
1133     /* PD_RKVENC */
1134     COMPOSITE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", gpll_cpll_npll_p, 0,
1135             RK3568_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
1136             RK3568_CLKGATE_CON(24), 0, GFLAGS),
1137     COMPOSITE_NOMUX(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0,
1138             RK3568_CLKSEL_CON(44), 8, 4, DFLAGS,
1139             RK3568_CLKGATE_CON(24), 1, GFLAGS),
1140     GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0,
1141             RK3568_CLKGATE_CON(24), 6, GFLAGS),
1142     GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0,
1143             RK3568_CLKGATE_CON(24), 7, GFLAGS),
1144     COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_npll_vpll_p, 0,
1145             RK3568_CLKSEL_CON(45), 14, 2, MFLAGS, 0, 5, DFLAGS,
1146             RK3568_CLKGATE_CON(24), 8, GFLAGS),
1147     COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", aclk_rkvdec_pre_p, CLK_SET_RATE_NO_REPARENT,
1148             RK3568_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS,
1149             RK3568_CLKGATE_CON(25), 0, GFLAGS),
1150     COMPOSITE_NOMUX(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0,
1151             RK3568_CLKSEL_CON(47), 8, 4, DFLAGS,
1152             RK3568_CLKGATE_CON(25), 1, GFLAGS),
1153     GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0,
1154             RK3568_CLKGATE_CON(25), 4, GFLAGS),
1155     GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0,
1156             RK3568_CLKGATE_CON(25), 5, GFLAGS),
1157     COMPOSITE(CLK_RKVDEC_CA, "clk_rkvdec_ca", gpll_cpll_npll_vpll_p, 0,
1158             RK3568_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1159             RK3568_CLKGATE_CON(25), 6, GFLAGS),
1160     COMPOSITE(CLK_RKVDEC_CORE, "clk_rkvdec_core", clk_rkvdec_core_p, CLK_SET_RATE_NO_REPARENT,
1161             RK3568_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS,
1162             RK3568_CLKGATE_CON(25), 7, GFLAGS),
1163     COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_npll_vpll_p, 0,
1164             RK3568_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
1165             RK3568_CLKGATE_CON(25), 8, GFLAGS),
1166
1167     /* PD_BUS */
1168     COMPOSITE_NODIV(ACLK_BUS, "aclk_bus", gpll200_gpll150_gpll100_xin24m_p, 0,
1169             RK3568_CLKSEL_CON(50), 0, 2, MFLAGS,
1170             RK3568_CLKGATE_CON(26), 0, GFLAGS),
1171     COMPOSITE_NODIV(PCLK_BUS, "pclk_bus", gpll100_gpll75_cpll50_xin24m_p, 0,
1172             RK3568_CLKSEL_CON(50), 4, 2, MFLAGS,
1173             RK3568_CLKGATE_CON(26), 1, GFLAGS),
1174     GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0,
1175             RK3568_CLKGATE_CON(26), 4, GFLAGS),
1176     COMPOSITE(CLK_TSADC_TSEN, "clk_tsadc_tsen", xin24m_gpll100_cpll100_p, 0,
1177             RK3568_CLKSEL_CON(51), 4, 2, MFLAGS, 0, 3, DFLAGS,
1178             RK3568_CLKGATE_CON(26), 5, GFLAGS),
1179     COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "clk_tsadc_tsen", 0,
1180             RK3568_CLKSEL_CON(51), 8, 7, DFLAGS,
1181             RK3568_CLKGATE_CON(26), 6, GFLAGS),
1182     GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0,
1183             RK3568_CLKGATE_CON(26), 7, GFLAGS),
1184     GATE(CLK_SARADC, "clk_saradc", "xin24m", 0,
1185             RK3568_CLKGATE_CON(26), 8, GFLAGS),
1186     GATE(PCLK_SCR, "pclk_scr", "pclk_bus", CLK_IGNORE_UNUSED,
1187             RK3568_CLKGATE_CON(26), 12, GFLAGS),
1188     GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 0,
1189             RK3568_CLKGATE_CON(26), 13, GFLAGS),
1190     GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
1191             RK3568_CLKGATE_CON(26), 14, GFLAGS),
1192     GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", CLK_IGNORE_UNUSED,
1193             RK3568_CLKGATE_CON(32), 13, GFLAGS),
1194     GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", CLK_IGNORE_UNUSED,
1195             RK3568_CLKGATE_CON(32), 14, GFLAGS),
1196     GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0,
1197             RK3568_CLKGATE_CON(32), 15, GFLAGS),
1198
1199     GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0,
1200             RK3568_CLKGATE_CON(27), 12, GFLAGS),
1201     COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_usb480m_p, 0,
1202             RK3568_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS,
1203             RK3568_CLKGATE_CON(27), 13, GFLAGS),
1204     COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
1205             RK3568_CLKSEL_CON(53), 0,
1206             RK3568_CLKGATE_CON(27), 14, GFLAGS,
1207             &rk3568_uart1_fracmux),
1208     GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
1209             RK3568_CLKGATE_CON(27), 15, GFLAGS),
1210
1211     GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0,
1212             RK3568_CLKGATE_CON(28), 0, GFLAGS),
1213     COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_usb480m_p, 0,
1214             RK3568_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS,
1215             RK3568_CLKGATE_CON(28), 1, GFLAGS),
1216     COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
1217             RK3568_CLKSEL_CON(55), 0,
1218             RK3568_CLKGATE_CON(28), 2, GFLAGS,
1219             &rk3568_uart2_fracmux),
1220     GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
1221             RK3568_CLKGATE_CON(28), 3, GFLAGS),
1222
1223     GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0,
1224             RK3568_CLKGATE_CON(28), 4, GFLAGS),
1225     COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_usb480m_p, 0,
1226             RK3568_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS,
1227             RK3568_CLKGATE_CON(28), 5, GFLAGS),
1228     COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
1229             RK3568_CLKSEL_CON(57), 0,
1230             RK3568_CLKGATE_CON(28), 6, GFLAGS,
1231             &rk3568_uart3_fracmux),
1232     GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
1233             RK3568_CLKGATE_CON(28), 7, GFLAGS),
1234
1235     GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0,
1236             RK3568_CLKGATE_CON(28), 8, GFLAGS),
1237     COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_usb480m_p, 0,
1238             RK3568_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS,
1239             RK3568_CLKGATE_CON(28), 9, GFLAGS),
1240     COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
1241             RK3568_CLKSEL_CON(59), 0,
1242             RK3568_CLKGATE_CON(28), 10, GFLAGS,
1243             &rk3568_uart4_fracmux),
1244     GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
1245             RK3568_CLKGATE_CON(28), 11, GFLAGS),
1246
1247     GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0,
1248             RK3568_CLKGATE_CON(28), 12, GFLAGS),
1249     COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_usb480m_p, 0,
1250             RK3568_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS,
1251             RK3568_CLKGATE_CON(28), 13, GFLAGS),
1252     COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
1253             RK3568_CLKSEL_CON(61), 0,
1254             RK3568_CLKGATE_CON(28), 14, GFLAGS,
1255             &rk3568_uart5_fracmux),
1256     GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
1257             RK3568_CLKGATE_CON(28), 15, GFLAGS),
1258
1259     GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 0,
1260             RK3568_CLKGATE_CON(29), 0, GFLAGS),
1261     COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_usb480m_p, 0,
1262             RK3568_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS,
1263             RK3568_CLKGATE_CON(29), 1, GFLAGS),
1264     COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
1265             RK3568_CLKSEL_CON(63), 0,
1266             RK3568_CLKGATE_CON(29), 2, GFLAGS,
1267             &rk3568_uart6_fracmux),
1268     GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_mux", 0,
1269             RK3568_CLKGATE_CON(29), 3, GFLAGS),
1270
1271     GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 0,
1272             RK3568_CLKGATE_CON(29), 4, GFLAGS),
1273     COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_usb480m_p, 0,
1274             RK3568_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS,
1275             RK3568_CLKGATE_CON(29), 5, GFLAGS),
1276     COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
1277             RK3568_CLKSEL_CON(65), 0,
1278             RK3568_CLKGATE_CON(29), 6, GFLAGS,
1279             &rk3568_uart7_fracmux),
1280     GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_mux", 0,
1281             RK3568_CLKGATE_CON(29), 7, GFLAGS),
1282
1283     GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 0,
1284             RK3568_CLKGATE_CON(29), 8, GFLAGS),
1285     COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_usb480m_p, 0,
1286             RK3568_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS,
1287             RK3568_CLKGATE_CON(29), 9, GFLAGS),
1288     COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT,
1289             RK3568_CLKSEL_CON(67), 0,
1290             RK3568_CLKGATE_CON(29), 10, GFLAGS,
1291             &rk3568_uart8_fracmux),
1292     GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_mux", 0,
1293             RK3568_CLKGATE_CON(29), 11, GFLAGS),
1294
1295     GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 0,
1296             RK3568_CLKGATE_CON(29), 12, GFLAGS),
1297     COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_usb480m_p, 0,
1298             RK3568_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS,
1299             RK3568_CLKGATE_CON(29), 13, GFLAGS),
1300     COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT,
1301             RK3568_CLKSEL_CON(69), 0,
1302             RK3568_CLKGATE_CON(29), 14, GFLAGS,
1303             &rk3568_uart9_fracmux),
1304     GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_mux", 0,
1305             RK3568_CLKGATE_CON(29), 15, GFLAGS),
1306
1307     GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 0,
1308             RK3568_CLKGATE_CON(27), 5, GFLAGS),
1309     COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
1310             RK3568_CLKSEL_CON(70), 7, 1, MFLAGS, 0, 5, DFLAGS,
1311             RK3568_CLKGATE_CON(27), 6, GFLAGS),
1312     GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 0,
1313             RK3568_CLKGATE_CON(27), 7, GFLAGS),
1314     COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
1315             RK3568_CLKSEL_CON(70), 15, 1, MFLAGS, 8, 5, DFLAGS,
1316             RK3568_CLKGATE_CON(27), 8, GFLAGS),
1317     GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 0,
1318             RK3568_CLKGATE_CON(27), 9, GFLAGS),
1319     COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0,
1320             RK3568_CLKSEL_CON(71), 7, 1, MFLAGS, 0, 5, DFLAGS,
1321             RK3568_CLKGATE_CON(27), 10, GFLAGS),
1322     COMPOSITE_NODIV(CLK_I2C, "clk_i2c", clk_i2c_p, 0,
1323             RK3568_CLKSEL_CON(71), 8, 2, MFLAGS,
1324             RK3568_CLKGATE_CON(32), 10, GFLAGS),
1325     GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0,
1326             RK3568_CLKGATE_CON(30), 0, GFLAGS),
1327     GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0,
1328             RK3568_CLKGATE_CON(30), 1, GFLAGS),
1329     GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0,
1330             RK3568_CLKGATE_CON(30), 2, GFLAGS),
1331     GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0,
1332             RK3568_CLKGATE_CON(30), 3, GFLAGS),
1333     GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0,
1334             RK3568_CLKGATE_CON(30), 4, GFLAGS),
1335     GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0,
1336             RK3568_CLKGATE_CON(30), 5, GFLAGS),
1337     GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0,
1338             RK3568_CLKGATE_CON(30), 6, GFLAGS),
1339     GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0,
1340             RK3568_CLKGATE_CON(30), 7, GFLAGS),
1341     GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0,
1342             RK3568_CLKGATE_CON(30), 8, GFLAGS),
1343     GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0,
1344             RK3568_CLKGATE_CON(30), 9, GFLAGS),
1345     GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0,
1346             RK3568_CLKGATE_CON(30), 10, GFLAGS),
1347     COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", gpll200_xin24m_cpll100_p, 0,
1348             RK3568_CLKSEL_CON(72), 0, 1, MFLAGS,
1349             RK3568_CLKGATE_CON(30), 11, GFLAGS),
1350     GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0,
1351             RK3568_CLKGATE_CON(30), 12, GFLAGS),
1352     COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", gpll200_xin24m_cpll100_p, 0,
1353             RK3568_CLKSEL_CON(72), 2, 1, MFLAGS,
1354             RK3568_CLKGATE_CON(30), 13, GFLAGS),
1355     GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0,
1356             RK3568_CLKGATE_CON(30), 14, GFLAGS),
1357     COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", gpll200_xin24m_cpll100_p, 0,
1358             RK3568_CLKSEL_CON(72), 4, 1, MFLAGS,
1359             RK3568_CLKGATE_CON(30), 15, GFLAGS),
1360     GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 0,
1361             RK3568_CLKGATE_CON(31), 0, GFLAGS),
1362     COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", gpll200_xin24m_cpll100_p, 0,
1363             RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS),
1364     GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS),
1365     COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0,
1366             RK3568_CLKSEL_CON(72), 8, 1, MFLAGS,
1367             RK3568_CLKGATE_CON(31), 11, GFLAGS),
1368     GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
1369             RK3568_CLKGATE_CON(31), 12, GFLAGS),
1370     GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0,
1371             RK3568_CLKGATE_CON(31), 13, GFLAGS),
1372     COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0,
1373             RK3568_CLKSEL_CON(72), 10, 1, MFLAGS,
1374             RK3568_CLKGATE_CON(31), 14, GFLAGS),
1375     GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
1376             RK3568_CLKGATE_CON(31), 15, GFLAGS),
1377     GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0,
1378             RK3568_CLKGATE_CON(32), 0, GFLAGS),
1379     COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0,
1380             RK3568_CLKSEL_CON(72), 12, 1, MFLAGS,
1381             RK3568_CLKGATE_CON(32), 1, GFLAGS),
1382     GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
1383             RK3568_CLKGATE_CON(32), 2, GFLAGS),
1384     COMPOSITE_NODIV(DBCLK_GPIO, "dbclk_gpio", xin24m_32k_p, 0,
1385             RK3568_CLKSEL_CON(72), 14, 1, MFLAGS,
1386             RK3568_CLKGATE_CON(32), 11, GFLAGS),
1387     GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0,
1388             RK3568_CLKGATE_CON(31), 2, GFLAGS),
1389     GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 0,
1390             RK3568_CLKGATE_CON(31), 3, GFLAGS),
1391     GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0,
1392             RK3568_CLKGATE_CON(31), 4, GFLAGS),
1393     GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 0,
1394             RK3568_CLKGATE_CON(31), 5, GFLAGS),
1395     GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0,
1396             RK3568_CLKGATE_CON(31), 6, GFLAGS),
1397     GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 0,
1398             RK3568_CLKGATE_CON(31), 7, GFLAGS),
1399     GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0,
1400             RK3568_CLKGATE_CON(31), 8, GFLAGS),
1401     GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 0,
1402             RK3568_CLKGATE_CON(31), 9, GFLAGS),
1403     GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0,
1404             RK3568_CLKGATE_CON(32), 3, GFLAGS),
1405     GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
1406             RK3568_CLKGATE_CON(32), 4, GFLAGS),
1407     GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
1408             RK3568_CLKGATE_CON(32), 5, GFLAGS),
1409     GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
1410             RK3568_CLKGATE_CON(32), 6, GFLAGS),
1411     GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
1412             RK3568_CLKGATE_CON(32), 7, GFLAGS),
1413     GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
1414             RK3568_CLKGATE_CON(32), 8, GFLAGS),
1415     GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
1416             RK3568_CLKGATE_CON(32), 9, GFLAGS),
1417
1418     /* PD_TOP */
1419     COMPOSITE_NODIV(ACLK_TOP_HIGH, "aclk_top_high", cpll500_gpll400_gpll300_xin24m_p, 0,
1420             RK3568_CLKSEL_CON(73), 0, 2, MFLAGS,
1421             RK3568_CLKGATE_CON(33), 0, GFLAGS),
1422     COMPOSITE_NODIV(ACLK_TOP_LOW, "aclk_top_low", gpll400_gpll300_gpll200_xin24m_p, 0,
1423             RK3568_CLKSEL_CON(73), 4, 2, MFLAGS,
1424             RK3568_CLKGATE_CON(33), 1, GFLAGS),
1425     COMPOSITE_NODIV(HCLK_TOP, "hclk_top", gpll150_gpll100_gpll75_xin24m_p, 0,
1426             RK3568_CLKSEL_CON(73), 8, 2, MFLAGS,
1427             RK3568_CLKGATE_CON(33), 2, GFLAGS),
1428     COMPOSITE_NODIV(PCLK_TOP, "pclk_top", gpll100_gpll75_cpll50_xin24m_p, 0,
1429             RK3568_CLKSEL_CON(73), 12, 2, MFLAGS,
1430             RK3568_CLKGATE_CON(33), 3, GFLAGS),
1431     GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 0,
1432             RK3568_CLKGATE_CON(33), 8, GFLAGS),
1433     COMPOSITE_NODIV(CLK_OPTC_ARB, "clk_optc_arb", xin24m_cpll100_p, 0,
1434             RK3568_CLKSEL_CON(73), 15, 1, MFLAGS,
1435             RK3568_CLKGATE_CON(33), 9, GFLAGS),
1436     GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 0,
1437             RK3568_CLKGATE_CON(33), 13, GFLAGS),
1438     GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 0,
1439             RK3568_CLKGATE_CON(33), 14, GFLAGS),
1440     GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 0,
1441             RK3568_CLKGATE_CON(33), 15, GFLAGS),
1442     GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0,
1443             RK3568_CLKGATE_CON(34), 4, GFLAGS),
1444     GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 0,
1445             RK3568_CLKGATE_CON(34), 5, GFLAGS),
1446     GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 0,
1447             RK3568_CLKGATE_CON(34), 6, GFLAGS),
1448     GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 0,
1449             RK3568_CLKGATE_CON(34), 11, GFLAGS),
1450     GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 0,
1451             RK3568_CLKGATE_CON(34), 12, GFLAGS),
1452     GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0,
1453             RK3568_CLKGATE_CON(34), 13, GFLAGS),
1454     GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0,
1455             RK3568_CLKGATE_CON(34), 14, GFLAGS),
1456 };
1457
1458 static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = {
1459     /* PD_PMU */
1460     FACTOR(0, "ppll_ph0", "ppll", 0, 1, 2),
1461     FACTOR(0, "ppll_ph180", "ppll", 0, 1, 2),
1462     FACTOR(0, "hpll_ph0", "hpll", 0, 1, 2),
1463
1464     MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0,
1465             RK3568_PMU_CLKSEL_CON(2), 15, 1, MFLAGS),
1466     COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "clk_pdpmu", 0,
1467             RK3568_PMU_CLKSEL_CON(2), 0, 5, DFLAGS,
1468             RK3568_PMU_CLKGATE_CON(0), 2, GFLAGS),
1469     GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0,
1470             RK3568_PMU_CLKGATE_CON(0), 6, GFLAGS),
1471     GATE(CLK_PMU, "clk_pmu", "xin24m", 0,
1472             RK3568_PMU_CLKGATE_CON(0), 7, GFLAGS),
1473     GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
1474             RK3568_PMU_CLKGATE_CON(1), 0, GFLAGS),
1475     COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "clk_pdpmu", 0,
1476             RK3568_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1477             RK3568_PMU_CLKGATE_CON(1), 1, GFLAGS),
1478     GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 0,
1479             RK3568_PMU_CLKGATE_CON(1), 2, GFLAGS),
1480
1481     COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
1482             RK3568_PMU_CLKSEL_CON(1), 0,
1483             RK3568_PMU_CLKGATE_CON(0), 1, GFLAGS,
1484             &rk3568_rtc32k_pmu_fracmux),
1485
1486     COMPOSITE_NOMUX(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IGNORE_UNUSED,
1487             RK3568_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
1488             RK3568_PMU_CLKGATE_CON(0), 0, GFLAGS),
1489
1490     COMPOSITE(CLK_UART0_DIV, "sclk_uart0_div", ppll_usb480m_cpll_gpll_p, 0,
1491             RK3568_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
1492             RK3568_PMU_CLKGATE_CON(1), 3, GFLAGS),
1493     COMPOSITE_FRACMUX(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
1494             RK3568_PMU_CLKSEL_CON(5), 0,
1495             RK3568_PMU_CLKGATE_CON(1), 4, GFLAGS,
1496             &rk3568_uart0_fracmux),
1497     GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
1498             RK3568_PMU_CLKGATE_CON(1), 5, GFLAGS),
1499
1500     GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
1501             RK3568_PMU_CLKGATE_CON(1), 9, GFLAGS),
1502     COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", xin24m_32k_p, 0,
1503             RK3568_PMU_CLKSEL_CON(6), 15, 1, MFLAGS,
1504             RK3568_PMU_CLKGATE_CON(1), 10, GFLAGS),
1505     GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
1506             RK3568_PMU_CLKGATE_CON(1), 6, GFLAGS),
1507     COMPOSITE(CLK_PWM0, "clk_pwm0", clk_pwm0_p, 0,
1508             RK3568_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
1509             RK3568_PMU_CLKGATE_CON(1), 7, GFLAGS),
1510     GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 0,
1511             RK3568_PMU_CLKGATE_CON(1), 8, GFLAGS),
1512     GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
1513             RK3568_PMU_CLKGATE_CON(1), 11, GFLAGS),
1514     GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
1515             RK3568_PMU_CLKGATE_CON(1), 12, GFLAGS),
1516     GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
1517             RK3568_PMU_CLKGATE_CON(1), 13, GFLAGS),
1518     COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "clk_pdpmu", 0,
1519             RK3568_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
1520             RK3568_PMU_CLKGATE_CON(2), 0, GFLAGS),
1521     GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 0,
1522             RK3568_PMU_CLKGATE_CON(2), 1, GFLAGS),
1523     MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0,
1524             RK3568_PMU_CLKSEL_CON(8), 0, 1, MFLAGS),
1525     GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 0,
1526             RK3568_PMU_CLKGATE_CON(2), 2, GFLAGS),
1527     MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0,
1528             RK3568_PMU_CLKSEL_CON(8), 1, 1, MFLAGS),
1529     GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 0,
1530             RK3568_PMU_CLKGATE_CON(2), 3, GFLAGS),
1531     MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0,
1532             RK3568_PMU_CLKSEL_CON(8), 2, 1, MFLAGS),
1533     GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 0,
1534             RK3568_PMU_CLKGATE_CON(2), 4, GFLAGS),
1535     MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0,
1536             RK3568_PMU_CLKSEL_CON(8), 3, 1, MFLAGS),
1537     COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "clk_pdpmu", 0,
1538             RK3568_PMU_CLKSEL_CON(8), 8, 6, DFLAGS,
1539             RK3568_PMU_CLKGATE_CON(2), 5, GFLAGS),
1540     GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
1541             RK3568_PMU_CLKGATE_CON(2), 6, GFLAGS),
1542     MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, CLK_SET_RATE_PARENT,
1543             RK3568_PMU_CLKSEL_CON(8), 15, 1, MFLAGS),
1544     COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0,
1545             RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS,
1546             RK3568_PMU_CLKGATE_CON(2), 7, GFLAGS),
1547     GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 0,
1548             RK3568_PMU_CLKGATE_CON(2), 8, GFLAGS),
1549     MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", clk_pciephy0_ref_p, CLK_SET_RATE_PARENT,
1550             RK3568_PMU_CLKSEL_CON(9), 3, 1, MFLAGS),
1551     COMPOSITE_NOMUX(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "ppll_ph0", 0,
1552             RK3568_PMU_CLKSEL_CON(9), 4, 3, DFLAGS,
1553             RK3568_PMU_CLKGATE_CON(2), 9, GFLAGS),
1554     GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 0,
1555             RK3568_PMU_CLKGATE_CON(2), 10, GFLAGS),
1556     MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", clk_pciephy1_ref_p, CLK_SET_RATE_PARENT,
1557             RK3568_PMU_CLKSEL_CON(9), 7, 1, MFLAGS),
1558     COMPOSITE_NOMUX(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "ppll_ph0", 0,
1559             RK3568_PMU_CLKSEL_CON(9), 8, 3, DFLAGS,
1560             RK3568_PMU_CLKGATE_CON(2), 11, GFLAGS),
1561     GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 0,
1562             RK3568_PMU_CLKGATE_CON(2), 12, GFLAGS),
1563     MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", clk_pciephy2_ref_p, CLK_SET_RATE_PARENT,
1564             RK3568_PMU_CLKSEL_CON(9), 11, 1, MFLAGS),
1565     GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 0,
1566             RK3568_PMU_CLKGATE_CON(2), 13, GFLAGS),
1567     GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 0,
1568             RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS),
1569     GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0,
1570             RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS),
1571     MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT,
1572             RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS),
1573 };
1574
1575 static const char *const rk3568_cru_critical_clocks[] __initconst = {
1576     "armclk",
1577     "pclk_core_pre",
1578     "aclk_bus",
1579     "pclk_bus",
1580     "aclk_top_high",
1581     "aclk_top_low",
1582     "hclk_top",
1583     "pclk_top",
1584     "aclk_perimid",
1585     "hclk_perimid",
1586     "aclk_secure_flash",
1587     "hclk_secure_flash",
1588     "aclk_core_niu2bus",
1589     "npll",
1590     "clk_optc_arb",
1591     "hclk_php",
1592     "pclk_php",
1593     "hclk_usb",
1594     "hclk_vo",
1595 };
1596
1597 static const char *const rk3568_pmucru_critical_clocks[] __initconst = {
1598     "pclk_pdpmu",
1599     "pclk_pmu",
1600     "clk_pmu",
1601 };
1602
1603 static void __init rk3568_pmu_clk_init(struct device_node *np)
1604 {
1605     struct rockchip_clk_provider *ctx;
1606     void __iomem *reg_base;
1607
1608     reg_base = of_iomap(np, 0);
1609     if (!reg_base) {
1610         pr_err("%s: could not map cru pmu region\n", __func__);
1611         return;
1612     }
1613
1614     ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1615     if (IS_ERR(ctx)) {
1616         pr_err("%s: rockchip pmu clk init failed\n", __func__);
1617         return;
1618     }
1619
1620     rockchip_clk_register_plls(ctx, rk3568_pmu_pll_clks,
1621                    ARRAY_SIZE(rk3568_pmu_pll_clks),
1622                    RK3568_GRF_SOC_STATUS0);
1623
1624     rockchip_clk_register_branches(ctx, rk3568_clk_pmu_branches,
1625                        ARRAY_SIZE(rk3568_clk_pmu_branches));
1626
1627     rockchip_register_softrst(np, 1, reg_base + RK3568_PMU_SOFTRST_CON(0),
1628                   ROCKCHIP_SOFTRST_HIWORD_MASK);
1629
1630     rockchip_clk_protect_critical(rk3568_pmucru_critical_clocks,
1631                       ARRAY_SIZE(rk3568_pmucru_critical_clocks));
1632
1633     rockchip_clk_of_add_provider(np, ctx);
1634 }
1635
1636 CLK_OF_DECLARE(rk3568_cru_pmu, "rockchip,rk3568-pmucru", rk3568_pmu_clk_init);
1637
1638 static void __init rk3568_clk_init(struct device_node *np)
1639 {
1640     struct rockchip_clk_provider *ctx;
1641     void __iomem *reg_base;
1642
1643     reg_base = of_iomap(np, 0);
1644     if (!reg_base) {
1645         pr_err("%s: could not map cru region\n", __func__);
1646         return;
1647     }
1648
1649     ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1650     if (IS_ERR(ctx)) {
1651         pr_err("%s: rockchip clk init failed\n", __func__);
1652         iounmap(reg_base);
1653         return;
1654     }
1655
1656     rockchip_clk_register_plls(ctx, rk3568_pll_clks,
1657                    ARRAY_SIZE(rk3568_pll_clks),
1658                    RK3568_GRF_SOC_STATUS0);
1659
1660     rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1661                      mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
1662                      &rk3568_cpuclk_data, rk3568_cpuclk_rates,
1663                      ARRAY_SIZE(rk3568_cpuclk_rates));
1664
1665     rockchip_clk_register_branches(ctx, rk3568_clk_branches,
1666                        ARRAY_SIZE(rk3568_clk_branches));
1667
1668     rockchip_register_softrst(np, 30, reg_base + RK3568_SOFTRST_CON(0),
1669                   ROCKCHIP_SOFTRST_HIWORD_MASK);
1670
1671     rockchip_register_restart_notifier(ctx, RK3568_GLB_SRST_FST, NULL);
1672
1673     rockchip_clk_protect_critical(rk3568_cru_critical_clocks,
1674                       ARRAY_SIZE(rk3568_cru_critical_clocks));
1675
1676     rockchip_clk_of_add_provider(np, ctx);
1677 }
1678
1679 CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init);
1680
1681 struct clk_rk3568_inits {
1682     void (*inits)(struct device_node *np);
1683 };
1684
1685 static const struct clk_rk3568_inits clk_rk3568_pmucru_init = {
1686     .inits = rk3568_pmu_clk_init,
1687 };
1688
1689 static const struct clk_rk3568_inits clk_3568_cru_init = {
1690     .inits = rk3568_clk_init,
1691 };
1692
1693 static const struct of_device_id clk_rk3568_match_table[] = {
1694     {
1695         .compatible = "rockchip,rk3568-cru",
1696         .data = &clk_3568_cru_init,
1697     },  {
1698         .compatible = "rockchip,rk3568-pmucru",
1699         .data = &clk_rk3568_pmucru_init,
1700     },
1701     { }
1702 };
1703
1704 static int __init clk_rk3568_probe(struct platform_device *pdev)
1705 {
1706     struct device_node *np = pdev->dev.of_node;
1707     const struct clk_rk3568_inits *init_data;
1708
1709     init_data = (struct clk_rk3568_inits *)of_device_get_match_data(&pdev->dev);
1710     if (!init_data)
1711         return -EINVAL;
1712
1713     if (init_data->inits)
1714         init_data->inits(np);
1715
1716     return 0;
1717 }
1718
1719 static struct platform_driver clk_rk3568_driver = {
1720     .driver     = {
1721         .name   = "clk-rk3568",
1722         .of_match_table = clk_rk3568_match_table,
1723         .suppress_bind_attrs = true,
1724     },
1725 };
1726 builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe);