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0007 #include <linux/clk-provider.h>
0008 #include <linux/module.h>
0009 #include <linux/io.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/regmap.h>
0015 #include <dt-bindings/clock/rk3399-cru.h>
0016 #include "clk.h"
0017
0018 enum rk3399_plls {
0019 lpll, bpll, dpll, cpll, gpll, npll, vpll,
0020 };
0021
0022 enum rk3399_pmu_plls {
0023 ppll,
0024 };
0025
0026 static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
0027
0028 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
0029 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
0030 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
0031 RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
0032 RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
0033 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
0034 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
0035 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
0036 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
0037 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
0038 RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
0039 RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
0040 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
0041 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
0042 RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
0043 RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
0044 RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
0045 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
0046 RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
0047 RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
0048 RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
0049 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
0050 RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
0051 RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
0052 RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
0053 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
0054 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
0055 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
0056 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
0057 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
0058 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
0059 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
0060 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
0061 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
0062 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
0063 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
0064 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
0065 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
0066 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
0067 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
0068 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
0069 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
0070 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
0071 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
0072 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
0073 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
0074 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
0075 RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0),
0076 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
0077 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
0078 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
0079 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
0080 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
0081 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
0082 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
0083 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
0084 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
0085 RK3036_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0),
0086 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
0087 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
0088 RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
0089 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
0090 RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
0091 RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0),
0092 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
0093 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
0094 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
0095 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
0096 RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
0097 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
0098 RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
0099 RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
0100 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
0101 RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0),
0102 RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0),
0103 RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0),
0104 RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0),
0105 { },
0106 };
0107
0108
0109 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
0110
0111 PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src",
0112 "clk_core_l_bpll_src",
0113 "clk_core_l_dpll_src",
0114 "clk_core_l_gpll_src" };
0115 PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",
0116 "clk_core_b_bpll_src",
0117 "clk_core_b_dpll_src",
0118 "clk_core_b_gpll_src" };
0119 PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
0120 "clk_ddrc_bpll_src",
0121 "clk_ddrc_dpll_src",
0122 "clk_ddrc_gpll_src" };
0123 PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
0124 "gpll_aclk_cci_src",
0125 "npll_aclk_cci_src",
0126 "vpll_aclk_cci_src" };
0127 PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
0128 "gpll_cci_trace" };
0129 PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
0130 "npll_cs"};
0131 PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src",
0132 "gpll_aclk_perihp_src" };
0133
0134 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
0135 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
0136 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
0137 PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
0138 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
0139 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll",
0140 "ppll" };
0141 PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll",
0142 "xin24m" };
0143 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll",
0144 "clk_usbphy_480m" };
0145 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
0146 "npll", "upll" };
0147 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll",
0148 "upll", "xin24m" };
0149 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
0150 "ppll", "upll", "xin24m" };
0151
0152 PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
0153 PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll",
0154 "npll" };
0155 PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll",
0156 "xin24m" };
0157
0158 PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
0159 "dclk_vop0_frac" };
0160 PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div",
0161 "dclk_vop1_frac" };
0162
0163 PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" };
0164
0165 PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
0166 PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
0167 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
0168 "cpll", "gpll" };
0169 PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru",
0170 "clk_pcie_core_phy" };
0171
0172 PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src",
0173 "gpll_aclk_emmc_src" };
0174
0175 PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src",
0176 "gpll_aclk_perilp0_src" };
0177
0178 PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src",
0179 "gpll_fclk_cm0s_src" };
0180
0181 PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src",
0182 "gpll_hclk_perilp1_src" };
0183
0184 PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
0185 PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
0186
0187 PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src",
0188 "clk_usbphy1_480m_src" };
0189 PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src",
0190 "gpll_aclk_gmac_src" };
0191 PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" };
0192 PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
0193 "clkin_i2s", "xin12m" };
0194 PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
0195 "clkin_i2s", "xin12m" };
0196 PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
0197 "clkin_i2s", "xin12m" };
0198 PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
0199 "clkin_i2s", "xin12m" };
0200 PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1",
0201 "clk_i2s2" };
0202 PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" };
0203
0204 PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
0205 PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
0206 PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
0207 PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
0208
0209
0210 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
0211 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
0212 PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" };
0213 PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" };
0214 PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac",
0215 "xin24m" };
0216 PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" };
0217
0218 static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
0219 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
0220 RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
0221 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
0222 RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
0223 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
0224 RK3399_PLL_CON(19), 8, 31, 0, NULL),
0225 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
0226 RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
0227 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
0228 RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
0229 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
0230 RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
0231 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
0232 RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
0233 };
0234
0235 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
0236 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
0237 RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
0238 };
0239
0240 #define MFLAGS CLK_MUX_HIWORD_MASK
0241 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
0242 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
0243 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
0244
0245 static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =
0246 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
0247 RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
0248
0249 static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =
0250 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
0251 RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
0252
0253 static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =
0254 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
0255 RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
0256
0257 static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =
0258 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
0259 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
0260
0261 static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
0262 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
0263 RK3399_CLKSEL_CON(33), 8, 2, MFLAGS);
0264
0265 static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
0266 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
0267 RK3399_CLKSEL_CON(34), 8, 2, MFLAGS);
0268
0269 static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
0270 MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
0271 RK3399_CLKSEL_CON(35), 8, 2, MFLAGS);
0272
0273 static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
0274 MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
0275 RK3399_CLKSEL_CON(36), 8, 2, MFLAGS);
0276
0277 static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
0278 MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
0279 RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
0280
0281 static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
0282 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
0283 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
0284
0285 static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
0286 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT,
0287 RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
0288
0289 static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
0290 MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
0291 RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
0292
0293 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
0294 .core_reg[0] = RK3399_CLKSEL_CON(0),
0295 .div_core_shift[0] = 0,
0296 .div_core_mask[0] = 0x1f,
0297 .num_cores = 1,
0298 .mux_core_alt = 3,
0299 .mux_core_main = 0,
0300 .mux_core_shift = 6,
0301 .mux_core_mask = 0x3,
0302 };
0303
0304 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
0305 .core_reg[0] = RK3399_CLKSEL_CON(2),
0306 .div_core_shift[0] = 0,
0307 .div_core_mask[0] = 0x1f,
0308 .num_cores = 1,
0309 .mux_core_alt = 3,
0310 .mux_core_main = 1,
0311 .mux_core_shift = 6,
0312 .mux_core_mask = 0x3,
0313 };
0314
0315 #define RK3399_DIV_ACLKM_MASK 0x1f
0316 #define RK3399_DIV_ACLKM_SHIFT 8
0317 #define RK3399_DIV_ATCLK_MASK 0x1f
0318 #define RK3399_DIV_ATCLK_SHIFT 0
0319 #define RK3399_DIV_PCLK_DBG_MASK 0x1f
0320 #define RK3399_DIV_PCLK_DBG_SHIFT 8
0321
0322 #define RK3399_CLKSEL0(_offs, _aclkm) \
0323 { \
0324 .reg = RK3399_CLKSEL_CON(0 + _offs), \
0325 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
0326 RK3399_DIV_ACLKM_SHIFT), \
0327 }
0328 #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \
0329 { \
0330 .reg = RK3399_CLKSEL_CON(1 + _offs), \
0331 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
0332 RK3399_DIV_ATCLK_SHIFT) | \
0333 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
0334 RK3399_DIV_PCLK_DBG_SHIFT), \
0335 }
0336
0337
0338 #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
0339 { \
0340 .prate = _prate##U, \
0341 .divs = { \
0342 RK3399_CLKSEL0(0, _aclkm), \
0343 RK3399_CLKSEL1(0, _atclk, _pdbg), \
0344 }, \
0345 }
0346
0347
0348 #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
0349 { \
0350 .prate = _prate##U, \
0351 .divs = { \
0352 RK3399_CLKSEL0(2, _aclkm), \
0353 RK3399_CLKSEL1(2, _atclk, _pdbg), \
0354 }, \
0355 }
0356
0357 static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
0358 RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8),
0359 RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
0360 RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7),
0361 RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
0362 RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6),
0363 RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
0364 RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5),
0365 RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
0366 RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4),
0367 RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3),
0368 RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3),
0369 RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2),
0370 RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1),
0371 RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1),
0372 RK3399_CPUCLKL_RATE( 96000000, 1, 1, 1),
0373 };
0374
0375 static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
0376 RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11),
0377 RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
0378 RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10),
0379 RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
0380 RK3399_CPUCLKB_RATE(2016000000, 1, 9, 9),
0381 RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
0382 RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9),
0383 RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
0384 RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8),
0385 RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
0386 RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7),
0387 RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
0388 RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6),
0389 RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
0390 RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5),
0391 RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4),
0392 RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3),
0393 RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3),
0394 RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2),
0395 RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1),
0396 RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1),
0397 RK3399_CPUCLKB_RATE( 96000000, 1, 1, 1),
0398 };
0399
0400 static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
0401
0402
0403
0404
0405
0406 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
0407 RK3399_CLKGATE_CON(6), 5, GFLAGS),
0408 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
0409 RK3399_CLKGATE_CON(6), 6, GFLAGS),
0410
0411 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0,
0412 RK3399_CLKGATE_CON(13), 12, GFLAGS),
0413 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0,
0414 RK3399_CLKGATE_CON(13), 12, GFLAGS),
0415 MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0,
0416 RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
0417
0418 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
0419 RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
0420
0421 COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0,
0422 RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
0423 RK3399_CLKGATE_CON(6), 4, GFLAGS),
0424
0425 COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0,
0426 RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
0427 RK3399_CLKGATE_CON(12), 0, GFLAGS),
0428 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
0429 RK3399_CLKGATE_CON(30), 0, GFLAGS),
0430 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
0431 RK3399_CLKGATE_CON(30), 1, GFLAGS),
0432 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0,
0433 RK3399_CLKGATE_CON(30), 2, GFLAGS),
0434 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0,
0435 RK3399_CLKGATE_CON(30), 3, GFLAGS),
0436 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0,
0437 RK3399_CLKGATE_CON(30), 4, GFLAGS),
0438
0439 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
0440 RK3399_CLKGATE_CON(12), 1, GFLAGS),
0441 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
0442 RK3399_CLKGATE_CON(12), 2, GFLAGS),
0443
0444 COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0,
0445 RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
0446 RK3399_CLKGATE_CON(12), 3, GFLAGS),
0447
0448 COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0,
0449 RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
0450 RK3399_CLKGATE_CON(12), 4, GFLAGS),
0451
0452 COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0,
0453 RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
0454 RK3399_CLKGATE_CON(13), 4, GFLAGS),
0455
0456 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
0457 RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
0458 RK3399_CLKGATE_CON(13), 5, GFLAGS),
0459
0460 COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0,
0461 RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
0462 RK3399_CLKGATE_CON(13), 6, GFLAGS),
0463
0464 COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
0465 RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
0466 RK3399_CLKGATE_CON(13), 7, GFLAGS),
0467
0468
0469 GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
0470 RK3399_CLKGATE_CON(0), 0, GFLAGS),
0471 GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
0472 RK3399_CLKGATE_CON(0), 1, GFLAGS),
0473 GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
0474 RK3399_CLKGATE_CON(0), 2, GFLAGS),
0475 GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
0476 RK3399_CLKGATE_CON(0), 3, GFLAGS),
0477
0478 COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
0479 RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
0480 RK3399_CLKGATE_CON(0), 4, GFLAGS),
0481 COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
0482 RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
0483 RK3399_CLKGATE_CON(0), 5, GFLAGS),
0484 COMPOSITE_NOMUX(PCLK_COREDBG_L, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
0485 RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
0486 RK3399_CLKGATE_CON(0), 6, GFLAGS),
0487
0488 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
0489 RK3399_CLKGATE_CON(14), 12, GFLAGS),
0490 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
0491 RK3399_CLKGATE_CON(14), 13, GFLAGS),
0492
0493 GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
0494 RK3399_CLKGATE_CON(14), 9, GFLAGS),
0495 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
0496 RK3399_CLKGATE_CON(14), 10, GFLAGS),
0497 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
0498 RK3399_CLKGATE_CON(14), 11, GFLAGS),
0499 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0,
0500 RK3399_CLKGATE_CON(0), 7, GFLAGS),
0501
0502
0503 GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
0504 RK3399_CLKGATE_CON(1), 0, GFLAGS),
0505 GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
0506 RK3399_CLKGATE_CON(1), 1, GFLAGS),
0507 GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
0508 RK3399_CLKGATE_CON(1), 2, GFLAGS),
0509 GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
0510 RK3399_CLKGATE_CON(1), 3, GFLAGS),
0511
0512 COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
0513 RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
0514 RK3399_CLKGATE_CON(1), 4, GFLAGS),
0515 COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
0516 RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
0517 RK3399_CLKGATE_CON(1), 5, GFLAGS),
0518 COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
0519 RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
0520 RK3399_CLKGATE_CON(1), 6, GFLAGS),
0521
0522 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
0523 RK3399_CLKGATE_CON(14), 5, GFLAGS),
0524 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
0525 RK3399_CLKGATE_CON(14), 6, GFLAGS),
0526
0527 GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
0528 RK3399_CLKGATE_CON(14), 1, GFLAGS),
0529 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
0530 RK3399_CLKGATE_CON(14), 3, GFLAGS),
0531 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
0532 RK3399_CLKGATE_CON(14), 4, GFLAGS),
0533
0534 DIV(PCLK_COREDBG_B, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
0535 RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
0536
0537 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
0538 RK3399_CLKGATE_CON(14), 2, GFLAGS),
0539
0540 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 0,
0541 RK3399_CLKGATE_CON(1), 7, GFLAGS),
0542
0543
0544 GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
0545 RK3399_CLKGATE_CON(6), 9, GFLAGS),
0546 GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
0547 RK3399_CLKGATE_CON(6), 8, GFLAGS),
0548 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0,
0549 RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
0550 RK3399_CLKGATE_CON(6), 10, GFLAGS),
0551
0552 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
0553 RK3399_CLKGATE_CON(32), 0, GFLAGS),
0554 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
0555 RK3399_CLKGATE_CON(32), 1, GFLAGS),
0556 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0,
0557 RK3399_CLKGATE_CON(32), 4, GFLAGS),
0558
0559 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
0560 RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
0561 RK3399_CLKGATE_CON(6), 11, GFLAGS),
0562 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
0563 RK3399_CLKGATE_CON(32), 2, GFLAGS),
0564 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
0565 RK3399_CLKGATE_CON(32), 3, GFLAGS),
0566
0567 COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0,
0568 RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
0569 RK3399_CLKGATE_CON(5), 5, GFLAGS),
0570
0571 MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
0572 RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
0573 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
0574 RK3399_CLKGATE_CON(5), 6, GFLAGS),
0575 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
0576 RK3399_CLKGATE_CON(5), 7, GFLAGS),
0577 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0,
0578 RK3399_CLKGATE_CON(5), 8, GFLAGS),
0579 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0,
0580 RK3399_CLKGATE_CON(5), 9, GFLAGS),
0581
0582
0583 COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
0584 RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
0585 RK3399_CLKGATE_CON(8), 13, GFLAGS),
0586 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0,
0587 RK3399_CLKSEL_CON(99), 0,
0588 RK3399_CLKGATE_CON(8), 14, GFLAGS,
0589 &rk3399_spdif_fracmux),
0590 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
0591 RK3399_CLKGATE_CON(8), 15, GFLAGS),
0592
0593 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
0594 RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
0595 RK3399_CLKGATE_CON(10), 6, GFLAGS),
0596
0597 COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
0598 RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
0599 RK3399_CLKGATE_CON(8), 3, GFLAGS),
0600 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,
0601 RK3399_CLKSEL_CON(96), 0,
0602 RK3399_CLKGATE_CON(8), 4, GFLAGS,
0603 &rk3399_i2s0_fracmux),
0604 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
0605 RK3399_CLKGATE_CON(8), 5, GFLAGS),
0606
0607 COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
0608 RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
0609 RK3399_CLKGATE_CON(8), 6, GFLAGS),
0610 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,
0611 RK3399_CLKSEL_CON(97), 0,
0612 RK3399_CLKGATE_CON(8), 7, GFLAGS,
0613 &rk3399_i2s1_fracmux),
0614 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
0615 RK3399_CLKGATE_CON(8), 8, GFLAGS),
0616
0617 COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
0618 RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
0619 RK3399_CLKGATE_CON(8), 9, GFLAGS),
0620 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,
0621 RK3399_CLKSEL_CON(98), 0,
0622 RK3399_CLKGATE_CON(8), 10, GFLAGS,
0623 &rk3399_i2s2_fracmux),
0624 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
0625 RK3399_CLKGATE_CON(8), 11, GFLAGS),
0626
0627 MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
0628 RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
0629 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
0630 RK3399_CLKSEL_CON(31), 2, 1, MFLAGS,
0631 RK3399_CLKGATE_CON(8), 12, GFLAGS),
0632
0633
0634 MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
0635 RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
0636 COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
0637 RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
0638 RK3399_CLKGATE_CON(9), 0, GFLAGS),
0639 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 0,
0640 RK3399_CLKSEL_CON(100), 0,
0641 RK3399_CLKGATE_CON(9), 1, GFLAGS,
0642 &rk3399_uart0_fracmux),
0643
0644 MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
0645 RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
0646 COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
0647 RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
0648 RK3399_CLKGATE_CON(9), 2, GFLAGS),
0649 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 0,
0650 RK3399_CLKSEL_CON(101), 0,
0651 RK3399_CLKGATE_CON(9), 3, GFLAGS,
0652 &rk3399_uart1_fracmux),
0653
0654 COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
0655 RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
0656 RK3399_CLKGATE_CON(9), 4, GFLAGS),
0657 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 0,
0658 RK3399_CLKSEL_CON(102), 0,
0659 RK3399_CLKGATE_CON(9), 5, GFLAGS,
0660 &rk3399_uart2_fracmux),
0661
0662 COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
0663 RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
0664 RK3399_CLKGATE_CON(9), 6, GFLAGS),
0665 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", 0,
0666 RK3399_CLKSEL_CON(103), 0,
0667 RK3399_CLKGATE_CON(9), 7, GFLAGS,
0668 &rk3399_uart3_fracmux),
0669
0670 COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
0671 RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
0672 RK3399_CLKGATE_CON(3), 4, GFLAGS),
0673
0674 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
0675 RK3399_CLKGATE_CON(18), 10, GFLAGS),
0676 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0,
0677 RK3399_CLKGATE_CON(18), 12, GFLAGS),
0678 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
0679 RK3399_CLKGATE_CON(18), 15, GFLAGS),
0680 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
0681 RK3399_CLKGATE_CON(19), 2, GFLAGS),
0682
0683 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 0,
0684 RK3399_CLKGATE_CON(4), 11, GFLAGS),
0685 GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", 0,
0686 RK3399_CLKGATE_CON(3), 5, GFLAGS),
0687 GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", 0,
0688 RK3399_CLKGATE_CON(3), 6, GFLAGS),
0689
0690
0691 GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED,
0692 RK3399_CLKGATE_CON(2), 0, GFLAGS),
0693 GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED,
0694 RK3399_CLKGATE_CON(2), 1, GFLAGS),
0695 GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED,
0696 RK3399_CLKGATE_CON(2), 2, GFLAGS),
0697 GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
0698 RK3399_CLKGATE_CON(2), 3, GFLAGS),
0699
0700 COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
0701 RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
0702 RK3399_CLKGATE_CON(2), 4, GFLAGS),
0703
0704 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED,
0705 RK3399_CLKGATE_CON(15), 0, GFLAGS),
0706 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED,
0707 RK3399_CLKGATE_CON(15), 1, GFLAGS),
0708 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED,
0709 RK3399_CLKGATE_CON(15), 2, GFLAGS),
0710 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED,
0711 RK3399_CLKGATE_CON(15), 3, GFLAGS),
0712 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED,
0713 RK3399_CLKGATE_CON(15), 4, GFLAGS),
0714 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED,
0715 RK3399_CLKGATE_CON(15), 7, GFLAGS),
0716
0717 GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
0718 RK3399_CLKGATE_CON(2), 5, GFLAGS),
0719 GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
0720 RK3399_CLKGATE_CON(2), 6, GFLAGS),
0721 COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
0722 RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS,
0723 RK3399_CLKGATE_CON(2), 7, GFLAGS),
0724
0725 GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
0726 RK3399_CLKGATE_CON(2), 8, GFLAGS),
0727 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
0728 RK3399_CLKGATE_CON(2), 9, GFLAGS),
0729 GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
0730 RK3399_CLKGATE_CON(2), 10, GFLAGS),
0731 COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
0732 RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
0733 GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
0734 RK3399_CLKGATE_CON(15), 5, GFLAGS),
0735 GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED,
0736 RK3399_CLKGATE_CON(15), 6, GFLAGS),
0737
0738
0739 COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
0740 RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
0741 RK3399_CLKGATE_CON(4), 0, GFLAGS),
0742 COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
0743 RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
0744 RK3399_CLKGATE_CON(4), 1, GFLAGS),
0745 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
0746 RK3399_CLKGATE_CON(17), 2, GFLAGS),
0747 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
0748 RK3399_CLKGATE_CON(17), 3, GFLAGS),
0749
0750 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
0751 RK3399_CLKGATE_CON(17), 0, GFLAGS),
0752 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
0753 RK3399_CLKGATE_CON(17), 1, GFLAGS),
0754
0755
0756 COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0,
0757 RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
0758 RK3399_CLKGATE_CON(4), 4, GFLAGS),
0759 COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0,
0760 RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
0761 RK3399_CLKGATE_CON(4), 5, GFLAGS),
0762
0763 COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
0764 RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
0765 RK3399_CLKGATE_CON(4), 2, GFLAGS),
0766 COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
0767 RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
0768 RK3399_CLKGATE_CON(4), 3, GFLAGS),
0769 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
0770 RK3399_CLKGATE_CON(17), 10, GFLAGS),
0771 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
0772 RK3399_CLKGATE_CON(17), 11, GFLAGS),
0773
0774 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
0775 RK3399_CLKGATE_CON(17), 8, GFLAGS),
0776 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
0777 RK3399_CLKGATE_CON(17), 9, GFLAGS),
0778
0779
0780 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
0781 RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
0782 RK3399_CLKGATE_CON(4), 6, GFLAGS),
0783 COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
0784 RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
0785 RK3399_CLKGATE_CON(4), 7, GFLAGS),
0786 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
0787 RK3399_CLKGATE_CON(16), 2, GFLAGS),
0788 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED,
0789 RK3399_CLKGATE_CON(16), 3, GFLAGS),
0790
0791 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
0792 RK3399_CLKGATE_CON(16), 0, GFLAGS),
0793 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED,
0794 RK3399_CLKGATE_CON(16), 1, GFLAGS),
0795
0796
0797 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
0798 RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
0799 RK3399_CLKGATE_CON(4), 10, GFLAGS),
0800
0801 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
0802 RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
0803 RK3399_CLKGATE_CON(4), 8, GFLAGS),
0804 COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
0805 RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
0806 RK3399_CLKGATE_CON(4), 9, GFLAGS),
0807 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
0808 RK3399_CLKGATE_CON(16), 10, GFLAGS),
0809 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED,
0810 RK3399_CLKGATE_CON(16), 11, GFLAGS),
0811
0812 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
0813 RK3399_CLKGATE_CON(16), 8, GFLAGS),
0814 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED,
0815 RK3399_CLKGATE_CON(16), 9, GFLAGS),
0816
0817
0818 COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
0819 RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
0820 RK3399_CLKGATE_CON(3), 7, GFLAGS),
0821 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
0822 RK3399_CLKGATE_CON(19), 0, GFLAGS),
0823 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED,
0824 RK3399_CLKGATE_CON(19), 1, GFLAGS),
0825
0826
0827 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
0828 RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
0829 RK3399_CLKGATE_CON(13), 0, GFLAGS),
0830 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0,
0831 RK3399_CLKGATE_CON(30), 8, GFLAGS),
0832 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0,
0833 RK3399_CLKGATE_CON(30), 10, GFLAGS),
0834 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0,
0835 RK3399_CLKGATE_CON(30), 11, GFLAGS),
0836 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0,
0837 RK3399_CLKGATE_CON(13), 1, GFLAGS),
0838
0839
0840 GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
0841 RK3399_CLKGATE_CON(5), 1, GFLAGS),
0842 GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
0843 RK3399_CLKGATE_CON(5), 0, GFLAGS),
0844 COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
0845 RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
0846 RK3399_CLKGATE_CON(5), 2, GFLAGS),
0847 COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
0848 RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
0849 RK3399_CLKGATE_CON(5), 3, GFLAGS),
0850 COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
0851 RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
0852 RK3399_CLKGATE_CON(5), 4, GFLAGS),
0853
0854 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
0855 RK3399_CLKGATE_CON(20), 2, GFLAGS),
0856 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
0857 RK3399_CLKGATE_CON(20), 10, GFLAGS),
0858 GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
0859 RK3399_CLKGATE_CON(20), 12, GFLAGS),
0860
0861 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0,
0862 RK3399_CLKGATE_CON(20), 5, GFLAGS),
0863 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0,
0864 RK3399_CLKGATE_CON(20), 6, GFLAGS),
0865 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0,
0866 RK3399_CLKGATE_CON(20), 7, GFLAGS),
0867 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0,
0868 RK3399_CLKGATE_CON(20), 8, GFLAGS),
0869 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0,
0870 RK3399_CLKGATE_CON(20), 9, GFLAGS),
0871 GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED,
0872 RK3399_CLKGATE_CON(20), 13, GFLAGS),
0873 GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
0874 RK3399_CLKGATE_CON(20), 15, GFLAGS),
0875
0876 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED,
0877 RK3399_CLKGATE_CON(20), 4, GFLAGS),
0878 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0,
0879 RK3399_CLKGATE_CON(20), 11, GFLAGS),
0880 GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED,
0881 RK3399_CLKGATE_CON(20), 14, GFLAGS),
0882 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0,
0883 RK3399_CLKGATE_CON(31), 8, GFLAGS),
0884
0885
0886 COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
0887 RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
0888 RK3399_CLKGATE_CON(12), 13, GFLAGS),
0889 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
0890 RK3399_CLKGATE_CON(33), 8, GFLAGS),
0891 GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED,
0892 RK3399_CLKGATE_CON(33), 9, GFLAGS),
0893
0894 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
0895 RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
0896 RK3399_CLKGATE_CON(6), 0, GFLAGS),
0897
0898 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
0899 RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
0900 RK3399_CLKGATE_CON(6), 1, GFLAGS),
0901
0902 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
0903 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
0904
0905 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
0906 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
0907
0908
0909 COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0,
0910 RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
0911 RK3399_CLKGATE_CON(6), 2, GFLAGS),
0912
0913 COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0,
0914 RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
0915 RK3399_CLKGATE_CON(12), 6, GFLAGS),
0916 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
0917 RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
0918
0919 COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0,
0920 RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
0921 RK3399_CLKGATE_CON(6), 3, GFLAGS),
0922 MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
0923 RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
0924
0925
0926 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0,
0927 RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
0928 RK3399_CLKGATE_CON(6), 14, GFLAGS),
0929
0930 GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
0931 RK3399_CLKGATE_CON(6), 13, GFLAGS),
0932 GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
0933 RK3399_CLKGATE_CON(6), 12, GFLAGS),
0934 COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
0935 RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
0936 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
0937 RK3399_CLKGATE_CON(32), 8, GFLAGS),
0938 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED,
0939 RK3399_CLKGATE_CON(32), 9, GFLAGS),
0940 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
0941 RK3399_CLKGATE_CON(32), 10, GFLAGS),
0942
0943
0944 GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
0945 RK3399_CLKGATE_CON(7), 1, GFLAGS),
0946 GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
0947 RK3399_CLKGATE_CON(7), 0, GFLAGS),
0948 COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,
0949 RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
0950 RK3399_CLKGATE_CON(7), 2, GFLAGS),
0951 COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED,
0952 RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
0953 RK3399_CLKGATE_CON(7), 3, GFLAGS),
0954 COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
0955 RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
0956 RK3399_CLKGATE_CON(7), 4, GFLAGS),
0957
0958
0959 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
0960 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
0961 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
0962 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
0963 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
0964 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
0965 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
0966 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
0967 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS),
0968 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
0969 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
0970 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS),
0971
0972
0973 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
0974 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS),
0975 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS),
0976 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS),
0977 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS),
0978 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
0979
0980
0981 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS),
0982
0983
0984 COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,
0985 RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
0986 RK3399_CLKGATE_CON(7), 7, GFLAGS),
0987
0988 COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0,
0989 RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
0990 RK3399_CLKGATE_CON(7), 8, GFLAGS),
0991
0992
0993 GATE(0, "cpll_fclk_cm0s_src", "cpll", 0,
0994 RK3399_CLKGATE_CON(7), 6, GFLAGS),
0995 GATE(0, "gpll_fclk_cm0s_src", "gpll", 0,
0996 RK3399_CLKGATE_CON(7), 5, GFLAGS),
0997 COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0,
0998 RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
0999 RK3399_CLKGATE_CON(7), 9, GFLAGS),
1000
1001
1002 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS),
1003 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS),
1004 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS),
1005 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS),
1006 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS),
1007
1008
1009 GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
1010 RK3399_CLKGATE_CON(8), 1, GFLAGS),
1011 GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
1012 RK3399_CLKGATE_CON(8), 0, GFLAGS),
1013 COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,
1014 RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
1015 COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED,
1016 RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
1017 RK3399_CLKGATE_CON(8), 2, GFLAGS),
1018
1019
1020 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS),
1021 GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS),
1022 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
1023 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS),
1024 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS),
1025 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS),
1026 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS),
1027 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS),
1028 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS),
1029
1030
1031 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
1032 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
1033 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
1034 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
1035 GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
1036 GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
1037 GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
1038 GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
1039 GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
1040 GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
1041 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
1042 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
1043 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
1044 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
1045 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
1046 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
1047 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
1048 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
1049 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
1050 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
1051 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS),
1052
1053
1054 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
1055 RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
1056 RK3399_CLKGATE_CON(9), 11, GFLAGS),
1057
1058
1059 COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0,
1060 RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
1061 RK3399_CLKGATE_CON(9), 10, GFLAGS),
1062
1063
1064 MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1065 RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
1066 COMPOSITE(SCLK_TESTCLKOUT1, "clk_testout1", mux_clk_testout1_p, 0,
1067 RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
1068 RK3399_CLKGATE_CON(13), 14, GFLAGS),
1069
1070 MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1071 RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
1072 COMPOSITE(SCLK_TESTCLKOUT2, "clk_testout2", mux_clk_testout2_p, 0,
1073 RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
1074 RK3399_CLKGATE_CON(13), 15, GFLAGS),
1075
1076
1077 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1078 RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
1079 RK3399_CLKGATE_CON(11), 0, GFLAGS),
1080 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
1081 RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
1082 RK3399_CLKGATE_CON(11), 1, GFLAGS),
1083
1084 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED,
1085 RK3399_CLKGATE_CON(29), 0, GFLAGS),
1086
1087 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0,
1088 RK3399_CLKGATE_CON(29), 1, GFLAGS),
1089 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0,
1090 RK3399_CLKGATE_CON(29), 2, GFLAGS),
1091 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED,
1092 RK3399_CLKGATE_CON(29), 12, GFLAGS),
1093
1094
1095 COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
1096 RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
1097 RK3399_CLKGATE_CON(11), 12, GFLAGS),
1098 COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0,
1099 RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
1100 RK3399_CLKGATE_CON(11), 3, GFLAGS),
1101 COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0,
1102 RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
1103 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1104
1105 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED,
1106 RK3399_CLKGATE_CON(29), 4, GFLAGS),
1107 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0,
1108 RK3399_CLKGATE_CON(29), 10, GFLAGS),
1109
1110 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED,
1111 RK3399_CLKGATE_CON(29), 5, GFLAGS),
1112 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0,
1113 RK3399_CLKGATE_CON(29), 9, GFLAGS),
1114
1115 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED,
1116 RK3399_CLKGATE_CON(29), 3, GFLAGS),
1117 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0,
1118 RK3399_CLKGATE_CON(29), 6, GFLAGS),
1119 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0,
1120 RK3399_CLKGATE_CON(29), 7, GFLAGS),
1121 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0,
1122 RK3399_CLKGATE_CON(29), 8, GFLAGS),
1123 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0,
1124 RK3399_CLKGATE_CON(29), 11, GFLAGS),
1125
1126
1127 COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0,
1128 RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
1129 RK3399_CLKGATE_CON(11), 8, GFLAGS),
1130
1131 COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
1132 RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
1133 RK3399_CLKGATE_CON(11), 11, GFLAGS),
1134 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
1135 RK3399_CLKGATE_CON(32), 12, GFLAGS),
1136 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0,
1137 RK3399_CLKGATE_CON(32), 13, GFLAGS),
1138
1139
1140 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
1141 RK3399_CLKGATE_CON(11), 6, GFLAGS),
1142
1143 COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0,
1144 RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
1145 RK3399_CLKGATE_CON(11), 7, GFLAGS),
1146
1147
1148 COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
1149 RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
1150 RK3399_CLKGATE_CON(10), 8, GFLAGS),
1151 COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
1152 RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
1153 RK3399_CLKGATE_CON(10), 9, GFLAGS),
1154
1155 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0,
1156 RK3399_CLKGATE_CON(28), 3, GFLAGS),
1157 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1158 RK3399_CLKGATE_CON(28), 1, GFLAGS),
1159
1160 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0,
1161 RK3399_CLKGATE_CON(28), 2, GFLAGS),
1162 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1163 RK3399_CLKGATE_CON(28), 0, GFLAGS),
1164
1165 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
1166 RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1167 RK3399_CLKGATE_CON(10), 12, GFLAGS),
1168
1169 COMPOSITE_FRACMUX_NOGATE(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0,
1170 RK3399_CLKSEL_CON(106), 0,
1171 &rk3399_dclk_vop0_fracmux),
1172
1173 COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0,
1174 RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
1175 RK3399_CLKGATE_CON(10), 14, GFLAGS),
1176
1177
1178 COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
1179 RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1180 RK3399_CLKGATE_CON(10), 10, GFLAGS),
1181 COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
1182 RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
1183 RK3399_CLKGATE_CON(10), 11, GFLAGS),
1184
1185 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0,
1186 RK3399_CLKGATE_CON(28), 7, GFLAGS),
1187 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1188 RK3399_CLKGATE_CON(28), 5, GFLAGS),
1189
1190 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0,
1191 RK3399_CLKGATE_CON(28), 6, GFLAGS),
1192 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1193 RK3399_CLKGATE_CON(28), 4, GFLAGS),
1194
1195 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0,
1196 RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1197 RK3399_CLKGATE_CON(10), 13, GFLAGS),
1198
1199 COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,
1200 RK3399_CLKSEL_CON(107), 0,
1201 &rk3399_dclk_vop1_fracmux),
1202
1203 COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,
1204 RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
1205 RK3399_CLKGATE_CON(10), 15, GFLAGS),
1206
1207
1208 COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0,
1209 RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
1210 RK3399_CLKGATE_CON(12), 8, GFLAGS),
1211 COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0,
1212 RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
1213 RK3399_CLKGATE_CON(12), 9, GFLAGS),
1214
1215 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED,
1216 RK3399_CLKGATE_CON(27), 1, GFLAGS),
1217 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0,
1218 RK3399_CLKGATE_CON(27), 5, GFLAGS),
1219 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0,
1220 RK3399_CLKGATE_CON(27), 7, GFLAGS),
1221
1222 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED,
1223 RK3399_CLKGATE_CON(27), 0, GFLAGS),
1224 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0,
1225 RK3399_CLKGATE_CON(27), 4, GFLAGS),
1226
1227 COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0,
1228 RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
1229 RK3399_CLKGATE_CON(11), 4, GFLAGS),
1230
1231 COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0,
1232 RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
1233 RK3399_CLKGATE_CON(12), 10, GFLAGS),
1234 COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0,
1235 RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
1236 RK3399_CLKGATE_CON(12), 11, GFLAGS),
1237
1238 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED,
1239 RK3399_CLKGATE_CON(27), 3, GFLAGS),
1240
1241 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED,
1242 RK3399_CLKGATE_CON(27), 2, GFLAGS),
1243 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0,
1244 RK3399_CLKGATE_CON(27), 8, GFLAGS),
1245
1246 COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0,
1247 RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
1248 RK3399_CLKGATE_CON(11), 5, GFLAGS),
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0,
1259 RK3399_CLKGATE_CON(27), 6, GFLAGS),
1260
1261
1262 COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
1263 RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
1264 RK3399_CLKGATE_CON(10), 7, GFLAGS),
1265
1266 COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
1267 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
1268
1269
1270 COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1271 RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
1272 RK3399_CLKGATE_CON(12), 12, GFLAGS),
1273
1274 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1275 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS),
1276 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
1277 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
1278 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
1279 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
1280
1281
1282
1283 DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1284 RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1285
1286 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
1287 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
1288 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
1289 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
1290 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
1291
1292 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
1293 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
1294 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS),
1295 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS),
1296 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS),
1297 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS),
1298 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS),
1299 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
1300 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
1301
1302
1303 SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_alive"),
1304
1305 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
1306 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
1307
1308 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS),
1309 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS),
1310 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS),
1311 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS),
1312
1313
1314 MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
1315 RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
1316 COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0,
1317 RK3399_CLKSEL_CON(105), 0,
1318 RK3399_CLKGATE_CON(13), 9, GFLAGS),
1319
1320 DIV(0, "clk_test_24m", "xin24m", 0,
1321 RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1322
1323
1324 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
1325 RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
1326 RK3399_CLKGATE_CON(9), 12, GFLAGS),
1327
1328 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
1329 RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
1330 RK3399_CLKGATE_CON(9), 13, GFLAGS),
1331
1332 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
1333 RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
1334 RK3399_CLKGATE_CON(9), 14, GFLAGS),
1335
1336 COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
1337 RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
1338 RK3399_CLKGATE_CON(9), 15, GFLAGS),
1339
1340 COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
1341 RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
1342 RK3399_CLKGATE_CON(13), 13, GFLAGS),
1343
1344
1345 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
1346 RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
1347 RK3399_CLKGATE_CON(10), 0, GFLAGS),
1348
1349 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
1350 RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
1351 RK3399_CLKGATE_CON(10), 2, GFLAGS),
1352
1353 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
1354 RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
1355 RK3399_CLKGATE_CON(10), 4, GFLAGS),
1356
1357 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
1358 RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
1359 RK3399_CLKGATE_CON(10), 1, GFLAGS),
1360
1361 COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
1362 RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
1363 RK3399_CLKGATE_CON(10), 3, GFLAGS),
1364
1365 COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
1366 RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
1367 RK3399_CLKGATE_CON(10), 5, GFLAGS),
1368
1369
1370 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS),
1371 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS),
1372 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS),
1373 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS),
1374 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS),
1375 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS),
1376 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS),
1377 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS),
1378 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS),
1379 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS),
1380 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS),
1381 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS),
1382
1383
1384
1385 COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
1386 RK3399_CLKSEL_CON(58), 0, 5, DFLAGS,
1387 RK3399_CLKGATE_CON(13), 11, GFLAGS),
1388
1389
1390 GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3),
1391 0, GFLAGS),
1392 GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3),
1393 1, GFLAGS),
1394 GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3),
1395 2, GFLAGS),
1396 GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3),
1397 3, GFLAGS),
1398 COMPOSITE_DDRCLK(SCLK_DDRC, "sclk_ddrc", mux_ddrclk_p, 0,
1399 RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP),
1400 };
1401
1402 static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1403
1404
1405
1406
1407 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
1408 RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
1409
1410 COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0,
1411 RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
1412
1413 COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0,
1414 RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
1415 RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
1416
1417 COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
1418 RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
1419 RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
1420
1421 COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", 0,
1422 RK3399_PMU_CLKSEL_CON(7), 0,
1423 &rk3399_pmuclk_wifi_fracmux),
1424
1425 MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
1426 RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
1427
1428 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
1429 RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
1430 RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
1431
1432 COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
1433 RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1434 RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
1435
1436 COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
1437 RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
1438 RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
1439
1440 DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
1441 RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
1442 MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
1443 RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
1444
1445 COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0,
1446 RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
1447 RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
1448
1449 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0,
1450 RK3399_PMU_CLKSEL_CON(6), 0,
1451 RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
1452 &rk3399_uart4_pmu_fracmux),
1453
1454 DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
1455 RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
1456
1457
1458 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
1459 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
1460
1461 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
1462
1463 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
1464 GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS),
1465 GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
1466 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
1467 GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
1468 GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
1469 GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
1470 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
1471 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
1472 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
1473 GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
1474 GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
1475 GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
1476 GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
1477 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
1478 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
1479
1480 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
1481 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
1482 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
1483 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
1484 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
1485 };
1486
1487 static const char *const rk3399_cru_critical_clocks[] __initconst = {
1488 "aclk_cci_pre",
1489 "aclk_gic",
1490 "aclk_gic_noc",
1491 "aclk_hdcp_noc",
1492 "hclk_hdcp_noc",
1493 "pclk_hdcp_noc",
1494 "pclk_perilp0",
1495 "pclk_perilp0",
1496 "hclk_perilp0",
1497 "hclk_perilp0_noc",
1498 "pclk_perilp1",
1499 "pclk_perilp1_noc",
1500 "pclk_perihp",
1501 "pclk_perihp_noc",
1502 "hclk_perihp",
1503 "aclk_perihp",
1504 "aclk_perihp_noc",
1505 "aclk_perilp0",
1506 "aclk_perilp0_noc",
1507 "hclk_perilp1",
1508 "hclk_perilp1_noc",
1509 "aclk_dmac0_perilp",
1510 "aclk_emmc_noc",
1511 "gpll_hclk_perilp1_src",
1512 "gpll_aclk_perilp0_src",
1513 "gpll_aclk_perihp_src",
1514 "aclk_vio_noc",
1515
1516
1517 "sclk_ddrc",
1518
1519 "armclkl",
1520 "armclkb",
1521 };
1522
1523 static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
1524 "ppll",
1525 "pclk_pmu_src",
1526 "fclk_cm0s_src_pmu",
1527 "clk_timer_src_pmu",
1528 "pclk_rkpwm_pmu",
1529 };
1530
1531 static void __init rk3399_clk_init(struct device_node *np)
1532 {
1533 struct rockchip_clk_provider *ctx;
1534 void __iomem *reg_base;
1535
1536 reg_base = of_iomap(np, 0);
1537 if (!reg_base) {
1538 pr_err("%s: could not map cru region\n", __func__);
1539 return;
1540 }
1541
1542 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1543 if (IS_ERR(ctx)) {
1544 pr_err("%s: rockchip clk init failed\n", __func__);
1545 iounmap(reg_base);
1546 return;
1547 }
1548
1549 rockchip_clk_register_plls(ctx, rk3399_pll_clks,
1550 ARRAY_SIZE(rk3399_pll_clks), -1);
1551
1552 rockchip_clk_register_branches(ctx, rk3399_clk_branches,
1553 ARRAY_SIZE(rk3399_clk_branches));
1554
1555 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
1556 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
1557 &rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
1558 ARRAY_SIZE(rk3399_cpuclkl_rates));
1559
1560 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
1561 mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
1562 &rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
1563 ARRAY_SIZE(rk3399_cpuclkb_rates));
1564
1565 rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
1566 ARRAY_SIZE(rk3399_cru_critical_clocks));
1567
1568 rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
1569 ROCKCHIP_SOFTRST_HIWORD_MASK);
1570
1571 rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
1572
1573 rockchip_clk_of_add_provider(np, ctx);
1574 }
1575 CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
1576
1577 static void __init rk3399_pmu_clk_init(struct device_node *np)
1578 {
1579 struct rockchip_clk_provider *ctx;
1580 void __iomem *reg_base;
1581
1582 reg_base = of_iomap(np, 0);
1583 if (!reg_base) {
1584 pr_err("%s: could not map cru pmu region\n", __func__);
1585 return;
1586 }
1587
1588 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1589 if (IS_ERR(ctx)) {
1590 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1591 iounmap(reg_base);
1592 return;
1593 }
1594
1595 rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
1596 ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
1597
1598 rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
1599 ARRAY_SIZE(rk3399_clk_pmu_branches));
1600
1601 rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks,
1602 ARRAY_SIZE(rk3399_pmucru_critical_clocks));
1603
1604 rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
1605 ROCKCHIP_SOFTRST_HIWORD_MASK);
1606
1607 rockchip_clk_of_add_provider(np, ctx);
1608 }
1609 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
1610
1611 struct clk_rk3399_inits {
1612 void (*inits)(struct device_node *np);
1613 };
1614
1615 static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
1616 .inits = rk3399_pmu_clk_init,
1617 };
1618
1619 static const struct clk_rk3399_inits clk_rk3399_cru_init = {
1620 .inits = rk3399_clk_init,
1621 };
1622
1623 static const struct of_device_id clk_rk3399_match_table[] = {
1624 {
1625 .compatible = "rockchip,rk3399-cru",
1626 .data = &clk_rk3399_cru_init,
1627 }, {
1628 .compatible = "rockchip,rk3399-pmucru",
1629 .data = &clk_rk3399_pmucru_init,
1630 },
1631 { }
1632 };
1633
1634 static int __init clk_rk3399_probe(struct platform_device *pdev)
1635 {
1636 struct device_node *np = pdev->dev.of_node;
1637 const struct of_device_id *match;
1638 const struct clk_rk3399_inits *init_data;
1639
1640 match = of_match_device(clk_rk3399_match_table, &pdev->dev);
1641 if (!match || !match->data)
1642 return -EINVAL;
1643
1644 init_data = match->data;
1645 if (init_data->inits)
1646 init_data->inits(np);
1647
1648 return 0;
1649 }
1650
1651 static struct platform_driver clk_rk3399_driver = {
1652 .driver = {
1653 .name = "clk-rk3399",
1654 .of_match_table = clk_rk3399_match_table,
1655 .suppress_bind_attrs = true,
1656 },
1657 };
1658 builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
