clk/rockchip/clk-rk3368.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
0004  */
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/io.h>
0008 #include <linux/of.h>
0009 #include <linux/of_address.h>
0010 #include <linux/platform_device.h>
0011 #include <dt-bindings/clock/rk3368-cru.h>
0012 #include "clk.h"
0013
0014 #define RK3368_GRF_SOC_STATUS0  0x480
0015
0016 enum rk3368_plls {
0017     apllb, aplll, dpll, cpll, gpll, npll,
0018 };
0019
0020 static struct rockchip_pll_rate_table rk3368_pll_rates[] = {
0021     RK3066_PLL_RATE(2208000000, 1, 92, 1),
0022     RK3066_PLL_RATE(2184000000, 1, 91, 1),
0023     RK3066_PLL_RATE(2160000000, 1, 90, 1),
0024     RK3066_PLL_RATE(2136000000, 1, 89, 1),
0025     RK3066_PLL_RATE(2112000000, 1, 88, 1),
0026     RK3066_PLL_RATE(2088000000, 1, 87, 1),
0027     RK3066_PLL_RATE(2064000000, 1, 86, 1),
0028     RK3066_PLL_RATE(2040000000, 1, 85, 1),
0029     RK3066_PLL_RATE(2016000000, 1, 84, 1),
0030     RK3066_PLL_RATE(1992000000, 1, 83, 1),
0031     RK3066_PLL_RATE(1968000000, 1, 82, 1),
0032     RK3066_PLL_RATE(1944000000, 1, 81, 1),
0033     RK3066_PLL_RATE(1920000000, 1, 80, 1),
0034     RK3066_PLL_RATE(1896000000, 1, 79, 1),
0035     RK3066_PLL_RATE(1872000000, 1, 78, 1),
0036     RK3066_PLL_RATE(1848000000, 1, 77, 1),
0037     RK3066_PLL_RATE(1824000000, 1, 76, 1),
0038     RK3066_PLL_RATE(1800000000, 1, 75, 1),
0039     RK3066_PLL_RATE(1776000000, 1, 74, 1),
0040     RK3066_PLL_RATE(1752000000, 1, 73, 1),
0041     RK3066_PLL_RATE(1728000000, 1, 72, 1),
0042     RK3066_PLL_RATE(1704000000, 1, 71, 1),
0043     RK3066_PLL_RATE(1680000000, 1, 70, 1),
0044     RK3066_PLL_RATE(1656000000, 1, 69, 1),
0045     RK3066_PLL_RATE(1632000000, 1, 68, 1),
0046     RK3066_PLL_RATE(1608000000, 1, 67, 1),
0047     RK3066_PLL_RATE(1560000000, 1, 65, 1),
0048     RK3066_PLL_RATE(1512000000, 1, 63, 1),
0049     RK3066_PLL_RATE(1488000000, 1, 62, 1),
0050     RK3066_PLL_RATE(1464000000, 1, 61, 1),
0051     RK3066_PLL_RATE(1440000000, 1, 60, 1),
0052     RK3066_PLL_RATE(1416000000, 1, 59, 1),
0053     RK3066_PLL_RATE(1392000000, 1, 58, 1),
0054     RK3066_PLL_RATE(1368000000, 1, 57, 1),
0055     RK3066_PLL_RATE(1344000000, 1, 56, 1),
0056     RK3066_PLL_RATE(1320000000, 1, 55, 1),
0057     RK3066_PLL_RATE(1296000000, 1, 54, 1),
0058     RK3066_PLL_RATE(1272000000, 1, 53, 1),
0059     RK3066_PLL_RATE(1248000000, 1, 52, 1),
0060     RK3066_PLL_RATE(1224000000, 1, 51, 1),
0061     RK3066_PLL_RATE(1200000000, 1, 50, 1),
0062     RK3066_PLL_RATE(1176000000, 1, 49, 1),
0063     RK3066_PLL_RATE(1128000000, 1, 47, 1),
0064     RK3066_PLL_RATE(1104000000, 1, 46, 1),
0065     RK3066_PLL_RATE(1008000000, 1, 84, 2),
0066     RK3066_PLL_RATE( 912000000, 1, 76, 2),
0067     RK3066_PLL_RATE( 888000000, 1, 74, 2),
0068     RK3066_PLL_RATE( 816000000, 1, 68, 2),
0069     RK3066_PLL_RATE( 792000000, 1, 66, 2),
0070     RK3066_PLL_RATE( 696000000, 1, 58, 2),
0071     RK3066_PLL_RATE( 672000000, 1, 56, 2),
0072     RK3066_PLL_RATE( 648000000, 1, 54, 2),
0073     RK3066_PLL_RATE( 624000000, 1, 52, 2),
0074     RK3066_PLL_RATE( 600000000, 1, 50, 2),
0075     RK3066_PLL_RATE( 576000000, 1, 48, 2),
0076     RK3066_PLL_RATE( 552000000, 1, 46, 2),
0077     RK3066_PLL_RATE( 528000000, 1, 88, 4),
0078     RK3066_PLL_RATE( 504000000, 1, 84, 4),
0079     RK3066_PLL_RATE( 480000000, 1, 80, 4),
0080     RK3066_PLL_RATE( 456000000, 1, 76, 4),
0081     RK3066_PLL_RATE( 408000000, 1, 68, 4),
0082     RK3066_PLL_RATE( 312000000, 1, 52, 4),
0083     RK3066_PLL_RATE( 252000000, 1, 84, 8),
0084     RK3066_PLL_RATE( 216000000, 1, 72, 8),
0085     RK3066_PLL_RATE( 126000000, 2, 84, 8),
0086     RK3066_PLL_RATE(  48000000, 2, 32, 8),
0087     { /* sentinel */ },
0088 };
0089
0090 PNAME(mux_pll_p)        = { "xin24m", "xin32k" };
0091 PNAME(mux_armclkb_p)        = { "apllb_core", "gpllb_core" };
0092 PNAME(mux_armclkl_p)        = { "aplll_core", "gplll_core" };
0093 PNAME(mux_ddrphy_p)     = { "dpll_ddr", "gpll_ddr" };
0094 PNAME(mux_cs_src_p)     = { "apllb_cs", "aplll_cs", "gpll_cs"};
0095 PNAME(mux_aclk_bus_src_p)   = { "cpll_aclk_bus", "gpll_aclk_bus" };
0096
0097 PNAME(mux_pll_src_cpll_gpll_p)      = { "cpll", "gpll" };
0098 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
0099 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
0100 PNAME(mux_pll_src_cpll_gpll_usb_p)  = { "cpll", "gpll", "usbphy_480m" };
0101 PNAME(mux_pll_src_cpll_gpll_usb_usb_p)  = { "cpll", "gpll", "usbphy_480m",
0102                         "usbphy_480m" };
0103 PNAME(mux_pll_src_cpll_gpll_usb_npll_p) = { "cpll", "gpll", "usbphy_480m",
0104                         "npll" };
0105 PNAME(mux_pll_src_cpll_gpll_npll_npll_p) = { "cpll", "gpll", "npll", "npll" };
0106 PNAME(mux_pll_src_cpll_gpll_npll_usb_p) = { "cpll", "gpll", "npll",
0107                         "usbphy_480m" };
0108
0109 PNAME(mux_i2s_8ch_pre_p)    = { "i2s_8ch_src", "i2s_8ch_frac",
0110                     "ext_i2s", "xin12m" };
0111 PNAME(mux_i2s_8ch_clkout_p) = { "i2s_8ch_pre", "xin12m" };
0112 PNAME(mux_i2s_2ch_p)        = { "i2s_2ch_src", "i2s_2ch_frac",
0113                     "dummy", "xin12m" };
0114 PNAME(mux_spdif_8ch_p)      = { "spdif_8ch_pre", "spdif_8ch_frac",
0115                     "ext_i2s", "xin12m" };
0116 PNAME(mux_edp_24m_p)        = { "xin24m", "dummy" };
0117 PNAME(mux_vip_out_p)        = { "vip_src", "xin24m" };
0118 PNAME(mux_usbphy480m_p)     = { "usbotg_out", "xin24m" };
0119 PNAME(mux_hsic_usbphy480m_p)    = { "usbotg_out", "dummy" };
0120 PNAME(mux_hsicphy480m_p)    = { "cpll", "gpll", "usbphy_480m" };
0121 PNAME(mux_uart0_p)      = { "uart0_src", "uart0_frac", "xin24m" };
0122 PNAME(mux_uart1_p)      = { "uart1_src", "uart1_frac", "xin24m" };
0123 PNAME(mux_uart2_p)      = { "uart2_src", "xin24m" };
0124 PNAME(mux_uart3_p)      = { "uart3_src", "uart3_frac", "xin24m" };
0125 PNAME(mux_uart4_p)      = { "uart4_src", "uart4_frac", "xin24m" };
0126 PNAME(mux_mac_p)        = { "mac_pll_src", "ext_gmac" };
0127 PNAME(mux_mmc_src_p)        = { "cpll", "gpll", "usbphy_480m", "xin24m" };
0128
0129 static struct rockchip_pll_clock rk3368_pll_clks[] __initdata = {
0130     [apllb] = PLL(pll_rk3066, PLL_APLLB, "apllb", mux_pll_p, 0, RK3368_PLL_CON(0),
0131              RK3368_PLL_CON(3), 8, 1, 0, rk3368_pll_rates),
0132     [aplll] = PLL(pll_rk3066, PLL_APLLL, "aplll", mux_pll_p, 0, RK3368_PLL_CON(4),
0133              RK3368_PLL_CON(7), 8, 0, 0, rk3368_pll_rates),
0134     [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
0135              RK3368_PLL_CON(11), 8, 2, 0, NULL),
0136     [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
0137              RK3368_PLL_CON(15), 8, 3, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
0138     [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
0139              RK3368_PLL_CON(19), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
0140     [npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3368_PLL_CON(20),
0141              RK3368_PLL_CON(23), 8, 5, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
0142 };
0143
0144 static struct clk_div_table div_ddrphy_t[] = {
0145     { .val = 0, .div = 1 },
0146     { .val = 1, .div = 2 },
0147     { .val = 3, .div = 4 },
0148     { /* sentinel */ },
0149 };
0150
0151 #define MFLAGS CLK_MUX_HIWORD_MASK
0152 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
0153 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
0154 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
0155
0156 static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
0157     .core_reg[0] = RK3368_CLKSEL_CON(0),
0158     .div_core_shift[0] = 0,
0159     .div_core_mask[0] = 0x1f,
0160     .num_cores = 1,
0161     .mux_core_alt = 1,
0162     .mux_core_main = 0,
0163     .mux_core_shift = 7,
0164     .mux_core_mask = 0x1,
0165 };
0166
0167 static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
0168     .core_reg[0] = RK3368_CLKSEL_CON(2),
0169     .div_core_shift[0] = 0,
0170     .mux_core_alt = 1,
0171     .num_cores = 1,
0172     .mux_core_main = 0,
0173     .div_core_mask[0] = 0x1f,
0174     .mux_core_shift = 7,
0175     .mux_core_mask = 0x1,
0176 };
0177
0178 #define RK3368_DIV_ACLKM_MASK       0x1f
0179 #define RK3368_DIV_ACLKM_SHIFT      8
0180 #define RK3368_DIV_ATCLK_MASK       0x1f
0181 #define RK3368_DIV_ATCLK_SHIFT      0
0182 #define RK3368_DIV_PCLK_DBG_MASK    0x1f
0183 #define RK3368_DIV_PCLK_DBG_SHIFT   8
0184
0185 #define RK3368_CLKSEL0(_offs, _aclkm)                   \
0186     {                               \
0187         .reg = RK3368_CLKSEL_CON(0 + _offs),            \
0188         .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \
0189                 RK3368_DIV_ACLKM_SHIFT),        \
0190     }
0191 #define RK3368_CLKSEL1(_offs, _atclk, _pdbg)                \
0192     {                               \
0193         .reg = RK3368_CLKSEL_CON(1 + _offs),            \
0194         .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \
0195                 RK3368_DIV_ATCLK_SHIFT) |       \
0196                HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK,   \
0197                 RK3368_DIV_PCLK_DBG_SHIFT),     \
0198     }
0199
0200 /* cluster_b: aclkm in clksel0, rest in clksel1 */
0201 #define RK3368_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg)      \
0202     {                               \
0203         .prate = _prate,                    \
0204         .divs = {                       \
0205             RK3368_CLKSEL0(0, _aclkm),          \
0206             RK3368_CLKSEL1(0, _atclk, _pdbg),       \
0207         },                          \
0208     }
0209
0210 /* cluster_l: aclkm in clksel2, rest in clksel3 */
0211 #define RK3368_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg)      \
0212     {                               \
0213         .prate = _prate,                    \
0214         .divs = {                       \
0215             RK3368_CLKSEL0(2, _aclkm),          \
0216             RK3368_CLKSEL1(2, _atclk, _pdbg),       \
0217         },                          \
0218     }
0219
0220 static struct rockchip_cpuclk_rate_table rk3368_cpuclkb_rates[] __initdata = {
0221     RK3368_CPUCLKB_RATE(1512000000, 1, 5, 5),
0222     RK3368_CPUCLKB_RATE(1488000000, 1, 4, 4),
0223     RK3368_CPUCLKB_RATE(1416000000, 1, 4, 4),
0224     RK3368_CPUCLKB_RATE(1200000000, 1, 3, 3),
0225     RK3368_CPUCLKB_RATE(1008000000, 1, 3, 3),
0226     RK3368_CPUCLKB_RATE( 816000000, 1, 2, 2),
0227     RK3368_CPUCLKB_RATE( 696000000, 1, 2, 2),
0228     RK3368_CPUCLKB_RATE( 600000000, 1, 1, 1),
0229     RK3368_CPUCLKB_RATE( 408000000, 1, 1, 1),
0230     RK3368_CPUCLKB_RATE( 312000000, 1, 1, 1),
0231 };
0232
0233 static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
0234     RK3368_CPUCLKL_RATE(1512000000, 1, 6, 6),
0235     RK3368_CPUCLKL_RATE(1488000000, 1, 5, 5),
0236     RK3368_CPUCLKL_RATE(1416000000, 1, 5, 5),
0237     RK3368_CPUCLKL_RATE(1200000000, 1, 4, 4),
0238     RK3368_CPUCLKL_RATE(1008000000, 1, 4, 4),
0239     RK3368_CPUCLKL_RATE( 816000000, 1, 3, 3),
0240     RK3368_CPUCLKL_RATE( 696000000, 1, 2, 2),
0241     RK3368_CPUCLKL_RATE( 600000000, 1, 2, 2),
0242     RK3368_CPUCLKL_RATE( 408000000, 1, 1, 1),
0243     RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1),
0244 };
0245
0246 static struct rockchip_clk_branch rk3368_i2s_8ch_fracmux __initdata =
0247     MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
0248         RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
0249
0250 static struct rockchip_clk_branch rk3368_spdif_8ch_fracmux __initdata =
0251     MUX(0, "spdif_8ch_pre", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
0252         RK3368_CLKSEL_CON(31), 8, 2, MFLAGS);
0253
0254 static struct rockchip_clk_branch rk3368_i2s_2ch_fracmux __initdata =
0255     MUX(0, "i2s_2ch_pre", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
0256         RK3368_CLKSEL_CON(53), 8, 2, MFLAGS);
0257
0258 static struct rockchip_clk_branch rk3368_uart0_fracmux __initdata =
0259     MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
0260         RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
0261
0262 static struct rockchip_clk_branch rk3368_uart1_fracmux __initdata =
0263     MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
0264         RK3368_CLKSEL_CON(35), 8, 2, MFLAGS);
0265
0266 static struct rockchip_clk_branch rk3368_uart3_fracmux __initdata =
0267     MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
0268         RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
0269
0270 static struct rockchip_clk_branch rk3368_uart4_fracmux __initdata =
0271     MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
0272         RK3368_CLKSEL_CON(41), 8, 2, MFLAGS);
0273
0274 static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
0275     /*
0276      * Clock-Architecture Diagram 2
0277      */
0278
0279     FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
0280
0281     MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, CLK_SET_RATE_PARENT,
0282             RK3368_CLKSEL_CON(13), 8, 1, MFLAGS),
0283
0284     GATE(0, "apllb_core", "apllb", CLK_IGNORE_UNUSED,
0285             RK3368_CLKGATE_CON(0), 0, GFLAGS),
0286     GATE(0, "gpllb_core", "gpll", CLK_IGNORE_UNUSED,
0287             RK3368_CLKGATE_CON(0), 1, GFLAGS),
0288
0289     GATE(0, "aplll_core", "aplll", CLK_IGNORE_UNUSED,
0290             RK3368_CLKGATE_CON(0), 4, GFLAGS),
0291     GATE(0, "gplll_core", "gpll", CLK_IGNORE_UNUSED,
0292             RK3368_CLKGATE_CON(0), 5, GFLAGS),
0293
0294     DIV(0, "aclkm_core_b", "armclkb", 0,
0295             RK3368_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
0296     DIV(0, "atclk_core_b", "armclkb", 0,
0297             RK3368_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
0298     DIV(0, "pclk_dbg_b", "armclkb", 0,
0299             RK3368_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
0300
0301     DIV(0, "aclkm_core_l", "armclkl", 0,
0302             RK3368_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
0303     DIV(0, "atclk_core_l", "armclkl", 0,
0304             RK3368_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
0305     DIV(0, "pclk_dbg_l", "armclkl", 0,
0306             RK3368_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
0307
0308     GATE(0, "apllb_cs", "apllb", CLK_IGNORE_UNUSED,
0309             RK3368_CLKGATE_CON(0), 9, GFLAGS),
0310     GATE(0, "aplll_cs", "aplll", CLK_IGNORE_UNUSED,
0311             RK3368_CLKGATE_CON(0), 10, GFLAGS),
0312     GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
0313             RK3368_CLKGATE_CON(0), 8, GFLAGS),
0314     COMPOSITE_NOGATE(0, "sclk_cs_pre", mux_cs_src_p, CLK_IGNORE_UNUSED,
0315             RK3368_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
0316     COMPOSITE_NOMUX(0, "clkin_trace", "sclk_cs_pre", CLK_IGNORE_UNUSED,
0317             RK3368_CLKSEL_CON(4), 8, 5, DFLAGS,
0318             RK3368_CLKGATE_CON(0), 13, GFLAGS),
0319
0320     COMPOSITE(0, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
0321             RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 7, DFLAGS,
0322             RK3368_CLKGATE_CON(0), 12, GFLAGS),
0323     GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),
0324
0325     GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
0326             RK3368_CLKGATE_CON(1), 8, GFLAGS),
0327     GATE(0, "gpll_ddr", "gpll", 0,
0328             RK3368_CLKGATE_CON(1), 9, GFLAGS),
0329     COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
0330             RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
0331
0332     FACTOR_GATE(0, "sclk_ddr", "ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
0333             RK3368_CLKGATE_CON(6), 14, GFLAGS),
0334     GATE(0, "sclk_ddr4x", "ddrphy_src", CLK_IGNORE_UNUSED,
0335             RK3368_CLKGATE_CON(6), 15, GFLAGS),
0336
0337     GATE(0, "gpll_aclk_bus", "gpll", CLK_IGNORE_UNUSED,
0338             RK3368_CLKGATE_CON(1), 10, GFLAGS),
0339     GATE(0, "cpll_aclk_bus", "cpll", CLK_IGNORE_UNUSED,
0340             RK3368_CLKGATE_CON(1), 11, GFLAGS),
0341     COMPOSITE_NOGATE(0, "aclk_bus_src", mux_aclk_bus_src_p, CLK_IGNORE_UNUSED,
0342             RK3368_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 5, DFLAGS),
0343
0344     GATE(ACLK_BUS, "aclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
0345             RK3368_CLKGATE_CON(1), 0, GFLAGS),
0346     COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
0347             RK3368_CLKSEL_CON(8), 12, 3, DFLAGS,
0348             RK3368_CLKGATE_CON(1), 2, GFLAGS),
0349     COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
0350             RK3368_CLKSEL_CON(8), 8, 2, DFLAGS,
0351             RK3368_CLKGATE_CON(1), 1, GFLAGS),
0352     COMPOSITE_NOMUX(0, "sclk_crypto", "aclk_bus_src", 0,
0353             RK3368_CLKSEL_CON(10), 14, 2, DFLAGS,
0354             RK3368_CLKGATE_CON(7), 2, GFLAGS),
0355
0356     COMPOSITE(0, "fclk_mcu_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
0357             RK3368_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 5, DFLAGS,
0358             RK3368_CLKGATE_CON(1), 3, GFLAGS),
0359     /*
0360      * stclk_mcu is listed as child of fclk_mcu_src in diagram 5,
0361      * but stclk_mcu has an additional own divider in diagram 2
0362      */
0363     COMPOSITE_NOMUX(0, "stclk_mcu", "fclk_mcu_src", 0,
0364             RK3368_CLKSEL_CON(12), 8, 3, DFLAGS,
0365             RK3368_CLKGATE_CON(13), 13, GFLAGS),
0366
0367     COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
0368             RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
0369             RK3368_CLKGATE_CON(6), 1, GFLAGS),
0370     COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
0371               RK3368_CLKSEL_CON(28), 0,
0372               RK3368_CLKGATE_CON(6), 2, GFLAGS,
0373               &rk3368_i2s_8ch_fracmux),
0374     COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
0375             RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
0376             RK3368_CLKGATE_CON(6), 0, GFLAGS),
0377     GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT,
0378             RK3368_CLKGATE_CON(6), 3, GFLAGS),
0379     COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
0380             RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS,
0381             RK3368_CLKGATE_CON(6), 4, GFLAGS),
0382     COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
0383               RK3368_CLKSEL_CON(32), 0,
0384               RK3368_CLKGATE_CON(6), 5, GFLAGS,
0385               &rk3368_spdif_8ch_fracmux),
0386     GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
0387          RK3368_CLKGATE_CON(6), 6, GFLAGS),
0388     COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
0389             RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS,
0390             RK3368_CLKGATE_CON(5), 13, GFLAGS),
0391     COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
0392               RK3368_CLKSEL_CON(54), 0,
0393               RK3368_CLKGATE_CON(5), 14, GFLAGS,
0394               &rk3368_i2s_2ch_fracmux),
0395     GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_pre", CLK_SET_RATE_PARENT,
0396          RK3368_CLKGATE_CON(5), 15, GFLAGS),
0397
0398     COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
0399             RK3368_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
0400             RK3368_CLKGATE_CON(6), 12, GFLAGS),
0401     GATE(0, "sclk_hsadc_tsp", "ext_hsadc_tsp", 0,
0402             RK3368_CLKGATE_CON(13), 7, GFLAGS),
0403
0404     MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
0405             RK3368_CLKSEL_CON(35), 12, 1, MFLAGS),
0406     COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
0407             RK3368_CLKSEL_CON(37), 0, 7, DFLAGS,
0408             RK3368_CLKGATE_CON(2), 4, GFLAGS),
0409     MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
0410             RK3368_CLKSEL_CON(37), 8, 1, MFLAGS),
0411
0412     /*
0413      * Clock-Architecture Diagram 3
0414      */
0415
0416     COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
0417             RK3368_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
0418             RK3368_CLKGATE_CON(4), 6, GFLAGS),
0419     COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
0420             RK3368_CLKSEL_CON(15), 14, 2, MFLAGS, 8, 5, DFLAGS,
0421             RK3368_CLKGATE_CON(4), 7, GFLAGS),
0422
0423     /*
0424      * We use aclk_vdpu by default ---GRF_SOC_CON0[7] setting in system,
0425      * so we ignore the mux and make clocks nodes as following,
0426      */
0427     FACTOR_GATE(0, "hclk_video_pre", "aclk_vdpu", 0, 1, 4,
0428         RK3368_CLKGATE_CON(4), 8, GFLAGS),
0429
0430     COMPOSITE(0, "sclk_hevc_cabac_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
0431             RK3368_CLKSEL_CON(17), 6, 2, MFLAGS, 0, 5, DFLAGS,
0432             RK3368_CLKGATE_CON(5), 1, GFLAGS),
0433     COMPOSITE(0, "sclk_hevc_core_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
0434             RK3368_CLKSEL_CON(17), 14, 2, MFLAGS, 8, 5, DFLAGS,
0435             RK3368_CLKGATE_CON(5), 2, GFLAGS),
0436
0437     COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb_p, CLK_IGNORE_UNUSED,
0438             RK3368_CLKSEL_CON(19), 6, 2, MFLAGS, 0, 5, DFLAGS,
0439             RK3368_CLKGATE_CON(4), 0, GFLAGS),
0440     DIV(0, "hclk_vio", "aclk_vio0", 0,
0441             RK3368_CLKSEL_CON(21), 0, 5, DFLAGS),
0442
0443     COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb_p, 0,
0444             RK3368_CLKSEL_CON(18), 14, 2, MFLAGS, 8, 5, DFLAGS,
0445             RK3368_CLKGATE_CON(4), 3, GFLAGS),
0446     COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb_p, 0,
0447             RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS,
0448             RK3368_CLKGATE_CON(4), 4, GFLAGS),
0449
0450     COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_cpll_gpll_npll_p, 0,
0451             RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
0452             RK3368_CLKGATE_CON(4), 1, GFLAGS),
0453
0454     GATE(SCLK_VOP0_PWM, "sclk_vop0_pwm", "xin24m", 0,
0455             RK3368_CLKGATE_CON(4), 2, GFLAGS),
0456
0457     COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
0458             RK3368_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 6, DFLAGS,
0459             RK3368_CLKGATE_CON(4), 9, GFLAGS),
0460
0461     GATE(0, "pclk_isp_in", "ext_isp", 0,
0462             RK3368_CLKGATE_CON(17), 2, GFLAGS),
0463     INVERTER(PCLK_ISP, "pclk_isp", "pclk_isp_in",
0464             RK3368_CLKSEL_CON(21), 6, IFLAGS),
0465
0466     GATE(0, "pclk_vip_in", "ext_vip", 0,
0467             RK3368_CLKGATE_CON(16), 13, GFLAGS),
0468     INVERTER(PCLK_VIP, "pclk_vip", "pclk_vip_in",
0469             RK3368_CLKSEL_CON(21), 13, IFLAGS),
0470
0471     GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
0472             RK3368_CLKGATE_CON(4), 13, GFLAGS),
0473     GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
0474             RK3368_CLKGATE_CON(4), 12, GFLAGS),
0475
0476     COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
0477             RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
0478             RK3368_CLKGATE_CON(4), 5, GFLAGS),
0479     COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
0480             RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS),
0481
0482     COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
0483             RK3368_CLKSEL_CON(23), 8, 1, MFLAGS,
0484             RK3368_CLKGATE_CON(5), 4, GFLAGS),
0485     COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
0486             RK3368_CLKSEL_CON(23), 6, 2, MFLAGS, 0, 6, DFLAGS,
0487             RK3368_CLKGATE_CON(5), 3, GFLAGS),
0488
0489     COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
0490             RK3368_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 6, DFLAGS,
0491             RK3368_CLKGATE_CON(5), 5, GFLAGS),
0492
0493     DIV(0, "pclk_pd_alive", "gpll", 0,
0494             RK3368_CLKSEL_CON(10), 8, 5, DFLAGS),
0495
0496     /* sclk_timer has a gate in the sgrf */
0497
0498     COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
0499             RK3368_CLKSEL_CON(10), 0, 5, DFLAGS,
0500             RK3368_CLKGATE_CON(7), 9, GFLAGS),
0501     GATE(SCLK_PVTM_PMU, "sclk_pvtm_pmu", "xin24m", 0,
0502             RK3368_CLKGATE_CON(7), 3, GFLAGS),
0503     COMPOSITE(0, "sclk_gpu_core_src", mux_pll_src_cpll_gpll_usb_npll_p, 0,
0504             RK3368_CLKSEL_CON(14), 6, 2, MFLAGS, 0, 5, DFLAGS,
0505             RK3368_CLKGATE_CON(4), 11, GFLAGS),
0506     MUX(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
0507             RK3368_CLKSEL_CON(14), 14, 1, MFLAGS),
0508     COMPOSITE_NOMUX(0, "aclk_gpu_mem_pre", "aclk_gpu_src", 0,
0509             RK3368_CLKSEL_CON(14), 8, 5, DFLAGS,
0510             RK3368_CLKGATE_CON(5), 8, GFLAGS),
0511     COMPOSITE_NOMUX(0, "aclk_gpu_cfg_pre", "aclk_gpu_src", 0,
0512             RK3368_CLKSEL_CON(16), 8, 5, DFLAGS,
0513             RK3368_CLKGATE_CON(5), 9, GFLAGS),
0514     GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0,
0515             RK3368_CLKGATE_CON(7), 11, GFLAGS),
0516
0517     COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
0518             RK3368_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 5, DFLAGS,
0519             RK3368_CLKGATE_CON(3), 0, GFLAGS),
0520     COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
0521             RK3368_CLKSEL_CON(9), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
0522             RK3368_CLKGATE_CON(3), 3, GFLAGS),
0523     COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
0524             RK3368_CLKSEL_CON(9), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
0525             RK3368_CLKGATE_CON(3), 2, GFLAGS),
0526     GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
0527             RK3368_CLKGATE_CON(3), 1, GFLAGS),
0528
0529     GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS),
0530
0531     /*
0532      * Clock-Architecture Diagram 4
0533      */
0534
0535     COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
0536             RK3368_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS,
0537             RK3368_CLKGATE_CON(3), 7, GFLAGS),
0538     COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
0539             RK3368_CLKSEL_CON(45), 15, 1, MFLAGS, 8, 7, DFLAGS,
0540             RK3368_CLKGATE_CON(3), 8, GFLAGS),
0541     COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
0542             RK3368_CLKSEL_CON(46), 15, 1, MFLAGS, 8, 7, DFLAGS,
0543             RK3368_CLKGATE_CON(3), 9, GFLAGS),
0544
0545
0546     COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
0547             RK3368_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
0548             RK3368_CLKGATE_CON(7), 12, GFLAGS),
0549     COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
0550             RK3368_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
0551             RK3368_CLKGATE_CON(7), 13, GFLAGS),
0552     COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
0553             RK3368_CLKSEL_CON(51), 8, 2, MFLAGS, 0, 7, DFLAGS,
0554             RK3368_CLKGATE_CON(7), 15, GFLAGS),
0555
0556     MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3368_SDMMC_CON0, 1),
0557     MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3368_SDMMC_CON1, 0),
0558
0559     MMC(SCLK_SDIO0_DRV,    "sdio0_drv",    "sclk_sdio0", RK3368_SDIO0_CON0, 1),
0560     MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3368_SDIO0_CON1, 0),
0561
0562     MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3368_EMMC_CON0,  1),
0563     MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3368_EMMC_CON1,  0),
0564
0565     GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
0566             RK3368_CLKGATE_CON(8), 1, GFLAGS),
0567
0568     /* pmu_grf_soc_con0[6] allows to select between xin32k and pvtm_pmu */
0569     GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
0570             RK3368_CLKGATE_CON(8), 4, GFLAGS),
0571
0572     /* pmu_grf_soc_con0[6] allows to select between xin32k and pvtm_pmu */
0573     COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
0574             RK3368_CLKSEL_CON(25), 0, 6, DFLAGS,
0575             RK3368_CLKGATE_CON(3), 5, GFLAGS),
0576
0577     COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
0578             RK3368_CLKSEL_CON(25), 8, 8, DFLAGS,
0579             RK3368_CLKGATE_CON(3), 6, GFLAGS),
0580
0581     COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
0582             RK3368_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS,
0583             RK3368_CLKGATE_CON(7), 8, GFLAGS),
0584
0585     COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_cpll_gpll_p, 0,
0586             RK3368_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 5, DFLAGS,
0587             RK3368_CLKGATE_CON(6), 7, GFLAGS),
0588
0589     COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb_usb_p, 0,
0590             RK3368_CLKSEL_CON(33), 12, 2, MFLAGS, 0, 7, DFLAGS,
0591             RK3368_CLKGATE_CON(2), 0, GFLAGS),
0592     COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
0593               RK3368_CLKSEL_CON(34), 0,
0594               RK3368_CLKGATE_CON(2), 1, GFLAGS,
0595               &rk3368_uart0_fracmux),
0596
0597     COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
0598             RK3368_CLKSEL_CON(35), 0, 7, DFLAGS,
0599             RK3368_CLKGATE_CON(2), 2, GFLAGS),
0600     COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
0601               RK3368_CLKSEL_CON(36), 0,
0602               RK3368_CLKGATE_CON(2), 3, GFLAGS,
0603               &rk3368_uart1_fracmux),
0604
0605     COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
0606             RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
0607             RK3368_CLKGATE_CON(2), 6, GFLAGS),
0608     COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
0609               RK3368_CLKSEL_CON(40), 0,
0610               RK3368_CLKGATE_CON(2), 7, GFLAGS,
0611               &rk3368_uart3_fracmux),
0612
0613     COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
0614             RK3368_CLKSEL_CON(41), 0, 7, DFLAGS,
0615             RK3368_CLKGATE_CON(2), 8, GFLAGS),
0616     COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
0617               RK3368_CLKSEL_CON(42), 0,
0618               RK3368_CLKGATE_CON(2), 9, GFLAGS,
0619               &rk3368_uart4_fracmux),
0620
0621     COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
0622             RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
0623             RK3368_CLKGATE_CON(3), 4, GFLAGS),
0624     MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
0625             RK3368_CLKSEL_CON(43), 8, 1, MFLAGS),
0626     GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
0627             RK3368_CLKGATE_CON(7), 7, GFLAGS),
0628     GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
0629             RK3368_CLKGATE_CON(7), 6, GFLAGS),
0630     GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
0631             RK3368_CLKGATE_CON(7), 4, GFLAGS),
0632     GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
0633             RK3368_CLKGATE_CON(7), 5, GFLAGS),
0634
0635     GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
0636             RK3368_CLKGATE_CON(7), 0, GFLAGS),
0637
0638     COMPOSITE_NODIV(0, "hsic_usbphy_480m", mux_hsic_usbphy480m_p, 0,
0639             RK3368_CLKSEL_CON(26), 8, 2, MFLAGS,
0640             RK3368_CLKGATE_CON(8), 0, GFLAGS),
0641     COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
0642             RK3368_CLKSEL_CON(26), 12, 2, MFLAGS,
0643             RK3368_CLKGATE_CON(8), 7, GFLAGS),
0644     GATE(SCLK_HSICPHY12M, "sclk_hsicphy12m", "xin12m", 0,
0645             RK3368_CLKGATE_CON(8), 6, GFLAGS),
0646
0647     /*
0648      * Clock-Architecture Diagram 5
0649      */
0650
0651     /* aclk_cci_pre gates */
0652     GATE(0, "aclk_core_niu_cpup", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 4, GFLAGS),
0653     GATE(0, "aclk_core_niu_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 3, GFLAGS),
0654     GATE(0, "aclk_cci400", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 2, GFLAGS),
0655     GATE(0, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 1, GFLAGS),
0656     GATE(0, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 0, GFLAGS),
0657
0658     /* aclkm_core_* gates */
0659     GATE(0, "aclk_adb400s_pd_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(10), 0, GFLAGS),
0660     GATE(0, "aclk_adb400s_pd_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 0, GFLAGS),
0661
0662     /* armclk* gates */
0663     GATE(0, "sclk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(10), 1, GFLAGS),
0664     GATE(0, "sclk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 1, GFLAGS),
0665
0666     /* sclk_cs_pre gates */
0667     GATE(0, "sclk_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 7, GFLAGS),
0668     GATE(0, "pclk_core_niu_sdbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 6, GFLAGS),
0669     GATE(0, "hclk_core_niu_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(11), 5, GFLAGS),
0670
0671     /* aclk_bus gates */
0672     GATE(0, "aclk_strc_sys", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 12, GFLAGS),
0673     GATE(ACLK_DMAC_BUS, "aclk_dmac_bus", "aclk_bus", 0, RK3368_CLKGATE_CON(12), 11, GFLAGS),
0674     GATE(0, "sclk_intmem1", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 6, GFLAGS),
0675     GATE(0, "sclk_intmem0", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 5, GFLAGS),
0676     GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 4, GFLAGS),
0677     GATE(0, "aclk_gic400", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 9, GFLAGS),
0678
0679     /* sclk_ddr gates */
0680     GATE(0, "nclk_ddrupctl", "sclk_ddr", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 2, GFLAGS),
0681
0682     /* clk_hsadc_tsp is part of diagram2 */
0683
0684     /* fclk_mcu_src gates */
0685     GATE(0, "hclk_noc_mcu", "fclk_mcu_src", 0, RK3368_CLKGATE_CON(13), 14, GFLAGS),
0686     GATE(0, "fclk_mcu", "fclk_mcu_src", 0, RK3368_CLKGATE_CON(13), 12, GFLAGS),
0687     GATE(0, "hclk_mcu", "fclk_mcu_src", 0, RK3368_CLKGATE_CON(13), 11, GFLAGS),
0688
0689     /* hclk_cpu gates */
0690     GATE(HCLK_SPDIF, "hclk_spdif", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 10, GFLAGS),
0691     GATE(HCLK_ROM, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 9, GFLAGS),
0692     GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 8, GFLAGS),
0693     GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 7, GFLAGS),
0694     GATE(HCLK_TSP, "hclk_tsp", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 10, GFLAGS),
0695     GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 4, GFLAGS),
0696     GATE(MCLK_CRYPTO, "mclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 3, GFLAGS),
0697
0698     /* pclk_cpu gates */
0699     GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 14, GFLAGS),
0700     GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 13, GFLAGS),
0701     GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 3, GFLAGS),
0702     GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 2, GFLAGS),
0703     GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 1, GFLAGS),
0704     GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 0, GFLAGS),
0705     GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
0706     GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
0707     GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
0708     GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
0709     GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
0710
0711     /*
0712      * video clk gates
0713      * aclk_video(_pre) can actually select between parents of aclk_vdpu
0714      * and aclk_vepu by setting bit GRF_SOC_CON0[7].
0715      */
0716     GATE(ACLK_VIDEO, "aclk_video", "aclk_vdpu", 0, RK3368_CLKGATE_CON(15), 0, GFLAGS),
0717     GATE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", "sclk_hevc_cabac_src", 0, RK3368_CLKGATE_CON(15), 3, GFLAGS),
0718     GATE(SCLK_HEVC_CORE, "sclk_hevc_core", "sclk_hevc_core_src", 0, RK3368_CLKGATE_CON(15), 2, GFLAGS),
0719     GATE(HCLK_VIDEO, "hclk_video", "hclk_video_pre", 0, RK3368_CLKGATE_CON(15), 1, GFLAGS),
0720
0721     /* aclk_rga_pre gates */
0722     GATE(ACLK_VIO1_NOC, "aclk_vio1_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 10, GFLAGS),
0723     GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(16), 0, GFLAGS),
0724     GATE(ACLK_HDCP, "aclk_hdcp", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(17), 10, GFLAGS),
0725
0726     /* aclk_vio0 gates */
0727     GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 11, GFLAGS),
0728     GATE(ACLK_VIO0_NOC, "aclk_vio0_noc", "aclk_vio0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 9, GFLAGS),
0729     GATE(ACLK_VOP, "aclk_vop", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 5, GFLAGS),
0730     GATE(ACLK_VOP_IEP, "aclk_vop_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 4, GFLAGS),
0731     GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 2, GFLAGS),
0732
0733     /* sclk_isp gates */
0734     GATE(HCLK_ISP, "hclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(16), 14, GFLAGS),
0735     GATE(ACLK_ISP, "aclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(17), 0, GFLAGS),
0736
0737     /* hclk_vio gates */
0738     GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 12, GFLAGS),
0739     GATE(HCLK_VIO_NOC, "hclk_vio_noc", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 8, GFLAGS),
0740     GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 7, GFLAGS),
0741     GATE(HCLK_VOP, "hclk_vop", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 6, GFLAGS),
0742     GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 3, GFLAGS),
0743     GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 1, GFLAGS),
0744     GATE(HCLK_VIO_HDCPMMU, "hclk_hdcpmmu", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 12, GFLAGS),
0745     GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 7, GFLAGS),
0746
0747     /*
0748      * pclk_vio gates
0749      * pclk_vio comes from the exactly same source as hclk_vio
0750      */
0751     GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 11, GFLAGS),
0752     GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 9, GFLAGS),
0753     GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 8, GFLAGS),
0754     GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 6, GFLAGS),
0755     GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 4, GFLAGS),
0756     GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 3, GFLAGS),
0757
0758     /* ext_vip gates in diagram3 */
0759
0760     /* gpu gates */
0761     GATE(SCLK_GPU_CORE, "sclk_gpu_core", "sclk_gpu_core_src", 0, RK3368_CLKGATE_CON(18), 2, GFLAGS),
0762     GATE(ACLK_GPU_MEM, "aclk_gpu_mem", "aclk_gpu_mem_pre", 0, RK3368_CLKGATE_CON(18), 1, GFLAGS),
0763     GATE(ACLK_GPU_CFG, "aclk_gpu_cfg", "aclk_gpu_cfg_pre", 0, RK3368_CLKGATE_CON(18), 0, GFLAGS),
0764
0765     /* aclk_peri gates */
0766     GATE(ACLK_DMAC_PERI, "aclk_dmac_peri", "aclk_peri", 0, RK3368_CLKGATE_CON(19), 3, GFLAGS),
0767     GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 2, GFLAGS),
0768     GATE(HCLK_SFC, "hclk_sfc", "aclk_peri", 0, RK3368_CLKGATE_CON(20), 15, GFLAGS),
0769     GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3368_CLKGATE_CON(20), 13, GFLAGS),
0770     GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 8, GFLAGS),
0771     GATE(ACLK_PERI_MMU, "aclk_peri_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(21), 4, GFLAGS),
0772
0773     /* hclk_peri gates */
0774     GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 0, GFLAGS),
0775     GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 11, GFLAGS),
0776     GATE(0, "hclk_mmc_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 10, GFLAGS),
0777     GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 9, GFLAGS),
0778     GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 7, GFLAGS),
0779     GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 6, GFLAGS),
0780     GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 5, GFLAGS),
0781     GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 4, GFLAGS),
0782     GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 3, GFLAGS),
0783     GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 2, GFLAGS),
0784     GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 1, GFLAGS),
0785     GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 3, GFLAGS),
0786     GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 2, GFLAGS),
0787     GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 1, GFLAGS),
0788     GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 0, GFLAGS),
0789
0790     /* pclk_peri gates */
0791     GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 15, GFLAGS),
0792     GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 14, GFLAGS),
0793     GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 13, GFLAGS),
0794     GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 12, GFLAGS),
0795     GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 11, GFLAGS),
0796     GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 10, GFLAGS),
0797     GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 9, GFLAGS),
0798     GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 8, GFLAGS),
0799     GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 7, GFLAGS),
0800     GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 6, GFLAGS),
0801     GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 5, GFLAGS),
0802     GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 4, GFLAGS),
0803     GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 1, GFLAGS),
0804     GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 14, GFLAGS),
0805     GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3368_CLKGATE_CON(20), 0, GFLAGS),
0806
0807     /* pclk_pd_alive gates */
0808     GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 13, GFLAGS),
0809     GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 12, GFLAGS),
0810     GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 9, GFLAGS),
0811     GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 8, GFLAGS),
0812     GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 3, GFLAGS),
0813     GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS),
0814     GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
0815
0816     /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
0817     SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
0818
0819     /*
0820      * pclk_vio gates
0821      * pclk_vio comes from the exactly same source as hclk_vio
0822      */
0823     GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 11, GFLAGS),
0824     GATE(PCLK_DPHYTX0, "pclk_dphytx0", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 10, GFLAGS),
0825
0826     /* pclk_pd_pmu gates */
0827     GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),
0828     GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3368_CLKGATE_CON(23), 4, GFLAGS),
0829     GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 3, GFLAGS),
0830     GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 2, GFLAGS),
0831     GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 1, GFLAGS),
0832     GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS),
0833
0834     /* timer gates */
0835     GATE(SCLK_TIMER15, "sclk_timer15", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 11, GFLAGS),
0836     GATE(SCLK_TIMER14, "sclk_timer14", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 10, GFLAGS),
0837     GATE(SCLK_TIMER13, "sclk_timer13", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 9, GFLAGS),
0838     GATE(SCLK_TIMER12, "sclk_timer12", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 8, GFLAGS),
0839     GATE(SCLK_TIMER11, "sclk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 7, GFLAGS),
0840     GATE(SCLK_TIMER10, "sclk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 6, GFLAGS),
0841     GATE(SCLK_TIMER05, "sclk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 5, GFLAGS),
0842     GATE(SCLK_TIMER04, "sclk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 4, GFLAGS),
0843     GATE(SCLK_TIMER03, "sclk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 3, GFLAGS),
0844     GATE(SCLK_TIMER02, "sclk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 2, GFLAGS),
0845     GATE(SCLK_TIMER01, "sclk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 1, GFLAGS),
0846     GATE(SCLK_TIMER00, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS),
0847 };
0848
0849 static const char *const rk3368_critical_clocks[] __initconst = {
0850     "aclk_bus",
0851     "aclk_peri",
0852     /*
0853      * pwm1 supplies vdd_logic on a lot of boards, is currently unhandled
0854      * but needs to stay enabled there (including its parents) at all times.
0855      */
0856     "pclk_pwm1",
0857     "pclk_pd_pmu",
0858     "pclk_pd_alive",
0859     "pclk_peri",
0860     "hclk_peri",
0861     "pclk_ddrphy",
0862     "pclk_ddrupctl",
0863     "pmu_hclk_otg0",
0864 };
0865
0866 static void __init rk3368_clk_init(struct device_node *np)
0867 {
0868     struct rockchip_clk_provider *ctx;
0869     void __iomem *reg_base;
0870
0871     reg_base = of_iomap(np, 0);
0872     if (!reg_base) {
0873         pr_err("%s: could not map cru region\n", __func__);
0874         return;
0875     }
0876
0877     ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
0878     if (IS_ERR(ctx)) {
0879         pr_err("%s: rockchip clk init failed\n", __func__);
0880         iounmap(reg_base);
0881         return;
0882     }
0883
0884     rockchip_clk_register_plls(ctx, rk3368_pll_clks,
0885                    ARRAY_SIZE(rk3368_pll_clks),
0886                    RK3368_GRF_SOC_STATUS0);
0887     rockchip_clk_register_branches(ctx, rk3368_clk_branches,
0888                   ARRAY_SIZE(rk3368_clk_branches));
0889     rockchip_clk_protect_critical(rk3368_critical_clocks,
0890                       ARRAY_SIZE(rk3368_critical_clocks));
0891
0892     rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
0893             mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
0894             &rk3368_cpuclkb_data, rk3368_cpuclkb_rates,
0895             ARRAY_SIZE(rk3368_cpuclkb_rates));
0896
0897     rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
0898             mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
0899             &rk3368_cpuclkl_data, rk3368_cpuclkl_rates,
0900             ARRAY_SIZE(rk3368_cpuclkl_rates));
0901
0902     rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0),
0903                   ROCKCHIP_SOFTRST_HIWORD_MASK);
0904
0905     rockchip_register_restart_notifier(ctx, RK3368_GLB_SRST_FST, NULL);
0906
0907     rockchip_clk_of_add_provider(np, ctx);
0908 }
0909 CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3368-cru", rk3368_clk_init);