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0007 #include <linux/clk-provider.h>
0008 #include <linux/io.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/syscore_ops.h>
0012 #include <dt-bindings/clock/rk3328-cru.h>
0013 #include "clk.h"
0014
0015 #define RK3328_GRF_SOC_CON4 0x410
0016 #define RK3328_GRF_SOC_STATUS0 0x480
0017 #define RK3328_GRF_MAC_CON1 0x904
0018 #define RK3328_GRF_MAC_CON2 0x908
0019
0020 enum rk3328_plls {
0021 apll, dpll, cpll, gpll, npll,
0022 };
0023
0024 static struct rockchip_pll_rate_table rk3328_pll_rates[] = {
0025
0026 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
0027 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
0028 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
0029 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
0030 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
0031 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
0032 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
0033 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
0034 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
0035 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
0036 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
0037 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
0038 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
0039 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
0040 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
0041 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
0042 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
0043 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
0044 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
0045 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
0046 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
0047 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
0048 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
0049 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
0050 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
0051 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
0052 RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
0053 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
0054 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
0055 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
0056 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
0057 RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
0058 RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
0059 RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
0060 RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
0061 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
0062 RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
0063 RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
0064 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
0065 RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
0066 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
0067 RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
0068 { },
0069 };
0070
0071 static struct rockchip_pll_rate_table rk3328_pll_frac_rates[] = {
0072
0073 RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134218),
0074
0075 RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671089),
0076
0077 RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671089),
0078
0079 RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671089),
0080
0081 RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797895),
0082
0083 RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066330),
0084
0085 { },
0086 };
0087
0088 #define RK3328_DIV_ACLKM_MASK 0x7
0089 #define RK3328_DIV_ACLKM_SHIFT 4
0090 #define RK3328_DIV_PCLK_DBG_MASK 0xf
0091 #define RK3328_DIV_PCLK_DBG_SHIFT 0
0092
0093 #define RK3328_CLKSEL1(_aclk_core, _pclk_dbg) \
0094 { \
0095 .reg = RK3328_CLKSEL_CON(1), \
0096 .val = HIWORD_UPDATE(_aclk_core, RK3328_DIV_ACLKM_MASK, \
0097 RK3328_DIV_ACLKM_SHIFT) | \
0098 HIWORD_UPDATE(_pclk_dbg, RK3328_DIV_PCLK_DBG_MASK, \
0099 RK3328_DIV_PCLK_DBG_SHIFT), \
0100 }
0101
0102 #define RK3328_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
0103 { \
0104 .prate = _prate, \
0105 .divs = { \
0106 RK3328_CLKSEL1(_aclk_core, _pclk_dbg), \
0107 }, \
0108 }
0109
0110 static struct rockchip_cpuclk_rate_table rk3328_cpuclk_rates[] __initdata = {
0111 RK3328_CPUCLK_RATE(1800000000, 1, 7),
0112 RK3328_CPUCLK_RATE(1704000000, 1, 7),
0113 RK3328_CPUCLK_RATE(1608000000, 1, 7),
0114 RK3328_CPUCLK_RATE(1512000000, 1, 7),
0115 RK3328_CPUCLK_RATE(1488000000, 1, 5),
0116 RK3328_CPUCLK_RATE(1416000000, 1, 5),
0117 RK3328_CPUCLK_RATE(1392000000, 1, 5),
0118 RK3328_CPUCLK_RATE(1296000000, 1, 5),
0119 RK3328_CPUCLK_RATE(1200000000, 1, 5),
0120 RK3328_CPUCLK_RATE(1104000000, 1, 5),
0121 RK3328_CPUCLK_RATE(1008000000, 1, 5),
0122 RK3328_CPUCLK_RATE(912000000, 1, 5),
0123 RK3328_CPUCLK_RATE(816000000, 1, 3),
0124 RK3328_CPUCLK_RATE(696000000, 1, 3),
0125 RK3328_CPUCLK_RATE(600000000, 1, 3),
0126 RK3328_CPUCLK_RATE(408000000, 1, 1),
0127 RK3328_CPUCLK_RATE(312000000, 1, 1),
0128 RK3328_CPUCLK_RATE(216000000, 1, 1),
0129 RK3328_CPUCLK_RATE(96000000, 1, 1),
0130 };
0131
0132 static const struct rockchip_cpuclk_reg_data rk3328_cpuclk_data = {
0133 .core_reg[0] = RK3328_CLKSEL_CON(0),
0134 .div_core_shift[0] = 0,
0135 .div_core_mask[0] = 0x1f,
0136 .num_cores = 1,
0137 .mux_core_alt = 1,
0138 .mux_core_main = 3,
0139 .mux_core_shift = 6,
0140 .mux_core_mask = 0x3,
0141 };
0142
0143 PNAME(mux_pll_p) = { "xin24m" };
0144
0145 PNAME(mux_2plls_p) = { "cpll", "gpll" };
0146 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
0147 PNAME(mux_cpll_gpll_apll_p) = { "cpll", "gpll", "apll" };
0148 PNAME(mux_2plls_xin24m_p) = { "cpll", "gpll", "xin24m" };
0149 PNAME(mux_2plls_hdmiphy_p) = { "cpll", "gpll",
0150 "dummy_hdmiphy" };
0151 PNAME(mux_4plls_p) = { "cpll", "gpll",
0152 "dummy_hdmiphy",
0153 "usb480m" };
0154 PNAME(mux_2plls_u480m_p) = { "cpll", "gpll",
0155 "usb480m" };
0156 PNAME(mux_2plls_24m_u480m_p) = { "cpll", "gpll",
0157 "xin24m", "usb480m" };
0158
0159 PNAME(mux_ddrphy_p) = { "dpll", "apll", "cpll" };
0160 PNAME(mux_armclk_p) = { "apll_core",
0161 "gpll_core",
0162 "dpll_core",
0163 "npll_core"};
0164 PNAME(mux_hdmiphy_p) = { "hdmi_phy", "xin24m" };
0165 PNAME(mux_usb480m_p) = { "usb480m_phy",
0166 "xin24m" };
0167
0168 PNAME(mux_i2s0_p) = { "clk_i2s0_div",
0169 "clk_i2s0_frac",
0170 "xin12m",
0171 "xin12m" };
0172 PNAME(mux_i2s1_p) = { "clk_i2s1_div",
0173 "clk_i2s1_frac",
0174 "clkin_i2s1",
0175 "xin12m" };
0176 PNAME(mux_i2s2_p) = { "clk_i2s2_div",
0177 "clk_i2s2_frac",
0178 "clkin_i2s2",
0179 "xin12m" };
0180 PNAME(mux_i2s1out_p) = { "clk_i2s1", "xin12m"};
0181 PNAME(mux_i2s2out_p) = { "clk_i2s2", "xin12m" };
0182 PNAME(mux_spdif_p) = { "clk_spdif_div",
0183 "clk_spdif_frac",
0184 "xin12m",
0185 "xin12m" };
0186 PNAME(mux_uart0_p) = { "clk_uart0_div",
0187 "clk_uart0_frac",
0188 "xin24m" };
0189 PNAME(mux_uart1_p) = { "clk_uart1_div",
0190 "clk_uart1_frac",
0191 "xin24m" };
0192 PNAME(mux_uart2_p) = { "clk_uart2_div",
0193 "clk_uart2_frac",
0194 "xin24m" };
0195
0196 PNAME(mux_sclk_cif_p) = { "clk_cif_src",
0197 "xin24m" };
0198 PNAME(mux_dclk_lcdc_p) = { "hdmiphy",
0199 "dclk_lcdc_src" };
0200 PNAME(mux_aclk_peri_pre_p) = { "cpll_peri",
0201 "gpll_peri",
0202 "hdmiphy_peri" };
0203 PNAME(mux_ref_usb3otg_src_p) = { "xin24m",
0204 "clk_usb3otg_ref" };
0205 PNAME(mux_xin24m_32k_p) = { "xin24m",
0206 "clk_rtc32k" };
0207 PNAME(mux_mac2io_src_p) = { "clk_mac2io_src",
0208 "gmac_clkin" };
0209 PNAME(mux_mac2phy_src_p) = { "clk_mac2phy_src",
0210 "phy_50m_out" };
0211 PNAME(mux_mac2io_ext_p) = { "clk_mac2io",
0212 "gmac_clkin" };
0213
0214 static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = {
0215 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
0216 0, RK3328_PLL_CON(0),
0217 RK3328_MODE_CON, 0, 4, 0, rk3328_pll_frac_rates),
0218 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
0219 0, RK3328_PLL_CON(8),
0220 RK3328_MODE_CON, 4, 3, 0, NULL),
0221 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
0222 0, RK3328_PLL_CON(16),
0223 RK3328_MODE_CON, 8, 2, 0, rk3328_pll_rates),
0224 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
0225 0, RK3328_PLL_CON(24),
0226 RK3328_MODE_CON, 12, 1, 0, rk3328_pll_frac_rates),
0227 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
0228 0, RK3328_PLL_CON(40),
0229 RK3328_MODE_CON, 1, 0, 0, rk3328_pll_rates),
0230 };
0231
0232 #define MFLAGS CLK_MUX_HIWORD_MASK
0233 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
0234 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
0235
0236 static struct rockchip_clk_branch rk3328_i2s0_fracmux __initdata =
0237 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
0238 RK3328_CLKSEL_CON(6), 8, 2, MFLAGS);
0239
0240 static struct rockchip_clk_branch rk3328_i2s1_fracmux __initdata =
0241 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT,
0242 RK3328_CLKSEL_CON(8), 8, 2, MFLAGS);
0243
0244 static struct rockchip_clk_branch rk3328_i2s2_fracmux __initdata =
0245 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
0246 RK3328_CLKSEL_CON(10), 8, 2, MFLAGS);
0247
0248 static struct rockchip_clk_branch rk3328_spdif_fracmux __initdata =
0249 MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, CLK_SET_RATE_PARENT,
0250 RK3328_CLKSEL_CON(12), 8, 2, MFLAGS);
0251
0252 static struct rockchip_clk_branch rk3328_uart0_fracmux __initdata =
0253 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
0254 RK3328_CLKSEL_CON(14), 8, 2, MFLAGS);
0255
0256 static struct rockchip_clk_branch rk3328_uart1_fracmux __initdata =
0257 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
0258 RK3328_CLKSEL_CON(16), 8, 2, MFLAGS);
0259
0260 static struct rockchip_clk_branch rk3328_uart2_fracmux __initdata =
0261 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
0262 RK3328_CLKSEL_CON(18), 8, 2, MFLAGS);
0263
0264 static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
0265
0266
0267
0268
0269 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
0270 RK3328_CLKSEL_CON(2), 8, 5, DFLAGS),
0271 COMPOSITE(SCLK_RTC32K, "clk_rtc32k", mux_2plls_xin24m_p, 0,
0272 RK3328_CLKSEL_CON(38), 14, 2, MFLAGS, 0, 14, DFLAGS,
0273 RK3328_CLKGATE_CON(0), 11, GFLAGS),
0274
0275
0276 MUX(HDMIPHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
0277 RK3328_MISC_CON, 13, 1, MFLAGS),
0278 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
0279 RK3328_MISC_CON, 15, 1, MFLAGS),
0280
0281
0282
0283
0284
0285
0286 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
0287 RK3328_CLKGATE_CON(0), 0, GFLAGS),
0288 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
0289 RK3328_CLKGATE_CON(0), 2, GFLAGS),
0290 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
0291 RK3328_CLKGATE_CON(0), 1, GFLAGS),
0292 GATE(0, "npll_core", "npll", CLK_IGNORE_UNUSED,
0293 RK3328_CLKGATE_CON(0), 12, GFLAGS),
0294 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
0295 RK3328_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
0296 RK3328_CLKGATE_CON(7), 0, GFLAGS),
0297 COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
0298 RK3328_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
0299 RK3328_CLKGATE_CON(7), 1, GFLAGS),
0300 GATE(0, "aclk_core_niu", "aclk_core", 0,
0301 RK3328_CLKGATE_CON(13), 0, GFLAGS),
0302 GATE(0, "aclk_gic400", "aclk_core", CLK_IGNORE_UNUSED,
0303 RK3328_CLKGATE_CON(13), 1, GFLAGS),
0304
0305 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
0306 RK3328_CLKGATE_CON(7), 2, GFLAGS),
0307
0308
0309 COMPOSITE(0, "aclk_gpu_pre", mux_4plls_p, 0,
0310 RK3328_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
0311 RK3328_CLKGATE_CON(6), 6, GFLAGS),
0312 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_SET_RATE_PARENT,
0313 RK3328_CLKGATE_CON(14), 0, GFLAGS),
0314 GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0,
0315 RK3328_CLKGATE_CON(14), 1, GFLAGS),
0316
0317
0318 COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
0319 RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
0320 RK3328_CLKGATE_CON(0), 4, GFLAGS),
0321 GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
0322 RK3328_CLKGATE_CON(18), 6, GFLAGS),
0323 GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
0324 RK3328_CLKGATE_CON(18), 5, GFLAGS),
0325 GATE(0, "aclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
0326 RK3328_CLKGATE_CON(18), 4, GFLAGS),
0327 GATE(0, "clk_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
0328 RK3328_CLKGATE_CON(0), 6, GFLAGS),
0329
0330 COMPOSITE(PCLK_DDR, "pclk_ddr", mux_2plls_hdmiphy_p, 0,
0331 RK3328_CLKSEL_CON(4), 13, 2, MFLAGS, 8, 3, DFLAGS,
0332 RK3328_CLKGATE_CON(7), 4, GFLAGS),
0333 GATE(0, "pclk_ddrupctl", "pclk_ddr", CLK_IGNORE_UNUSED,
0334 RK3328_CLKGATE_CON(18), 1, GFLAGS),
0335 GATE(0, "pclk_ddr_msch", "pclk_ddr", CLK_IGNORE_UNUSED,
0336 RK3328_CLKGATE_CON(18), 2, GFLAGS),
0337 GATE(0, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
0338 RK3328_CLKGATE_CON(18), 3, GFLAGS),
0339 GATE(0, "pclk_ddrstdby", "pclk_ddr", CLK_IGNORE_UNUSED,
0340 RK3328_CLKGATE_CON(18), 7, GFLAGS),
0341 GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
0342 RK3328_CLKGATE_CON(18), 9, GFLAGS),
0343
0344
0345
0346
0347
0348
0349 COMPOSITE(ACLK_BUS_PRE, "aclk_bus_pre", mux_2plls_hdmiphy_p, 0,
0350 RK3328_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
0351 RK3328_CLKGATE_CON(8), 0, GFLAGS),
0352 COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_pre", 0,
0353 RK3328_CLKSEL_CON(1), 8, 2, DFLAGS,
0354 RK3328_CLKGATE_CON(8), 1, GFLAGS),
0355 COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", 0,
0356 RK3328_CLKSEL_CON(1), 12, 3, DFLAGS,
0357 RK3328_CLKGATE_CON(8), 2, GFLAGS),
0358 GATE(0, "pclk_bus", "pclk_bus_pre", 0,
0359 RK3328_CLKGATE_CON(8), 3, GFLAGS),
0360 GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0,
0361 RK3328_CLKGATE_CON(8), 4, GFLAGS),
0362
0363 COMPOSITE(SCLK_TSP, "clk_tsp", mux_2plls_p, 0,
0364 RK3328_CLKSEL_CON(21), 15, 1, MFLAGS, 8, 5, DFLAGS,
0365 RK3328_CLKGATE_CON(2), 5, GFLAGS),
0366 GATE(0, "clk_hsadc_tsp", "ext_gpio3a2", 0,
0367 RK3328_CLKGATE_CON(17), 13, GFLAGS),
0368
0369
0370 COMPOSITE(0, "clk_i2s0_div", mux_2plls_p, 0,
0371 RK3328_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
0372 RK3328_CLKGATE_CON(1), 1, GFLAGS),
0373 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
0374 RK3328_CLKSEL_CON(7), 0,
0375 RK3328_CLKGATE_CON(1), 2, GFLAGS,
0376 &rk3328_i2s0_fracmux),
0377 GATE(SCLK_I2S0, "clk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
0378 RK3328_CLKGATE_CON(1), 3, GFLAGS),
0379
0380 COMPOSITE(0, "clk_i2s1_div", mux_2plls_p, 0,
0381 RK3328_CLKSEL_CON(8), 15, 1, MFLAGS, 0, 7, DFLAGS,
0382 RK3328_CLKGATE_CON(1), 4, GFLAGS),
0383 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
0384 RK3328_CLKSEL_CON(9), 0,
0385 RK3328_CLKGATE_CON(1), 5, GFLAGS,
0386 &rk3328_i2s1_fracmux),
0387 GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
0388 RK3328_CLKGATE_CON(1), 6, GFLAGS),
0389 COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0,
0390 RK3328_CLKSEL_CON(8), 12, 1, MFLAGS,
0391 RK3328_CLKGATE_CON(1), 7, GFLAGS),
0392
0393 COMPOSITE(0, "clk_i2s2_div", mux_2plls_p, 0,
0394 RK3328_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 7, DFLAGS,
0395 RK3328_CLKGATE_CON(1), 8, GFLAGS),
0396 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
0397 RK3328_CLKSEL_CON(11), 0,
0398 RK3328_CLKGATE_CON(1), 9, GFLAGS,
0399 &rk3328_i2s2_fracmux),
0400 GATE(SCLK_I2S2, "clk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
0401 RK3328_CLKGATE_CON(1), 10, GFLAGS),
0402 COMPOSITE_NODIV(SCLK_I2S2_OUT, "i2s2_out", mux_i2s2out_p, 0,
0403 RK3328_CLKSEL_CON(10), 12, 1, MFLAGS,
0404 RK3328_CLKGATE_CON(1), 11, GFLAGS),
0405
0406 COMPOSITE(0, "clk_spdif_div", mux_2plls_p, 0,
0407 RK3328_CLKSEL_CON(12), 15, 1, MFLAGS, 0, 7, DFLAGS,
0408 RK3328_CLKGATE_CON(1), 12, GFLAGS),
0409 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
0410 RK3328_CLKSEL_CON(13), 0,
0411 RK3328_CLKGATE_CON(1), 13, GFLAGS,
0412 &rk3328_spdif_fracmux),
0413
0414
0415 COMPOSITE(0, "clk_uart0_div", mux_2plls_u480m_p, 0,
0416 RK3328_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
0417 RK3328_CLKGATE_CON(1), 14, GFLAGS),
0418 COMPOSITE(0, "clk_uart1_div", mux_2plls_u480m_p, 0,
0419 RK3328_CLKSEL_CON(16), 12, 2, MFLAGS, 0, 7, DFLAGS,
0420 RK3328_CLKGATE_CON(2), 0, GFLAGS),
0421 COMPOSITE(0, "clk_uart2_div", mux_2plls_u480m_p, 0,
0422 RK3328_CLKSEL_CON(18), 12, 2, MFLAGS, 0, 7, DFLAGS,
0423 RK3328_CLKGATE_CON(2), 2, GFLAGS),
0424 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
0425 RK3328_CLKSEL_CON(15), 0,
0426 RK3328_CLKGATE_CON(1), 15, GFLAGS,
0427 &rk3328_uart0_fracmux),
0428 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
0429 RK3328_CLKSEL_CON(17), 0,
0430 RK3328_CLKGATE_CON(2), 1, GFLAGS,
0431 &rk3328_uart1_fracmux),
0432 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
0433 RK3328_CLKSEL_CON(19), 0,
0434 RK3328_CLKGATE_CON(2), 3, GFLAGS,
0435 &rk3328_uart2_fracmux),
0436
0437
0438
0439
0440
0441 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_2plls_p, 0,
0442 RK3328_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 7, DFLAGS,
0443 RK3328_CLKGATE_CON(2), 9, GFLAGS),
0444 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_2plls_p, 0,
0445 RK3328_CLKSEL_CON(34), 15, 1, MFLAGS, 8, 7, DFLAGS,
0446 RK3328_CLKGATE_CON(2), 10, GFLAGS),
0447 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_2plls_p, 0,
0448 RK3328_CLKSEL_CON(35), 7, 1, MFLAGS, 0, 7, DFLAGS,
0449 RK3328_CLKGATE_CON(2), 11, GFLAGS),
0450 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_2plls_p, 0,
0451 RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS,
0452 RK3328_CLKGATE_CON(2), 12, GFLAGS),
0453 COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0,
0454 RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
0455 RK3328_CLKGATE_CON(2), 4, GFLAGS),
0456 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
0457 RK3328_CLKSEL_CON(22), 0, 10, DFLAGS,
0458 RK3328_CLKGATE_CON(2), 6, GFLAGS),
0459 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "clk_24m", 0,
0460 RK3328_CLKSEL_CON(23), 0, 10, DFLAGS,
0461 RK3328_CLKGATE_CON(2), 14, GFLAGS),
0462 COMPOSITE(SCLK_SPI, "clk_spi", mux_2plls_p, 0,
0463 RK3328_CLKSEL_CON(24), 7, 1, MFLAGS, 0, 7, DFLAGS,
0464 RK3328_CLKGATE_CON(2), 7, GFLAGS),
0465 COMPOSITE(SCLK_PWM, "clk_pwm", mux_2plls_p, 0,
0466 RK3328_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 7, DFLAGS,
0467 RK3328_CLKGATE_CON(2), 8, GFLAGS),
0468 COMPOSITE(SCLK_OTP, "clk_otp", mux_2plls_xin24m_p, 0,
0469 RK3328_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 6, DFLAGS,
0470 RK3328_CLKGATE_CON(3), 8, GFLAGS),
0471 COMPOSITE(SCLK_EFUSE, "clk_efuse", mux_2plls_xin24m_p, 0,
0472 RK3328_CLKSEL_CON(5), 14, 2, MFLAGS, 8, 5, DFLAGS,
0473 RK3328_CLKGATE_CON(2), 13, GFLAGS),
0474 COMPOSITE(SCLK_PDM, "clk_pdm", mux_cpll_gpll_apll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
0475 RK3328_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
0476 RK3328_CLKGATE_CON(2), 15, GFLAGS),
0477
0478 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
0479 RK3328_CLKGATE_CON(8), 5, GFLAGS),
0480 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
0481 RK3328_CLKGATE_CON(8), 6, GFLAGS),
0482 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
0483 RK3328_CLKGATE_CON(8), 7, GFLAGS),
0484 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
0485 RK3328_CLKGATE_CON(8), 8, GFLAGS),
0486 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
0487 RK3328_CLKGATE_CON(8), 9, GFLAGS),
0488 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
0489 RK3328_CLKGATE_CON(8), 10, GFLAGS),
0490
0491 COMPOSITE(SCLK_WIFI, "clk_wifi", mux_2plls_u480m_p, 0,
0492 RK3328_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 6, DFLAGS,
0493 RK3328_CLKGATE_CON(0), 10, GFLAGS),
0494
0495
0496
0497
0498
0499
0500 COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_4plls_p, 0,
0501 RK3328_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
0502 RK3328_CLKGATE_CON(6), 0, GFLAGS),
0503 FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
0504 RK3328_CLKGATE_CON(11), 0, GFLAGS),
0505 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", CLK_SET_RATE_PARENT,
0506 RK3328_CLKGATE_CON(24), 0, GFLAGS),
0507 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", CLK_SET_RATE_PARENT,
0508 RK3328_CLKGATE_CON(24), 1, GFLAGS),
0509 GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", 0,
0510 RK3328_CLKGATE_CON(24), 2, GFLAGS),
0511 GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", 0,
0512 RK3328_CLKGATE_CON(24), 3, GFLAGS),
0513
0514 COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_4plls_p, 0,
0515 RK3328_CLKSEL_CON(48), 14, 2, MFLAGS, 8, 5, DFLAGS,
0516 RK3328_CLKGATE_CON(6), 1, GFLAGS),
0517
0518 COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_4plls_p, 0,
0519 RK3328_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
0520 RK3328_CLKGATE_CON(6), 2, GFLAGS),
0521
0522 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_4plls_p, 0,
0523 RK3328_CLKSEL_CON(50), 6, 2, MFLAGS, 0, 5, DFLAGS,
0524 RK3328_CLKGATE_CON(6), 5, GFLAGS),
0525 FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
0526 RK3328_CLKGATE_CON(11), 8, GFLAGS),
0527 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", CLK_SET_RATE_PARENT,
0528 RK3328_CLKGATE_CON(23), 0, GFLAGS),
0529 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", CLK_SET_RATE_PARENT,
0530 RK3328_CLKGATE_CON(23), 1, GFLAGS),
0531 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 0,
0532 RK3328_CLKGATE_CON(23), 2, GFLAGS),
0533 GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 0,
0534 RK3328_CLKGATE_CON(23), 3, GFLAGS),
0535
0536 COMPOSITE(ACLK_RKVENC, "aclk_rkvenc", mux_4plls_p, 0,
0537 RK3328_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
0538 RK3328_CLKGATE_CON(6), 3, GFLAGS),
0539 FACTOR_GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 0, 1, 4,
0540 RK3328_CLKGATE_CON(11), 4, GFLAGS),
0541 GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 0,
0542 RK3328_CLKGATE_CON(25), 0, GFLAGS),
0543 GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0,
0544 RK3328_CLKGATE_CON(25), 1, GFLAGS),
0545 GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,
0546 RK3328_CLKGATE_CON(25), 2, GFLAGS),
0547 GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0,
0548 RK3328_CLKGATE_CON(25), 3, GFLAGS),
0549 GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0,
0550 RK3328_CLKGATE_CON(25), 4, GFLAGS),
0551 GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0,
0552 RK3328_CLKGATE_CON(25), 5, GFLAGS),
0553 GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED,
0554 RK3328_CLKGATE_CON(25), 6, GFLAGS),
0555
0556 COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
0557 RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
0558 RK3328_CLKGATE_CON(6), 4, GFLAGS),
0559
0560 COMPOSITE(SCLK_VENC_DSP, "sclk_venc_dsp", mux_4plls_p, 0,
0561 RK3328_CLKSEL_CON(52), 14, 2, MFLAGS, 8, 5, DFLAGS,
0562 RK3328_CLKGATE_CON(6), 7, GFLAGS),
0563
0564
0565
0566
0567
0568
0569 COMPOSITE(ACLK_VIO_PRE, "aclk_vio_pre", mux_4plls_p, 0,
0570 RK3328_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS,
0571 RK3328_CLKGATE_CON(5), 2, GFLAGS),
0572 DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_vio_pre", 0,
0573 RK3328_CLKSEL_CON(37), 8, 5, DFLAGS),
0574
0575 COMPOSITE(ACLK_RGA_PRE, "aclk_rga_pre", mux_4plls_p, 0,
0576 RK3328_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS,
0577 RK3328_CLKGATE_CON(5), 0, GFLAGS),
0578 COMPOSITE(SCLK_RGA, "clk_rga", mux_4plls_p, 0,
0579 RK3328_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS,
0580 RK3328_CLKGATE_CON(5), 1, GFLAGS),
0581 COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_4plls_p, 0,
0582 RK3328_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
0583 RK3328_CLKGATE_CON(5), 5, GFLAGS),
0584 GATE(SCLK_HDMI_SFC, "sclk_hdmi_sfc", "xin24m", 0,
0585 RK3328_CLKGATE_CON(5), 4, GFLAGS),
0586
0587 COMPOSITE_NODIV(0, "clk_cif_src", mux_2plls_p, 0,
0588 RK3328_CLKSEL_CON(42), 7, 1, MFLAGS,
0589 RK3328_CLKGATE_CON(5), 3, GFLAGS),
0590 COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cif_out", mux_sclk_cif_p, CLK_SET_RATE_PARENT,
0591 RK3328_CLKSEL_CON(42), 5, 1, MFLAGS, 0, 5, DFLAGS),
0592
0593 COMPOSITE(DCLK_LCDC_SRC, "dclk_lcdc_src", mux_gpll_cpll_p, 0,
0594 RK3328_CLKSEL_CON(40), 0, 1, MFLAGS, 8, 8, DFLAGS,
0595 RK3328_CLKGATE_CON(5), 6, GFLAGS),
0596 DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0,
0597 RK3328_CLKSEL_CON(40), 3, 3, DFLAGS),
0598 MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0599 RK3328_CLKSEL_CON(40), 1, 1, MFLAGS),
0600
0601
0602
0603
0604
0605
0606 GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
0607 RK3328_CLKGATE_CON(4), 0, GFLAGS),
0608 GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
0609 RK3328_CLKGATE_CON(4), 1, GFLAGS),
0610 GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
0611 RK3328_CLKGATE_CON(4), 2, GFLAGS),
0612 COMPOSITE_NOGATE(ACLK_PERI_PRE, "aclk_peri_pre", mux_aclk_peri_pre_p, 0,
0613 RK3328_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS),
0614 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED,
0615 RK3328_CLKSEL_CON(29), 0, 2, DFLAGS,
0616 RK3328_CLKGATE_CON(10), 2, GFLAGS),
0617 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED,
0618 RK3328_CLKSEL_CON(29), 4, 3, DFLAGS,
0619 RK3328_CLKGATE_CON(10), 1, GFLAGS),
0620 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
0621 RK3328_CLKGATE_CON(10), 0, GFLAGS),
0622
0623 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_2plls_24m_u480m_p, 0,
0624 RK3328_CLKSEL_CON(30), 8, 2, MFLAGS, 0, 8, DFLAGS,
0625 RK3328_CLKGATE_CON(4), 3, GFLAGS),
0626
0627 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_2plls_24m_u480m_p, 0,
0628 RK3328_CLKSEL_CON(31), 8, 2, MFLAGS, 0, 8, DFLAGS,
0629 RK3328_CLKGATE_CON(4), 4, GFLAGS),
0630
0631 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_2plls_24m_u480m_p, 0,
0632 RK3328_CLKSEL_CON(32), 8, 2, MFLAGS, 0, 8, DFLAGS,
0633 RK3328_CLKGATE_CON(4), 5, GFLAGS),
0634
0635 COMPOSITE(SCLK_SDMMC_EXT, "clk_sdmmc_ext", mux_2plls_24m_u480m_p, 0,
0636 RK3328_CLKSEL_CON(43), 8, 2, MFLAGS, 0, 8, DFLAGS,
0637 RK3328_CLKGATE_CON(4), 10, GFLAGS),
0638
0639 COMPOSITE(SCLK_REF_USB3OTG_SRC, "clk_ref_usb3otg_src", mux_2plls_p, 0,
0640 RK3328_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS,
0641 RK3328_CLKGATE_CON(4), 9, GFLAGS),
0642
0643 MUX(SCLK_REF_USB3OTG, "clk_ref_usb3otg", mux_ref_usb3otg_src_p, CLK_SET_RATE_PARENT,
0644 RK3328_CLKSEL_CON(45), 8, 1, MFLAGS),
0645
0646 GATE(SCLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0,
0647 RK3328_CLKGATE_CON(4), 7, GFLAGS),
0648
0649 COMPOSITE(SCLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", mux_xin24m_32k_p, 0,
0650 RK3328_CLKSEL_CON(33), 15, 1, MFLAGS, 0, 10, DFLAGS,
0651 RK3328_CLKGATE_CON(4), 8, GFLAGS),
0652
0653
0654
0655
0656
0657
0658 COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,
0659 RK3328_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
0660 RK3328_CLKGATE_CON(3), 2, GFLAGS),
0661 COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0,
0662 RK3328_CLKSEL_CON(25), 8, 3, DFLAGS,
0663 RK3328_CLKGATE_CON(9), 0, GFLAGS),
0664
0665 COMPOSITE(SCLK_MAC2IO_SRC, "clk_mac2io_src", mux_2plls_p, 0,
0666 RK3328_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 5, DFLAGS,
0667 RK3328_CLKGATE_CON(3), 1, GFLAGS),
0668 GATE(SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", 0,
0669 RK3328_CLKGATE_CON(9), 7, GFLAGS),
0670 GATE(SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", 0,
0671 RK3328_CLKGATE_CON(9), 4, GFLAGS),
0672 GATE(SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", 0,
0673 RK3328_CLKGATE_CON(9), 5, GFLAGS),
0674 GATE(SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", 0,
0675 RK3328_CLKGATE_CON(9), 6, GFLAGS),
0676 COMPOSITE(SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_p, 0,
0677 RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS,
0678 RK3328_CLKGATE_CON(3), 5, GFLAGS),
0679 MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPARENT,
0680 RK3328_GRF_MAC_CON1, 10, 1, MFLAGS),
0681 MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_NO_REPARENT,
0682 RK3328_GRF_SOC_CON4, 14, 1, MFLAGS),
0683
0684 COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0,
0685 RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS,
0686 RK3328_CLKGATE_CON(3), 0, GFLAGS),
0687 GATE(SCLK_MAC2PHY_REF, "clk_mac2phy_ref", "clk_mac2phy", 0,
0688 RK3328_CLKGATE_CON(9), 3, GFLAGS),
0689 GATE(SCLK_MAC2PHY_RXTX, "clk_mac2phy_rxtx", "clk_mac2phy", 0,
0690 RK3328_CLKGATE_CON(9), 1, GFLAGS),
0691 COMPOSITE_NOMUX(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy", 0,
0692 RK3328_CLKSEL_CON(26), 8, 2, DFLAGS,
0693 RK3328_CLKGATE_CON(9), 2, GFLAGS),
0694 MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p, CLK_SET_RATE_NO_REPARENT,
0695 RK3328_GRF_MAC_CON2, 10, 1, MFLAGS),
0696
0697 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
0698
0699
0700
0701
0702
0703
0704 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(21), 10, GFLAGS),
0705 GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(22), 3, GFLAGS),
0706 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 2, GFLAGS),
0707 GATE(0, "aclk_vop_niu", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 4, GFLAGS),
0708
0709 GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 6, GFLAGS),
0710 GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 8, GFLAGS),
0711 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 15, GFLAGS),
0712 GATE(0, "aclk_vio_niu", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 2, GFLAGS),
0713
0714 GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 3, GFLAGS),
0715 GATE(0, "hclk_vop_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 5, GFLAGS),
0716 GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 7, GFLAGS),
0717 GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 9, GFLAGS),
0718 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 11, GFLAGS),
0719 GATE(0, "hclk_ahb1tom", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 12, GFLAGS),
0720 GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 13, GFLAGS),
0721 GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 14, GFLAGS),
0722 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 0, GFLAGS),
0723 GATE(0, "hclk_vio_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 1, GFLAGS),
0724 GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 4, GFLAGS),
0725 GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 5, GFLAGS),
0726
0727
0728 GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
0729 GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
0730
0731 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
0732 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
0733 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 2, GFLAGS),
0734 GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 15, GFLAGS),
0735 GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 6, GFLAGS),
0736 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 7, GFLAGS),
0737 GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 8, GFLAGS),
0738 GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 9, GFLAGS),
0739 GATE(0, "hclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 12, GFLAGS),
0740 GATE(0, "pclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 13, GFLAGS),
0741
0742
0743 GATE(ACLK_MAC2PHY, "aclk_mac2phy", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 0, GFLAGS),
0744 GATE(ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 2, GFLAGS),
0745 GATE(0, "aclk_gmac_niu", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 4, GFLAGS),
0746 GATE(PCLK_MAC2PHY, "pclk_mac2phy", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 1, GFLAGS),
0747 GATE(PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 3, GFLAGS),
0748 GATE(0, "pclk_gmac_niu", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 5, GFLAGS),
0749
0750
0751 GATE(0, "aclk_bus_niu", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 12, GFLAGS),
0752 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 11, GFLAGS),
0753 GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 12, GFLAGS),
0754 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 0, GFLAGS),
0755 GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 1, GFLAGS),
0756
0757 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 2, GFLAGS),
0758 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 3, GFLAGS),
0759 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 4, GFLAGS),
0760 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 5, GFLAGS),
0761 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 6, GFLAGS),
0762 GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 11, GFLAGS),
0763 GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 7, GFLAGS),
0764 GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 8, GFLAGS),
0765 GATE(0, "hclk_bus_niu", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 13, GFLAGS),
0766 GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(28), 0, GFLAGS),
0767
0768 GATE(0, "pclk_bus_niu", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 14, GFLAGS),
0769 GATE(0, "pclk_efuse", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 9, GFLAGS),
0770 GATE(0, "pclk_otp", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 4, GFLAGS),
0771 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 10, GFLAGS),
0772 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 0, GFLAGS),
0773 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 1, GFLAGS),
0774 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 2, GFLAGS),
0775 GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 3, GFLAGS),
0776 GATE(0, "pclk_stimer", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 4, GFLAGS),
0777 GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 5, GFLAGS),
0778 GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 6, GFLAGS),
0779 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 7, GFLAGS),
0780 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 8, GFLAGS),
0781 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 9, GFLAGS),
0782 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 10, GFLAGS),
0783 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 11, GFLAGS),
0784 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 12, GFLAGS),
0785 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 13, GFLAGS),
0786 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 14, GFLAGS),
0787 GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 15, GFLAGS),
0788 GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 0, GFLAGS),
0789 GATE(0, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 4, GFLAGS),
0790 GATE(0, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 6, GFLAGS),
0791 GATE(0, "pclk_sim", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 10, GFLAGS),
0792 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 15, GFLAGS),
0793 GATE(0, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 3, GFLAGS),
0794
0795
0796 SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),
0797
0798 GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 1, GFLAGS),
0799 GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 2, GFLAGS),
0800 GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 2, GFLAGS),
0801 GATE(PCLK_USB2_GRF, "pclk_usb2_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 14, GFLAGS),
0802 GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 13, GFLAGS),
0803 GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(17), 5, GFLAGS),
0804 GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 7, GFLAGS),
0805 GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 8, GFLAGS),
0806 GATE(0, "pclk_phy_niu", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(15), 15, GFLAGS),
0807
0808
0809 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
0810 RK3328_SDMMC_CON0, 1),
0811 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
0812 RK3328_SDMMC_CON1, 1),
0813
0814 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
0815 RK3328_SDIO_CON0, 1),
0816 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
0817 RK3328_SDIO_CON1, 1),
0818
0819 MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
0820 RK3328_EMMC_CON0, 1),
0821 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
0822 RK3328_EMMC_CON1, 1),
0823
0824 MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext",
0825 RK3328_SDMMC_EXT_CON0, 1),
0826 MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext",
0827 RK3328_SDMMC_EXT_CON1, 1),
0828 };
0829
0830 static const char *const rk3328_critical_clocks[] __initconst = {
0831 "aclk_bus",
0832 "aclk_bus_niu",
0833 "pclk_bus",
0834 "pclk_bus_niu",
0835 "hclk_bus",
0836 "hclk_bus_niu",
0837 "aclk_peri",
0838 "hclk_peri",
0839 "hclk_peri_niu",
0840 "pclk_peri",
0841 "pclk_peri_niu",
0842 "pclk_dbg",
0843 "aclk_core_niu",
0844 "aclk_gic400",
0845 "aclk_intmem",
0846 "hclk_rom",
0847 "pclk_grf",
0848 "pclk_cru",
0849 "pclk_sgrf",
0850 "pclk_timer0",
0851 "clk_timer0",
0852 "pclk_ddr_msch",
0853 "pclk_ddr_mon",
0854 "pclk_ddr_grf",
0855 "clk_ddrupctl",
0856 "clk_ddrmsch",
0857 "hclk_ahb1tom",
0858 "clk_jtag",
0859 "pclk_ddrphy",
0860 "pclk_pmu",
0861 "hclk_otg_pmu",
0862 "aclk_rga_niu",
0863 "pclk_vio_h2p",
0864 "hclk_vio_h2p",
0865 "aclk_vio_niu",
0866 "hclk_vio_niu",
0867 "aclk_vop_niu",
0868 "hclk_vop_niu",
0869 "aclk_gpu_niu",
0870 "aclk_rkvdec_niu",
0871 "hclk_rkvdec_niu",
0872 "aclk_vpu_niu",
0873 "hclk_vpu_niu",
0874 "aclk_rkvenc_niu",
0875 "hclk_rkvenc_niu",
0876 "aclk_gmac_niu",
0877 "pclk_gmac_niu",
0878 "pclk_phy_niu",
0879 };
0880
0881 static void __init rk3328_clk_init(struct device_node *np)
0882 {
0883 struct rockchip_clk_provider *ctx;
0884 void __iomem *reg_base;
0885
0886 reg_base = of_iomap(np, 0);
0887 if (!reg_base) {
0888 pr_err("%s: could not map cru region\n", __func__);
0889 return;
0890 }
0891
0892 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
0893 if (IS_ERR(ctx)) {
0894 pr_err("%s: rockchip clk init failed\n", __func__);
0895 iounmap(reg_base);
0896 return;
0897 }
0898
0899 rockchip_clk_register_plls(ctx, rk3328_pll_clks,
0900 ARRAY_SIZE(rk3328_pll_clks),
0901 RK3328_GRF_SOC_STATUS0);
0902 rockchip_clk_register_branches(ctx, rk3328_clk_branches,
0903 ARRAY_SIZE(rk3328_clk_branches));
0904 rockchip_clk_protect_critical(rk3328_critical_clocks,
0905 ARRAY_SIZE(rk3328_critical_clocks));
0906
0907 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
0908 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
0909 &rk3328_cpuclk_data, rk3328_cpuclk_rates,
0910 ARRAY_SIZE(rk3328_cpuclk_rates));
0911
0912 rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0),
0913 ROCKCHIP_SOFTRST_HIWORD_MASK);
0914
0915 rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL);
0916
0917 rockchip_clk_of_add_provider(np, ctx);
0918 }
0919 CLK_OF_DECLARE(rk3328_cru, "rockchip,rk3328-cru", rk3328_clk_init);
