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0007 #include <linux/clk-provider.h>
0008 #include <linux/io.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/syscore_ops.h>
0012 #include <dt-bindings/clock/rk3308-cru.h>
0013 #include "clk.h"
0014
0015 #define RK3308_GRF_SOC_STATUS0 0x380
0016
0017 enum rk3308_plls {
0018 apll, dpll, vpll0, vpll1,
0019 };
0020
0021 static struct rockchip_pll_rate_table rk3308_pll_rates[] = {
0022
0023 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
0024 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
0025 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
0026 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
0027 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
0028 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
0029 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
0030 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
0031 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
0032 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
0033 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
0034 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
0035 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
0036 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
0037 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
0038 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
0039 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
0040 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
0041 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
0042 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
0043 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
0044 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
0045 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
0046 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
0047 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
0048 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
0049 RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
0050 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
0051 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
0052 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
0053 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
0054 RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
0055 RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
0056 RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
0057 RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0),
0058 RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
0059 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
0060 RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
0061 RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
0062 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
0063 RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
0064 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
0065 RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
0066 { },
0067 };
0068
0069 #define RK3308_DIV_ACLKM_MASK 0x7
0070 #define RK3308_DIV_ACLKM_SHIFT 12
0071 #define RK3308_DIV_PCLK_DBG_MASK 0xf
0072 #define RK3308_DIV_PCLK_DBG_SHIFT 8
0073
0074 #define RK3308_CLKSEL0(_aclk_core, _pclk_dbg) \
0075 { \
0076 .reg = RK3308_CLKSEL_CON(0), \
0077 .val = HIWORD_UPDATE(_aclk_core, RK3308_DIV_ACLKM_MASK, \
0078 RK3308_DIV_ACLKM_SHIFT) | \
0079 HIWORD_UPDATE(_pclk_dbg, RK3308_DIV_PCLK_DBG_MASK, \
0080 RK3308_DIV_PCLK_DBG_SHIFT), \
0081 }
0082
0083 #define RK3308_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
0084 { \
0085 .prate = _prate, \
0086 .divs = { \
0087 RK3308_CLKSEL0(_aclk_core, _pclk_dbg), \
0088 }, \
0089 }
0090
0091 static struct rockchip_cpuclk_rate_table rk3308_cpuclk_rates[] __initdata = {
0092 RK3308_CPUCLK_RATE(1608000000, 1, 7),
0093 RK3308_CPUCLK_RATE(1512000000, 1, 7),
0094 RK3308_CPUCLK_RATE(1488000000, 1, 5),
0095 RK3308_CPUCLK_RATE(1416000000, 1, 5),
0096 RK3308_CPUCLK_RATE(1392000000, 1, 5),
0097 RK3308_CPUCLK_RATE(1296000000, 1, 5),
0098 RK3308_CPUCLK_RATE(1200000000, 1, 5),
0099 RK3308_CPUCLK_RATE(1104000000, 1, 5),
0100 RK3308_CPUCLK_RATE(1008000000, 1, 5),
0101 RK3308_CPUCLK_RATE(912000000, 1, 5),
0102 RK3308_CPUCLK_RATE(816000000, 1, 3),
0103 RK3308_CPUCLK_RATE(696000000, 1, 3),
0104 RK3308_CPUCLK_RATE(600000000, 1, 3),
0105 RK3308_CPUCLK_RATE(408000000, 1, 1),
0106 RK3308_CPUCLK_RATE(312000000, 1, 1),
0107 RK3308_CPUCLK_RATE(216000000, 1, 1),
0108 RK3308_CPUCLK_RATE(96000000, 1, 1),
0109 };
0110
0111 static const struct rockchip_cpuclk_reg_data rk3308_cpuclk_data = {
0112 .core_reg[0] = RK3308_CLKSEL_CON(0),
0113 .div_core_shift[0] = 0,
0114 .div_core_mask[0] = 0xf,
0115 .num_cores = 1,
0116 .mux_core_alt = 1,
0117 .mux_core_main = 0,
0118 .mux_core_shift = 6,
0119 .mux_core_mask = 0x3,
0120 };
0121
0122 PNAME(mux_pll_p) = { "xin24m" };
0123 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
0124 PNAME(mux_armclk_p) = { "apll_core", "vpll0_core", "vpll1_core" };
0125 PNAME(mux_dpll_vpll0_p) = { "dpll", "vpll0" };
0126 PNAME(mux_dpll_vpll0_xin24m_p) = { "dpll", "vpll0", "xin24m" };
0127 PNAME(mux_dpll_vpll0_vpll1_p) = { "dpll", "vpll0", "vpll1" };
0128 PNAME(mux_dpll_vpll0_vpll1_xin24m_p) = { "dpll", "vpll0", "vpll1", "xin24m" };
0129 PNAME(mux_dpll_vpll0_vpll1_usb480m_xin24m_p) = { "dpll", "vpll0", "vpll1", "usb480m", "xin24m" };
0130 PNAME(mux_vpll0_vpll1_p) = { "vpll0", "vpll1" };
0131 PNAME(mux_vpll0_vpll1_xin24m_p) = { "vpll0", "vpll1", "xin24m" };
0132 PNAME(mux_uart0_p) = { "clk_uart0_src", "dummy", "clk_uart0_frac" };
0133 PNAME(mux_uart1_p) = { "clk_uart1_src", "dummy", "clk_uart1_frac" };
0134 PNAME(mux_uart2_p) = { "clk_uart2_src", "dummy", "clk_uart2_frac" };
0135 PNAME(mux_uart3_p) = { "clk_uart3_src", "dummy", "clk_uart3_frac" };
0136 PNAME(mux_uart4_p) = { "clk_uart4_src", "dummy", "clk_uart4_frac" };
0137 PNAME(mux_dclk_vop_p) = { "dclk_vop_src", "dclk_vop_frac", "xin24m" };
0138 PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" };
0139 PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
0140 PNAME(mux_sdio_p) = { "clk_sdio_div", "clk_sdio_div50" };
0141 PNAME(mux_emmc_p) = { "clk_emmc_div", "clk_emmc_div50" };
0142 PNAME(mux_mac_p) = { "clk_mac_src", "mac_clkin" };
0143 PNAME(mux_mac_rmii_sel_p) = { "clk_mac_rx_tx_div20", "clk_mac_rx_tx_div2" };
0144 PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x_out", "clk_ddr_stdby_div4" };
0145 PNAME(mux_rtc32k_p) = { "xin32k", "clk_pvtm_32k", "clk_rtc32k_frac", "clk_rtc32k_div" };
0146 PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_usbphy_ref_src" };
0147 PNAME(mux_wifi_src_p) = { "clk_wifi_dpll", "clk_wifi_vpll0" };
0148 PNAME(mux_wifi_p) = { "clk_wifi_osc", "clk_wifi_src" };
0149 PNAME(mux_pdm_p) = { "clk_pdm_src", "clk_pdm_frac" };
0150 PNAME(mux_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "mclk_i2s0_8ch_in" };
0151 PNAME(mux_i2s0_8ch_tx_rx_p) = { "clk_i2s0_8ch_tx_mux", "clk_i2s0_8ch_rx_mux"};
0152 PNAME(mux_i2s0_8ch_tx_out_p) = { "clk_i2s0_8ch_tx", "xin12m" };
0153 PNAME(mux_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "mclk_i2s0_8ch_in" };
0154 PNAME(mux_i2s0_8ch_rx_tx_p) = { "clk_i2s0_8ch_rx_mux", "clk_i2s0_8ch_tx_mux"};
0155 PNAME(mux_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "mclk_i2s1_8ch_in" };
0156 PNAME(mux_i2s1_8ch_tx_rx_p) = { "clk_i2s1_8ch_tx_mux", "clk_i2s1_8ch_rx_mux"};
0157 PNAME(mux_i2s1_8ch_tx_out_p) = { "clk_i2s1_8ch_tx", "xin12m" };
0158 PNAME(mux_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "mclk_i2s1_8ch_in" };
0159 PNAME(mux_i2s1_8ch_rx_tx_p) = { "clk_i2s1_8ch_rx_mux", "clk_i2s1_8ch_tx_mux"};
0160 PNAME(mux_i2s2_8ch_tx_p) = { "clk_i2s2_8ch_tx_src", "clk_i2s2_8ch_tx_frac", "mclk_i2s2_8ch_in" };
0161 PNAME(mux_i2s2_8ch_tx_rx_p) = { "clk_i2s2_8ch_tx_mux", "clk_i2s2_8ch_rx_mux"};
0162 PNAME(mux_i2s2_8ch_tx_out_p) = { "clk_i2s2_8ch_tx", "xin12m" };
0163 PNAME(mux_i2s2_8ch_rx_p) = { "clk_i2s2_8ch_rx_src", "clk_i2s2_8ch_rx_frac", "mclk_i2s2_8ch_in" };
0164 PNAME(mux_i2s2_8ch_rx_tx_p) = { "clk_i2s2_8ch_rx_mux", "clk_i2s2_8ch_tx_mux"};
0165 PNAME(mux_i2s3_8ch_tx_p) = { "clk_i2s3_8ch_tx_src", "clk_i2s3_8ch_tx_frac", "mclk_i2s3_8ch_in" };
0166 PNAME(mux_i2s3_8ch_tx_rx_p) = { "clk_i2s3_8ch_tx_mux", "clk_i2s3_8ch_rx_mux"};
0167 PNAME(mux_i2s3_8ch_tx_out_p) = { "clk_i2s3_8ch_tx", "xin12m" };
0168 PNAME(mux_i2s3_8ch_rx_p) = { "clk_i2s3_8ch_rx_src", "clk_i2s3_8ch_rx_frac", "mclk_i2s3_8ch_in" };
0169 PNAME(mux_i2s3_8ch_rx_tx_p) = { "clk_i2s3_8ch_rx_mux", "clk_i2s3_8ch_tx_mux"};
0170 PNAME(mux_i2s0_2ch_p) = { "clk_i2s0_2ch_src", "clk_i2s0_2ch_frac", "mclk_i2s0_2ch_in" };
0171 PNAME(mux_i2s0_2ch_out_p) = { "clk_i2s0_2ch", "xin12m" };
0172 PNAME(mux_i2s1_2ch_p) = { "clk_i2s1_2ch_src", "clk_i2s1_2ch_frac", "mclk_i2s1_2ch_in"};
0173 PNAME(mux_i2s1_2ch_out_p) = { "clk_i2s1_2ch", "xin12m" };
0174 PNAME(mux_spdif_tx_src_p) = { "clk_spdif_tx_div", "clk_spdif_tx_div50" };
0175 PNAME(mux_spdif_tx_p) = { "clk_spdif_tx_src", "clk_spdif_tx_frac", "mclk_i2s0_2ch_in" };
0176 PNAME(mux_spdif_rx_src_p) = { "clk_spdif_rx_div", "clk_spdif_rx_div50" };
0177 PNAME(mux_spdif_rx_p) = { "clk_spdif_rx_src", "clk_spdif_rx_frac" };
0178
0179 static struct rockchip_pll_clock rk3308_pll_clks[] __initdata = {
0180 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
0181 0, RK3308_PLL_CON(0),
0182 RK3308_MODE_CON, 0, 0, 0, rk3308_pll_rates),
0183 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
0184 0, RK3308_PLL_CON(8),
0185 RK3308_MODE_CON, 2, 1, 0, rk3308_pll_rates),
0186 [vpll0] = PLL(pll_rk3328, PLL_VPLL0, "vpll0", mux_pll_p,
0187 0, RK3308_PLL_CON(16),
0188 RK3308_MODE_CON, 4, 2, 0, rk3308_pll_rates),
0189 [vpll1] = PLL(pll_rk3328, PLL_VPLL1, "vpll1", mux_pll_p,
0190 0, RK3308_PLL_CON(24),
0191 RK3308_MODE_CON, 6, 3, 0, rk3308_pll_rates),
0192 };
0193
0194 #define MFLAGS CLK_MUX_HIWORD_MASK
0195 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
0196 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
0197
0198 static struct rockchip_clk_branch rk3308_uart0_fracmux __initdata =
0199 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
0200 RK3308_CLKSEL_CON(11), 14, 2, MFLAGS);
0201
0202 static struct rockchip_clk_branch rk3308_uart1_fracmux __initdata =
0203 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
0204 RK3308_CLKSEL_CON(14), 14, 2, MFLAGS);
0205
0206 static struct rockchip_clk_branch rk3308_uart2_fracmux __initdata =
0207 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
0208 RK3308_CLKSEL_CON(17), 14, 2, MFLAGS);
0209
0210 static struct rockchip_clk_branch rk3308_uart3_fracmux __initdata =
0211 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
0212 RK3308_CLKSEL_CON(20), 14, 2, MFLAGS);
0213
0214 static struct rockchip_clk_branch rk3308_uart4_fracmux __initdata =
0215 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
0216 RK3308_CLKSEL_CON(23), 14, 2, MFLAGS);
0217
0218 static struct rockchip_clk_branch rk3308_dclk_vop_fracmux __initdata =
0219 MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
0220 RK3308_CLKSEL_CON(8), 14, 2, MFLAGS);
0221
0222 static struct rockchip_clk_branch rk3308_rtc32k_fracmux __initdata =
0223 MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
0224 RK3308_CLKSEL_CON(2), 8, 2, MFLAGS);
0225
0226 static struct rockchip_clk_branch rk3308_pdm_fracmux __initdata =
0227 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
0228 RK3308_CLKSEL_CON(46), 15, 1, MFLAGS);
0229
0230 static struct rockchip_clk_branch rk3308_i2s0_8ch_tx_fracmux __initdata =
0231 MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
0232 RK3308_CLKSEL_CON(52), 10, 2, MFLAGS);
0233
0234 static struct rockchip_clk_branch rk3308_i2s0_8ch_rx_fracmux __initdata =
0235 MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
0236 RK3308_CLKSEL_CON(54), 10, 2, MFLAGS);
0237
0238 static struct rockchip_clk_branch rk3308_i2s1_8ch_tx_fracmux __initdata =
0239 MUX(SCLK_I2S1_8CH_TX_MUX, "clk_i2s1_8ch_tx_mux", mux_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
0240 RK3308_CLKSEL_CON(56), 10, 2, MFLAGS);
0241
0242 static struct rockchip_clk_branch rk3308_i2s1_8ch_rx_fracmux __initdata =
0243 MUX(SCLK_I2S1_8CH_RX_MUX, "clk_i2s1_8ch_rx_mux", mux_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
0244 RK3308_CLKSEL_CON(58), 10, 2, MFLAGS);
0245
0246 static struct rockchip_clk_branch rk3308_i2s2_8ch_tx_fracmux __initdata =
0247 MUX(SCLK_I2S2_8CH_TX_MUX, "clk_i2s2_8ch_tx_mux", mux_i2s2_8ch_tx_p, CLK_SET_RATE_PARENT,
0248 RK3308_CLKSEL_CON(60), 10, 2, MFLAGS);
0249
0250 static struct rockchip_clk_branch rk3308_i2s2_8ch_rx_fracmux __initdata =
0251 MUX(SCLK_I2S2_8CH_RX_MUX, "clk_i2s2_8ch_rx_mux", mux_i2s2_8ch_rx_p, CLK_SET_RATE_PARENT,
0252 RK3308_CLKSEL_CON(62), 10, 2, MFLAGS);
0253
0254 static struct rockchip_clk_branch rk3308_i2s3_8ch_tx_fracmux __initdata =
0255 MUX(SCLK_I2S3_8CH_TX_MUX, "clk_i2s3_8ch_tx_mux", mux_i2s3_8ch_tx_p, CLK_SET_RATE_PARENT,
0256 RK3308_CLKSEL_CON(64), 10, 2, MFLAGS);
0257
0258 static struct rockchip_clk_branch rk3308_i2s3_8ch_rx_fracmux __initdata =
0259 MUX(SCLK_I2S3_8CH_RX_MUX, "clk_i2s3_8ch_rx_mux", mux_i2s3_8ch_rx_p, CLK_SET_RATE_PARENT,
0260 RK3308_CLKSEL_CON(66), 10, 2, MFLAGS);
0261
0262 static struct rockchip_clk_branch rk3308_i2s0_2ch_fracmux __initdata =
0263 MUX(0, "clk_i2s0_2ch_mux", mux_i2s0_2ch_p, CLK_SET_RATE_PARENT,
0264 RK3308_CLKSEL_CON(68), 10, 2, MFLAGS);
0265
0266 static struct rockchip_clk_branch rk3308_i2s1_2ch_fracmux __initdata =
0267 MUX(0, "clk_i2s1_2ch_mux", mux_i2s1_2ch_p, CLK_SET_RATE_PARENT,
0268 RK3308_CLKSEL_CON(70), 10, 2, MFLAGS);
0269
0270 static struct rockchip_clk_branch rk3308_spdif_tx_fracmux __initdata =
0271 MUX(0, "clk_spdif_tx_mux", mux_spdif_tx_p, CLK_SET_RATE_PARENT,
0272 RK3308_CLKSEL_CON(48), 14, 2, MFLAGS);
0273
0274 static struct rockchip_clk_branch rk3308_spdif_rx_fracmux __initdata =
0275 MUX(0, "clk_spdif_rx_mux", mux_spdif_rx_p, CLK_SET_RATE_PARENT,
0276 RK3308_CLKSEL_CON(50), 15, 1, MFLAGS);
0277
0278
0279 static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
0280
0281
0282
0283
0284 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
0285 RK3308_MODE_CON, 8, 2, MFLAGS),
0286 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
0287
0288
0289
0290
0291
0292 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
0293 RK3308_CLKGATE_CON(0), 0, GFLAGS),
0294 GATE(0, "vpll0_core", "vpll0", CLK_IGNORE_UNUSED,
0295 RK3308_CLKGATE_CON(0), 0, GFLAGS),
0296 GATE(0, "vpll1_core", "vpll1", CLK_IGNORE_UNUSED,
0297 RK3308_CLKGATE_CON(0), 0, GFLAGS),
0298 COMPOSITE_NOMUX(0, "pclk_core_dbg", "armclk", CLK_IGNORE_UNUSED,
0299 RK3308_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
0300 RK3308_CLKGATE_CON(0), 2, GFLAGS),
0301 COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
0302 RK3308_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
0303 RK3308_CLKGATE_CON(0), 1, GFLAGS),
0304
0305 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
0306 RK3308_CLKGATE_CON(0), 3, GFLAGS),
0307
0308 GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
0309 RK3308_CLKGATE_CON(0), 4, GFLAGS),
0310
0311
0312
0313
0314
0315 COMPOSITE_NODIV(ACLK_BUS_SRC, "clk_bus_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
0316 RK3308_CLKSEL_CON(5), 6, 2, MFLAGS,
0317 RK3308_CLKGATE_CON(1), 0, GFLAGS),
0318 COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
0319 RK3308_CLKSEL_CON(6), 8, 5, DFLAGS,
0320 RK3308_CLKGATE_CON(1), 3, GFLAGS),
0321 GATE(PCLK_DDR, "pclk_ddr", "pclk_bus", CLK_IGNORE_UNUSED,
0322 RK3308_CLKGATE_CON(4), 15, GFLAGS),
0323 COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
0324 RK3308_CLKSEL_CON(6), 0, 5, DFLAGS,
0325 RK3308_CLKGATE_CON(1), 2, GFLAGS),
0326 COMPOSITE_NOMUX(ACLK_BUS, "aclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
0327 RK3308_CLKSEL_CON(5), 0, 5, DFLAGS,
0328 RK3308_CLKGATE_CON(1), 1, GFLAGS),
0329
0330 COMPOSITE(0, "clk_uart0_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
0331 RK3308_CLKSEL_CON(10), 13, 3, MFLAGS, 0, 5, DFLAGS,
0332 RK3308_CLKGATE_CON(1), 9, GFLAGS),
0333 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
0334 RK3308_CLKSEL_CON(12), 0,
0335 RK3308_CLKGATE_CON(1), 11, GFLAGS,
0336 &rk3308_uart0_fracmux),
0337 GATE(SCLK_UART0, "clk_uart0", "clk_uart0_mux", 0,
0338 RK3308_CLKGATE_CON(1), 12, GFLAGS),
0339
0340 COMPOSITE(0, "clk_uart1_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
0341 RK3308_CLKSEL_CON(13), 13, 3, MFLAGS, 0, 5, DFLAGS,
0342 RK3308_CLKGATE_CON(1), 13, GFLAGS),
0343 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
0344 RK3308_CLKSEL_CON(15), 0,
0345 RK3308_CLKGATE_CON(1), 15, GFLAGS,
0346 &rk3308_uart1_fracmux),
0347 GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
0348 RK3308_CLKGATE_CON(2), 0, GFLAGS),
0349
0350 COMPOSITE(0, "clk_uart2_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
0351 RK3308_CLKSEL_CON(16), 13, 3, MFLAGS, 0, 5, DFLAGS,
0352 RK3308_CLKGATE_CON(2), 1, GFLAGS),
0353 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
0354 RK3308_CLKSEL_CON(18), 0,
0355 RK3308_CLKGATE_CON(2), 3, GFLAGS,
0356 &rk3308_uart2_fracmux),
0357 GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
0358 RK3308_CLKGATE_CON(2), 4, GFLAGS),
0359
0360 COMPOSITE(0, "clk_uart3_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
0361 RK3308_CLKSEL_CON(19), 13, 3, MFLAGS, 0, 5, DFLAGS,
0362 RK3308_CLKGATE_CON(2), 5, GFLAGS),
0363 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
0364 RK3308_CLKSEL_CON(21), 0,
0365 RK3308_CLKGATE_CON(2), 7, GFLAGS,
0366 &rk3308_uart3_fracmux),
0367 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
0368 RK3308_CLKGATE_CON(2), 8, GFLAGS),
0369
0370 COMPOSITE(0, "clk_uart4_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
0371 RK3308_CLKSEL_CON(22), 13, 3, MFLAGS, 0, 5, DFLAGS,
0372 RK3308_CLKGATE_CON(2), 9, GFLAGS),
0373 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
0374 RK3308_CLKSEL_CON(24), 0,
0375 RK3308_CLKGATE_CON(2), 11, GFLAGS,
0376 &rk3308_uart4_fracmux),
0377 GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0,
0378 RK3308_CLKGATE_CON(2), 12, GFLAGS),
0379
0380 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_dpll_vpll0_xin24m_p, 0,
0381 RK3308_CLKSEL_CON(25), 14, 2, MFLAGS, 0, 7, DFLAGS,
0382 RK3308_CLKGATE_CON(2), 13, GFLAGS),
0383 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_dpll_vpll0_xin24m_p, 0,
0384 RK3308_CLKSEL_CON(26), 14, 2, MFLAGS, 0, 7, DFLAGS,
0385 RK3308_CLKGATE_CON(2), 14, GFLAGS),
0386 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_dpll_vpll0_xin24m_p, 0,
0387 RK3308_CLKSEL_CON(27), 14, 2, MFLAGS, 0, 7, DFLAGS,
0388 RK3308_CLKGATE_CON(2), 15, GFLAGS),
0389 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_dpll_vpll0_xin24m_p, 0,
0390 RK3308_CLKSEL_CON(28), 14, 2, MFLAGS, 0, 7, DFLAGS,
0391 RK3308_CLKGATE_CON(3), 0, GFLAGS),
0392
0393 COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_dpll_vpll0_xin24m_p, 0,
0394 RK3308_CLKSEL_CON(29), 14, 2, MFLAGS, 0, 7, DFLAGS,
0395 RK3308_CLKGATE_CON(3), 1, GFLAGS),
0396 COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_dpll_vpll0_xin24m_p, 0,
0397 RK3308_CLKSEL_CON(74), 14, 2, MFLAGS, 0, 7, DFLAGS,
0398 RK3308_CLKGATE_CON(15), 0, GFLAGS),
0399 COMPOSITE(SCLK_PWM2, "clk_pwm2", mux_dpll_vpll0_xin24m_p, 0,
0400 RK3308_CLKSEL_CON(75), 14, 2, MFLAGS, 0, 7, DFLAGS,
0401 RK3308_CLKGATE_CON(15), 1, GFLAGS),
0402
0403 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_dpll_vpll0_xin24m_p, 0,
0404 RK3308_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 7, DFLAGS,
0405 RK3308_CLKGATE_CON(3), 2, GFLAGS),
0406 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_dpll_vpll0_xin24m_p, 0,
0407 RK3308_CLKSEL_CON(31), 14, 2, MFLAGS, 0, 7, DFLAGS,
0408 RK3308_CLKGATE_CON(3), 3, GFLAGS),
0409 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_dpll_vpll0_xin24m_p, 0,
0410 RK3308_CLKSEL_CON(32), 14, 2, MFLAGS, 0, 7, DFLAGS,
0411 RK3308_CLKGATE_CON(3), 4, GFLAGS),
0412
0413 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
0414 RK3308_CLKGATE_CON(3), 10, GFLAGS),
0415 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
0416 RK3308_CLKGATE_CON(3), 11, GFLAGS),
0417 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
0418 RK3308_CLKGATE_CON(3), 12, GFLAGS),
0419 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
0420 RK3308_CLKGATE_CON(3), 13, GFLAGS),
0421 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
0422 RK3308_CLKGATE_CON(3), 14, GFLAGS),
0423 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
0424 RK3308_CLKGATE_CON(3), 15, GFLAGS),
0425
0426 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
0427 RK3308_CLKSEL_CON(33), 0, 11, DFLAGS,
0428 RK3308_CLKGATE_CON(3), 5, GFLAGS),
0429 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
0430 RK3308_CLKSEL_CON(34), 0, 11, DFLAGS,
0431 RK3308_CLKGATE_CON(3), 6, GFLAGS),
0432
0433 COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
0434 RK3308_CLKSEL_CON(35), 0, 4, DFLAGS,
0435 RK3308_CLKGATE_CON(3), 7, GFLAGS),
0436 COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0,
0437 RK3308_CLKSEL_CON(35), 4, 2, DFLAGS,
0438 RK3308_CLKGATE_CON(3), 8, GFLAGS),
0439
0440 GATE(SCLK_CPU_BOOST, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
0441 RK3308_CLKGATE_CON(3), 9, GFLAGS),
0442
0443 COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_dpll_vpll0_vpll1_p, 0,
0444 RK3308_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
0445 RK3308_CLKGATE_CON(1), 4, GFLAGS),
0446 COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_dpll_vpll0_vpll1_p, 0,
0447 RK3308_CLKSEL_CON(7), 14, 2, MFLAGS, 8, 5, DFLAGS,
0448 RK3308_CLKGATE_CON(1), 5, GFLAGS),
0449
0450 COMPOSITE(0, "dclk_vop_src", mux_dpll_vpll0_vpll1_p, 0,
0451 RK3308_CLKSEL_CON(8), 10, 2, MFLAGS, 0, 8, DFLAGS,
0452 RK3308_CLKGATE_CON(1), 6, GFLAGS),
0453 COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
0454 RK3308_CLKSEL_CON(9), 0,
0455 RK3308_CLKGATE_CON(1), 7, GFLAGS,
0456 &rk3308_dclk_vop_fracmux),
0457 GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
0458 RK3308_CLKGATE_CON(1), 8, GFLAGS),
0459
0460
0461
0462
0463
0464 COMPOSITE_NODIV(ACLK_PERI_SRC, "clk_peri_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
0465 RK3308_CLKSEL_CON(36), 6, 2, MFLAGS,
0466 RK3308_CLKGATE_CON(8), 0, GFLAGS),
0467 COMPOSITE_NOMUX(ACLK_PERI, "aclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
0468 RK3308_CLKSEL_CON(36), 0, 5, DFLAGS,
0469 RK3308_CLKGATE_CON(8), 1, GFLAGS),
0470 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
0471 RK3308_CLKSEL_CON(37), 0, 5, DFLAGS,
0472 RK3308_CLKGATE_CON(8), 2, GFLAGS),
0473 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
0474 RK3308_CLKSEL_CON(37), 8, 5, DFLAGS,
0475 RK3308_CLKGATE_CON(8), 3, GFLAGS),
0476
0477 COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
0478 RK3308_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
0479 RK3308_CLKGATE_CON(8), 4, GFLAGS),
0480 COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
0481 RK3308_CLKSEL_CON(38), 6, 2, MFLAGS, 0, 5, DFLAGS,
0482 RK3308_CLKGATE_CON(8), 4, GFLAGS),
0483 COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0484 RK3308_CLKSEL_CON(38), 15, 1, MFLAGS,
0485 RK3308_CLKGATE_CON(8), 5, GFLAGS),
0486
0487 COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
0488 RK3308_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS,
0489 RK3308_CLKGATE_CON(8), 6, GFLAGS),
0490 COMPOSITE(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
0491 RK3308_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS,
0492 RK3308_CLKGATE_CON(8), 6, GFLAGS),
0493 COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0494 RK3308_CLKSEL_CON(39), 15, 1, MFLAGS,
0495 RK3308_CLKGATE_CON(8), 7, GFLAGS),
0496 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3308_SDMMC_CON0, 1),
0497 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3308_SDMMC_CON1, 1),
0498
0499 COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
0500 RK3308_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS,
0501 RK3308_CLKGATE_CON(8), 8, GFLAGS),
0502 COMPOSITE(SCLK_SDIO_DIV50, "clk_sdio_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
0503 RK3308_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS,
0504 RK3308_CLKGATE_CON(8), 8, GFLAGS),
0505 COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0506 RK3308_CLKSEL_CON(40), 15, 1, MFLAGS,
0507 RK3308_CLKGATE_CON(8), 9, GFLAGS),
0508 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3308_SDIO_CON0, 1),
0509 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3308_SDIO_CON1, 1),
0510
0511 COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
0512 RK3308_CLKSEL_CON(41), 8, 2, MFLAGS, 0, 8, DFLAGS,
0513 RK3308_CLKGATE_CON(8), 10, GFLAGS),
0514 COMPOSITE(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_dpll_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
0515 RK3308_CLKSEL_CON(41), 8, 2, MFLAGS, 0, 8, DFLAGS,
0516 RK3308_CLKGATE_CON(8), 10, GFLAGS),
0517 COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0518 RK3308_CLKSEL_CON(41), 15, 1, MFLAGS,
0519 RK3308_CLKGATE_CON(8), 11, GFLAGS),
0520 MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RK3308_EMMC_CON0, 1),
0521 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RK3308_EMMC_CON1, 1),
0522
0523 COMPOSITE(SCLK_SFC, "clk_sfc", mux_dpll_vpll0_vpll1_p, 0,
0524 RK3308_CLKSEL_CON(42), 14, 2, MFLAGS, 0, 7, DFLAGS,
0525 RK3308_CLKGATE_CON(8), 12, GFLAGS),
0526
0527 GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k", 0,
0528 RK3308_CLKGATE_CON(8), 13, GFLAGS),
0529
0530 COMPOSITE(SCLK_MAC_SRC, "clk_mac_src", mux_dpll_vpll0_vpll1_p, 0,
0531 RK3308_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
0532 RK3308_CLKGATE_CON(8), 14, GFLAGS),
0533 MUX(SCLK_MAC, "clk_mac", mux_mac_p, CLK_SET_RATE_PARENT,
0534 RK3308_CLKSEL_CON(43), 14, 1, MFLAGS),
0535 GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_mac", 0,
0536 RK3308_CLKGATE_CON(9), 1, GFLAGS),
0537 GATE(SCLK_MAC_RX_TX, "clk_mac_rx_tx", "clk_mac", 0,
0538 RK3308_CLKGATE_CON(9), 0, GFLAGS),
0539 FACTOR(0, "clk_mac_rx_tx_div2", "clk_mac_rx_tx", 0, 1, 2),
0540 FACTOR(0, "clk_mac_rx_tx_div20", "clk_mac_rx_tx", 0, 1, 20),
0541 MUX(SCLK_MAC_RMII, "clk_mac_rmii_sel", mux_mac_rmii_sel_p, CLK_SET_RATE_PARENT,
0542 RK3308_CLKSEL_CON(43), 15, 1, MFLAGS),
0543
0544 COMPOSITE(SCLK_OWIRE, "clk_owire", mux_dpll_vpll0_xin24m_p, 0,
0545 RK3308_CLKSEL_CON(44), 14, 2, MFLAGS, 8, 6, DFLAGS,
0546 RK3308_CLKGATE_CON(8), 15, GFLAGS),
0547
0548
0549
0550
0551
0552 GATE(0, "clk_ddr_mon_timer", "xin24m", CLK_IGNORE_UNUSED,
0553 RK3308_CLKGATE_CON(0), 12, GFLAGS),
0554
0555 GATE(0, "clk_ddr_mon", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
0556 RK3308_CLKGATE_CON(4), 10, GFLAGS),
0557 GATE(0, "clk_ddr_upctrl", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
0558 RK3308_CLKGATE_CON(4), 11, GFLAGS),
0559 GATE(0, "clk_ddr_msch", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
0560 RK3308_CLKGATE_CON(4), 12, GFLAGS),
0561 GATE(0, "clk_ddr_msch_peribus", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
0562 RK3308_CLKGATE_CON(4), 13, GFLAGS),
0563
0564 COMPOSITE(SCLK_DDRCLK, "clk_ddrphy4x_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
0565 RK3308_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 3, DFLAGS,
0566 RK3308_CLKGATE_CON(0), 10, GFLAGS),
0567 GATE(0, "clk_ddrphy4x", "clk_ddrphy4x_src", CLK_IGNORE_UNUSED,
0568 RK3308_CLKGATE_CON(0), 11, GFLAGS),
0569 FACTOR_GATE(0, "clk_ddr_stdby_div4", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
0570 RK3308_CLKGATE_CON(0), 13, GFLAGS),
0571 COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED,
0572 RK3308_CLKSEL_CON(1), 8, 1, MFLAGS,
0573 RK3308_CLKGATE_CON(4), 14, GFLAGS),
0574
0575
0576
0577
0578
0579 GATE(PCLK_PMU, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED,
0580 RK3308_CLKGATE_CON(4), 5, GFLAGS),
0581 GATE(SCLK_PMU, "clk_pmu", "pclk_bus", CLK_IGNORE_UNUSED,
0582 RK3308_CLKGATE_CON(4), 6, GFLAGS),
0583
0584 COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
0585 RK3308_CLKSEL_CON(3), 0,
0586 RK3308_CLKGATE_CON(4), 3, GFLAGS,
0587 &rk3308_rtc32k_fracmux),
0588 MUX(0, "clk_rtc32k_div_src", mux_vpll0_vpll1_p, 0,
0589 RK3308_CLKSEL_CON(2), 10, 1, MFLAGS),
0590 COMPOSITE_NOMUX(0, "clk_rtc32k_div", "clk_rtc32k_div_src", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
0591 RK3308_CLKSEL_CON(4), 0, 16, DFLAGS,
0592 RK3308_CLKGATE_CON(4), 2, GFLAGS),
0593
0594 COMPOSITE(0, "clk_usbphy_ref_src", mux_dpll_vpll0_p, 0,
0595 RK3308_CLKSEL_CON(72), 6, 1, MFLAGS, 0, 6, DFLAGS,
0596 RK3308_CLKGATE_CON(4), 7, GFLAGS),
0597 COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT,
0598 RK3308_CLKSEL_CON(72), 7, 1, MFLAGS,
0599 RK3308_CLKGATE_CON(4), 8, GFLAGS),
0600
0601 GATE(0, "clk_wifi_dpll", "dpll", 0,
0602 RK3308_CLKGATE_CON(15), 2, GFLAGS),
0603 GATE(0, "clk_wifi_vpll0", "vpll0", 0,
0604 RK3308_CLKGATE_CON(15), 3, GFLAGS),
0605 GATE(0, "clk_wifi_osc", "xin24m", 0,
0606 RK3308_CLKGATE_CON(15), 4, GFLAGS),
0607 COMPOSITE(0, "clk_wifi_src", mux_wifi_src_p, 0,
0608 RK3308_CLKSEL_CON(44), 6, 1, MFLAGS, 0, 6, DFLAGS,
0609 RK3308_CLKGATE_CON(4), 0, GFLAGS),
0610 COMPOSITE_NODIV(SCLK_WIFI, "clk_wifi", mux_wifi_p, CLK_SET_RATE_PARENT,
0611 RK3308_CLKSEL_CON(44), 7, 1, MFLAGS,
0612 RK3308_CLKGATE_CON(4), 1, GFLAGS),
0613
0614 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
0615 RK3308_CLKGATE_CON(4), 4, GFLAGS),
0616
0617
0618
0619
0620
0621 COMPOSITE_NODIV(0, "clk_audio_src", mux_vpll0_vpll1_xin24m_p, 0,
0622 RK3308_CLKSEL_CON(45), 6, 2, MFLAGS,
0623 RK3308_CLKGATE_CON(10), 0, GFLAGS),
0624 COMPOSITE_NOMUX(HCLK_AUDIO, "hclk_audio", "clk_audio_src", 0,
0625 RK3308_CLKSEL_CON(45), 0, 5, DFLAGS,
0626 RK3308_CLKGATE_CON(10), 1, GFLAGS),
0627 COMPOSITE_NOMUX(PCLK_AUDIO, "pclk_audio", "clk_audio_src", 0,
0628 RK3308_CLKSEL_CON(45), 8, 5, DFLAGS,
0629 RK3308_CLKGATE_CON(10), 2, GFLAGS),
0630
0631 COMPOSITE(0, "clk_pdm_src", mux_vpll0_vpll1_xin24m_p, 0,
0632 RK3308_CLKSEL_CON(46), 8, 2, MFLAGS, 0, 7, DFLAGS,
0633 RK3308_CLKGATE_CON(10), 3, GFLAGS),
0634 COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
0635 RK3308_CLKSEL_CON(47), 0,
0636 RK3308_CLKGATE_CON(10), 4, GFLAGS,
0637 &rk3308_pdm_fracmux),
0638 GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", 0,
0639 RK3308_CLKGATE_CON(10), 5, GFLAGS),
0640
0641 COMPOSITE(SCLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
0642 RK3308_CLKSEL_CON(52), 8, 2, MFLAGS, 0, 7, DFLAGS,
0643 RK3308_CLKGATE_CON(10), 12, GFLAGS),
0644 COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
0645 RK3308_CLKSEL_CON(53), 0,
0646 RK3308_CLKGATE_CON(10), 13, GFLAGS,
0647 &rk3308_i2s0_8ch_tx_fracmux),
0648 COMPOSITE_NODIV(SCLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", mux_i2s0_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
0649 RK3308_CLKSEL_CON(52), 12, 1, MFLAGS,
0650 RK3308_CLKGATE_CON(10), 14, GFLAGS),
0651 COMPOSITE_NODIV(SCLK_I2S0_8CH_TX_OUT, "clk_i2s0_8ch_tx_out", mux_i2s0_8ch_tx_out_p, CLK_SET_RATE_PARENT,
0652 RK3308_CLKSEL_CON(52), 15, 1, MFLAGS,
0653 RK3308_CLKGATE_CON(10), 15, GFLAGS),
0654
0655 COMPOSITE(SCLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
0656 RK3308_CLKSEL_CON(54), 8, 2, MFLAGS, 0, 7, DFLAGS,
0657 RK3308_CLKGATE_CON(11), 0, GFLAGS),
0658 COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
0659 RK3308_CLKSEL_CON(55), 0,
0660 RK3308_CLKGATE_CON(11), 1, GFLAGS,
0661 &rk3308_i2s0_8ch_rx_fracmux),
0662 COMPOSITE_NODIV(SCLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", mux_i2s0_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
0663 RK3308_CLKSEL_CON(54), 12, 1, MFLAGS,
0664 RK3308_CLKGATE_CON(11), 2, GFLAGS),
0665 GATE(SCLK_I2S0_8CH_RX_OUT, "clk_i2s0_8ch_rx_out", "clk_i2s0_8ch_rx", 0,
0666 RK3308_CLKGATE_CON(11), 3, GFLAGS),
0667
0668 COMPOSITE(SCLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
0669 RK3308_CLKSEL_CON(56), 8, 2, MFLAGS, 0, 7, DFLAGS,
0670 RK3308_CLKGATE_CON(11), 4, GFLAGS),
0671 COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
0672 RK3308_CLKSEL_CON(57), 0,
0673 RK3308_CLKGATE_CON(11), 5, GFLAGS,
0674 &rk3308_i2s1_8ch_tx_fracmux),
0675 COMPOSITE_NODIV(SCLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", mux_i2s1_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
0676 RK3308_CLKSEL_CON(56), 12, 1, MFLAGS,
0677 RK3308_CLKGATE_CON(11), 6, GFLAGS),
0678 COMPOSITE_NODIV(SCLK_I2S1_8CH_TX_OUT, "clk_i2s1_8ch_tx_out", mux_i2s1_8ch_tx_out_p, CLK_SET_RATE_PARENT,
0679 RK3308_CLKSEL_CON(56), 15, 1, MFLAGS,
0680 RK3308_CLKGATE_CON(11), 7, GFLAGS),
0681
0682 COMPOSITE(SCLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
0683 RK3308_CLKSEL_CON(58), 8, 2, MFLAGS, 0, 7, DFLAGS,
0684 RK3308_CLKGATE_CON(11), 8, GFLAGS),
0685 COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
0686 RK3308_CLKSEL_CON(59), 0,
0687 RK3308_CLKGATE_CON(11), 9, GFLAGS,
0688 &rk3308_i2s1_8ch_rx_fracmux),
0689 COMPOSITE_NODIV(SCLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", mux_i2s1_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
0690 RK3308_CLKSEL_CON(58), 12, 1, MFLAGS,
0691 RK3308_CLKGATE_CON(11), 10, GFLAGS),
0692 GATE(SCLK_I2S1_8CH_RX_OUT, "clk_i2s1_8ch_rx_out", "clk_i2s1_8ch_rx", 0,
0693 RK3308_CLKGATE_CON(11), 11, GFLAGS),
0694
0695 COMPOSITE(SCLK_I2S2_8CH_TX_SRC, "clk_i2s2_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
0696 RK3308_CLKSEL_CON(60), 8, 2, MFLAGS, 0, 7, DFLAGS,
0697 RK3308_CLKGATE_CON(11), 12, GFLAGS),
0698 COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_tx_frac", "clk_i2s2_8ch_tx_src", CLK_SET_RATE_PARENT,
0699 RK3308_CLKSEL_CON(61), 0,
0700 RK3308_CLKGATE_CON(11), 13, GFLAGS,
0701 &rk3308_i2s2_8ch_tx_fracmux),
0702 COMPOSITE_NODIV(SCLK_I2S2_8CH_TX, "clk_i2s2_8ch_tx", mux_i2s2_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
0703 RK3308_CLKSEL_CON(60), 12, 1, MFLAGS,
0704 RK3308_CLKGATE_CON(11), 14, GFLAGS),
0705 COMPOSITE_NODIV(SCLK_I2S2_8CH_TX_OUT, "clk_i2s2_8ch_tx_out", mux_i2s2_8ch_tx_out_p, CLK_SET_RATE_PARENT,
0706 RK3308_CLKSEL_CON(60), 15, 1, MFLAGS,
0707 RK3308_CLKGATE_CON(11), 15, GFLAGS),
0708
0709 COMPOSITE(SCLK_I2S2_8CH_RX_SRC, "clk_i2s2_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
0710 RK3308_CLKSEL_CON(62), 8, 2, MFLAGS, 0, 7, DFLAGS,
0711 RK3308_CLKGATE_CON(12), 0, GFLAGS),
0712 COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_rx_frac", "clk_i2s2_8ch_rx_src", CLK_SET_RATE_PARENT,
0713 RK3308_CLKSEL_CON(63), 0,
0714 RK3308_CLKGATE_CON(12), 1, GFLAGS,
0715 &rk3308_i2s2_8ch_rx_fracmux),
0716 COMPOSITE_NODIV(SCLK_I2S2_8CH_RX, "clk_i2s2_8ch_rx", mux_i2s2_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
0717 RK3308_CLKSEL_CON(62), 12, 1, MFLAGS,
0718 RK3308_CLKGATE_CON(12), 2, GFLAGS),
0719 GATE(SCLK_I2S2_8CH_RX_OUT, "clk_i2s2_8ch_rx_out", "clk_i2s2_8ch_rx", 0,
0720 RK3308_CLKGATE_CON(12), 3, GFLAGS),
0721
0722 COMPOSITE(SCLK_I2S3_8CH_TX_SRC, "clk_i2s3_8ch_tx_src", mux_vpll0_vpll1_xin24m_p, 0,
0723 RK3308_CLKSEL_CON(64), 8, 2, MFLAGS, 0, 7, DFLAGS,
0724 RK3308_CLKGATE_CON(12), 4, GFLAGS),
0725 COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_tx_frac", "clk_i2s3_8ch_tx_src", CLK_SET_RATE_PARENT,
0726 RK3308_CLKSEL_CON(65), 0,
0727 RK3308_CLKGATE_CON(12), 5, GFLAGS,
0728 &rk3308_i2s3_8ch_tx_fracmux),
0729 COMPOSITE_NODIV(SCLK_I2S3_8CH_TX, "clk_i2s3_8ch_tx", mux_i2s3_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
0730 RK3308_CLKSEL_CON(64), 12, 1, MFLAGS,
0731 RK3308_CLKGATE_CON(12), 6, GFLAGS),
0732 COMPOSITE_NODIV(SCLK_I2S3_8CH_TX_OUT, "clk_i2s3_8ch_tx_out", mux_i2s3_8ch_tx_out_p, CLK_SET_RATE_PARENT,
0733 RK3308_CLKSEL_CON(64), 15, 1, MFLAGS,
0734 RK3308_CLKGATE_CON(12), 7, GFLAGS),
0735
0736 COMPOSITE(SCLK_I2S3_8CH_RX_SRC, "clk_i2s3_8ch_rx_src", mux_vpll0_vpll1_xin24m_p, 0,
0737 RK3308_CLKSEL_CON(66), 8, 2, MFLAGS, 0, 7, DFLAGS,
0738 RK3308_CLKGATE_CON(12), 8, GFLAGS),
0739 COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_rx_frac", "clk_i2s3_8ch_rx_src", CLK_SET_RATE_PARENT,
0740 RK3308_CLKSEL_CON(67), 0,
0741 RK3308_CLKGATE_CON(12), 9, GFLAGS,
0742 &rk3308_i2s3_8ch_rx_fracmux),
0743 COMPOSITE_NODIV(SCLK_I2S3_8CH_RX, "clk_i2s3_8ch_rx", mux_i2s3_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
0744 RK3308_CLKSEL_CON(66), 12, 1, MFLAGS,
0745 RK3308_CLKGATE_CON(12), 10, GFLAGS),
0746 GATE(SCLK_I2S3_8CH_RX_OUT, "clk_i2s3_8ch_rx_out", "clk_i2s3_8ch_rx", 0,
0747 RK3308_CLKGATE_CON(12), 11, GFLAGS),
0748
0749 COMPOSITE(SCLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", mux_vpll0_vpll1_xin24m_p, 0,
0750 RK3308_CLKSEL_CON(68), 8, 2, MFLAGS, 0, 7, DFLAGS,
0751 RK3308_CLKGATE_CON(12), 12, GFLAGS),
0752 COMPOSITE_FRACMUX(0, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT,
0753 RK3308_CLKSEL_CON(69), 0,
0754 RK3308_CLKGATE_CON(12), 13, GFLAGS,
0755 &rk3308_i2s0_2ch_fracmux),
0756 GATE(SCLK_I2S0_2CH, "clk_i2s0_2ch", "clk_i2s0_2ch_mux", 0,
0757 RK3308_CLKGATE_CON(12), 14, GFLAGS),
0758 COMPOSITE_NODIV(SCLK_I2S0_2CH_OUT, "clk_i2s0_2ch_out", mux_i2s0_2ch_out_p, CLK_SET_RATE_PARENT,
0759 RK3308_CLKSEL_CON(68), 15, 1, MFLAGS,
0760 RK3308_CLKGATE_CON(12), 15, GFLAGS),
0761
0762 COMPOSITE(SCLK_I2S1_2CH_SRC, "clk_i2s1_2ch_src", mux_vpll0_vpll1_xin24m_p, 0,
0763 RK3308_CLKSEL_CON(70), 8, 2, MFLAGS, 0, 7, DFLAGS,
0764 RK3308_CLKGATE_CON(13), 0, GFLAGS),
0765 COMPOSITE_FRACMUX(0, "clk_i2s1_2ch_frac", "clk_i2s1_2ch_src", CLK_SET_RATE_PARENT,
0766 RK3308_CLKSEL_CON(71), 0,
0767 RK3308_CLKGATE_CON(13), 1, GFLAGS,
0768 &rk3308_i2s1_2ch_fracmux),
0769 GATE(SCLK_I2S1_2CH, "clk_i2s1_2ch", "clk_i2s1_2ch_mux", 0,
0770 RK3308_CLKGATE_CON(13), 2, GFLAGS),
0771 COMPOSITE_NODIV(SCLK_I2S1_2CH_OUT, "clk_i2s1_2ch_out", mux_i2s1_2ch_out_p, CLK_SET_RATE_PARENT,
0772 RK3308_CLKSEL_CON(70), 15, 1, MFLAGS,
0773 RK3308_CLKGATE_CON(13), 3, GFLAGS),
0774
0775 COMPOSITE(SCLK_SPDIF_TX_DIV, "clk_spdif_tx_div", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
0776 RK3308_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
0777 RK3308_CLKGATE_CON(10), 6, GFLAGS),
0778 COMPOSITE(SCLK_SPDIF_TX_DIV50, "clk_spdif_tx_div50", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
0779 RK3308_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
0780 RK3308_CLKGATE_CON(10), 6, GFLAGS),
0781 MUX(0, "clk_spdif_tx_src", mux_spdif_tx_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0782 RK3308_CLKSEL_CON(48), 12, 1, MFLAGS),
0783 COMPOSITE_FRACMUX(0, "clk_spdif_tx_frac", "clk_spdif_tx_src", CLK_SET_RATE_PARENT,
0784 RK3308_CLKSEL_CON(49), 0,
0785 RK3308_CLKGATE_CON(10), 7, GFLAGS,
0786 &rk3308_spdif_tx_fracmux),
0787 GATE(SCLK_SPDIF_TX, "clk_spdif_tx", "clk_spdif_tx_mux", 0,
0788 RK3308_CLKGATE_CON(10), 8, GFLAGS),
0789
0790 COMPOSITE(SCLK_SPDIF_RX_DIV, "clk_spdif_rx_div", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
0791 RK3308_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
0792 RK3308_CLKGATE_CON(10), 9, GFLAGS),
0793 COMPOSITE(SCLK_SPDIF_RX_DIV50, "clk_spdif_rx_div50", mux_vpll0_vpll1_xin24m_p, CLK_IGNORE_UNUSED,
0794 RK3308_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
0795 RK3308_CLKGATE_CON(10), 9, GFLAGS),
0796 MUX(0, "clk_spdif_rx_src", mux_spdif_rx_src_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0797 RK3308_CLKSEL_CON(50), 14, 1, MFLAGS),
0798 COMPOSITE_FRACMUX(0, "clk_spdif_rx_frac", "clk_spdif_rx_src", CLK_SET_RATE_PARENT,
0799 RK3308_CLKSEL_CON(51), 0,
0800 RK3308_CLKGATE_CON(10), 10, GFLAGS,
0801 &rk3308_spdif_rx_fracmux),
0802 GATE(SCLK_SPDIF_RX, "clk_spdif_rx", "clk_spdif_rx_mux", 0,
0803 RK3308_CLKGATE_CON(10), 11, GFLAGS),
0804
0805
0806
0807
0808
0809 GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 5, GFLAGS),
0810 GATE(0, "pclk_core_dbg_niu", "aclk_core", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 6, GFLAGS),
0811 GATE(0, "pclk_core_dbg_daplite", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 7, GFLAGS),
0812 GATE(0, "aclk_core_perf", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 8, GFLAGS),
0813 GATE(0, "pclk_core_grf", "pclk_core_dbg", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(0), 9, GFLAGS),
0814
0815 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 2, GFLAGS),
0816 GATE(0, "aclk_peribus_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 3, GFLAGS),
0817 GATE(ACLK_MAC, "aclk_mac", "aclk_peri", 0, RK3308_CLKGATE_CON(9), 4, GFLAGS),
0818
0819 GATE(0, "hclk_peri_niu", "hclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 5, GFLAGS),
0820 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 6, GFLAGS),
0821 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 7, GFLAGS),
0822 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 8, GFLAGS),
0823 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 9, GFLAGS),
0824 GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 10, GFLAGS),
0825 GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 11, GFLAGS),
0826 GATE(HCLK_HOST, "hclk_host", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 12, GFLAGS),
0827 GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 13, GFLAGS),
0828
0829 GATE(0, "pclk_peri_niu", "pclk_peri", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(9), 14, GFLAGS),
0830 GATE(PCLK_MAC, "pclk_mac", "pclk_peri", 0, RK3308_CLKGATE_CON(9), 15, GFLAGS),
0831
0832 GATE(0, "hclk_audio_niu", "hclk_audio", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(14), 0, GFLAGS),
0833 GATE(HCLK_PDM, "hclk_pdm", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 1, GFLAGS),
0834 GATE(HCLK_SPDIFTX, "hclk_spdiftx", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 2, GFLAGS),
0835 GATE(HCLK_SPDIFRX, "hclk_spdifrx", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 3, GFLAGS),
0836 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 4, GFLAGS),
0837 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 5, GFLAGS),
0838 GATE(HCLK_I2S2_8CH, "hclk_i2s2_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 6, GFLAGS),
0839 GATE(HCLK_I2S3_8CH, "hclk_i2s3_8ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 7, GFLAGS),
0840 GATE(HCLK_I2S0_2CH, "hclk_i2s0_2ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 8, GFLAGS),
0841 GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 9, GFLAGS),
0842 GATE(HCLK_VAD, "hclk_vad", "hclk_audio", 0, RK3308_CLKGATE_CON(14), 10, GFLAGS),
0843
0844 GATE(0, "pclk_audio_niu", "pclk_audio", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(14), 11, GFLAGS),
0845 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_audio", 0, RK3308_CLKGATE_CON(14), 12, GFLAGS),
0846
0847 GATE(0, "aclk_bus_niu", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 0, GFLAGS),
0848 GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 1, GFLAGS),
0849 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 2, GFLAGS),
0850 GATE(ACLK_VOP, "aclk_vop", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 3, GFLAGS),
0851 GATE(0, "aclk_gic", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 4, GFLAGS),
0852
0853 SGRF_GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus"),
0854
0855 SGRF_GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus"),
0856
0857 SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),
0858
0859 GATE(0, "hclk_bus_niu", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 5, GFLAGS),
0860 GATE(0, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 6, GFLAGS),
0861 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 0, RK3308_CLKGATE_CON(5), 7, GFLAGS),
0862 GATE(HCLK_VOP, "hclk_vop", "hclk_bus", 0, RK3308_CLKGATE_CON(5), 8, GFLAGS),
0863
0864 GATE(0, "pclk_bus_niu", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 9, GFLAGS),
0865 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 10, GFLAGS),
0866 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 11, GFLAGS),
0867 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 12, GFLAGS),
0868 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 13, GFLAGS),
0869 GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 14, GFLAGS),
0870 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 15, GFLAGS),
0871 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 0, GFLAGS),
0872 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 1, GFLAGS),
0873 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 2, GFLAGS),
0874 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 3, GFLAGS),
0875 GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 4, GFLAGS),
0876 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 5, GFLAGS),
0877 GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 6, GFLAGS),
0878 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 7, GFLAGS),
0879 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 8, GFLAGS),
0880 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 9, GFLAGS),
0881 GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 10, GFLAGS),
0882 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 12, GFLAGS),
0883 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 13, GFLAGS),
0884 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 14, GFLAGS),
0885 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 15, GFLAGS),
0886 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 0, RK3308_CLKGATE_CON(7), 0, GFLAGS),
0887 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 1, GFLAGS),
0888 GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 2, GFLAGS),
0889 GATE(PCLK_USBSD_DET, "pclk_usbsd_det", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 3, GFLAGS),
0890 GATE(PCLK_DDR_UPCTL, "pclk_ddr_upctl", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 4, GFLAGS),
0891 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 5, GFLAGS),
0892 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 6, GFLAGS),
0893 GATE(PCLK_DDR_STDBY, "pclk_ddr_stdby", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 7, GFLAGS),
0894 GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 8, GFLAGS),
0895 GATE(PCLK_CRU, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 9, GFLAGS),
0896 GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_bus", 0, RK3308_CLKGATE_CON(7), 10, GFLAGS),
0897 GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 11, GFLAGS),
0898 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 12, GFLAGS),
0899 GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 13, GFLAGS),
0900 GATE(PCLK_CAN, "pclk_can", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 14, GFLAGS),
0901 GATE(PCLK_OWIRE, "pclk_owire", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 15, GFLAGS),
0902 };
0903
0904 static const char *const rk3308_critical_clocks[] __initconst = {
0905 "aclk_bus",
0906 "hclk_bus",
0907 "pclk_bus",
0908 "aclk_peri",
0909 "hclk_peri",
0910 "pclk_peri",
0911 "hclk_audio",
0912 "pclk_audio",
0913 "sclk_ddrc",
0914 "clk_ddrphy4x",
0915 };
0916
0917 static void __init rk3308_clk_init(struct device_node *np)
0918 {
0919 struct rockchip_clk_provider *ctx;
0920 void __iomem *reg_base;
0921
0922 reg_base = of_iomap(np, 0);
0923 if (!reg_base) {
0924 pr_err("%s: could not map cru region\n", __func__);
0925 return;
0926 }
0927
0928 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
0929 if (IS_ERR(ctx)) {
0930 pr_err("%s: rockchip clk init failed\n", __func__);
0931 iounmap(reg_base);
0932 return;
0933 }
0934
0935 rockchip_clk_register_plls(ctx, rk3308_pll_clks,
0936 ARRAY_SIZE(rk3308_pll_clks),
0937 RK3308_GRF_SOC_STATUS0);
0938 rockchip_clk_register_branches(ctx, rk3308_clk_branches,
0939 ARRAY_SIZE(rk3308_clk_branches));
0940 rockchip_clk_protect_critical(rk3308_critical_clocks,
0941 ARRAY_SIZE(rk3308_critical_clocks));
0942
0943 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
0944 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
0945 &rk3308_cpuclk_data, rk3308_cpuclk_rates,
0946 ARRAY_SIZE(rk3308_cpuclk_rates));
0947
0948 rockchip_register_softrst(np, 10, reg_base + RK3308_SOFTRST_CON(0),
0949 ROCKCHIP_SOFTRST_HIWORD_MASK);
0950
0951 rockchip_register_restart_notifier(ctx, RK3308_GLB_SRST_FST, NULL);
0952
0953 rockchip_clk_of_add_provider(np, ctx);
0954 }
0955
0956 CLK_OF_DECLARE(rk3308_cru, "rockchip,rk3308-cru", rk3308_clk_init);
