clk/rockchip/clk-rk3228.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
0004  * Author: Xing Zheng <zhengxing@rock-chips.com>
0005  *         Jeffy Chen <jeffy.chen@rock-chips.com>
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/io.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/syscore_ops.h>
0013 #include <dt-bindings/clock/rk3228-cru.h>
0014 #include "clk.h"
0015
0016 #define RK3228_GRF_SOC_STATUS0  0x480
0017
0018 enum rk3228_plls {
0019     apll, dpll, cpll, gpll,
0020 };
0021
0022 static struct rockchip_pll_rate_table rk3228_pll_rates[] = {
0023     /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
0024     RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
0025     RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
0026     RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
0027     RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
0028     RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
0029     RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
0030     RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
0031     RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
0032     RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
0033     RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
0034     RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
0035     RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
0036     RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
0037     RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
0038     RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
0039     RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
0040     RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
0041     RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
0042     RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
0043     RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
0044     RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
0045     RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
0046     RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
0047     RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
0048     RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
0049     RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
0050     RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
0051     RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
0052     RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
0053     RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
0054     RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
0055     RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
0056     RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
0057     RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
0058     RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
0059     RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
0060     RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
0061     RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
0062     RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
0063     RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
0064     RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
0065     RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
0066     { /* sentinel */ },
0067 };
0068
0069 #define RK3228_DIV_CPU_MASK     0x1f
0070 #define RK3228_DIV_CPU_SHIFT        8
0071
0072 #define RK3228_DIV_PERI_MASK        0xf
0073 #define RK3228_DIV_PERI_SHIFT       0
0074 #define RK3228_DIV_ACLK_MASK        0x7
0075 #define RK3228_DIV_ACLK_SHIFT       4
0076 #define RK3228_DIV_HCLK_MASK        0x3
0077 #define RK3228_DIV_HCLK_SHIFT       8
0078 #define RK3228_DIV_PCLK_MASK        0x7
0079 #define RK3228_DIV_PCLK_SHIFT       12
0080
0081 #define RK3228_CLKSEL1(_core_aclk_div, _core_peri_div)              \
0082     {                                   \
0083         .reg = RK2928_CLKSEL_CON(1),                    \
0084         .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK,  \
0085                      RK3228_DIV_PERI_SHIFT) |           \
0086                HIWORD_UPDATE(_core_aclk_div, RK3228_DIV_ACLK_MASK,  \
0087                      RK3228_DIV_ACLK_SHIFT),            \
0088 }
0089
0090 #define RK3228_CPUCLK_RATE(_prate, _core_aclk_div, _core_peri_div)      \
0091     {                                   \
0092         .prate = _prate,                        \
0093         .divs = {                           \
0094             RK3228_CLKSEL1(_core_aclk_div, _core_peri_div),     \
0095         },                              \
0096     }
0097
0098 static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = {
0099     RK3228_CPUCLK_RATE(1800000000, 1, 7),
0100     RK3228_CPUCLK_RATE(1704000000, 1, 7),
0101     RK3228_CPUCLK_RATE(1608000000, 1, 7),
0102     RK3228_CPUCLK_RATE(1512000000, 1, 7),
0103     RK3228_CPUCLK_RATE(1488000000, 1, 5),
0104     RK3228_CPUCLK_RATE(1464000000, 1, 5),
0105     RK3228_CPUCLK_RATE(1416000000, 1, 5),
0106     RK3228_CPUCLK_RATE(1392000000, 1, 5),
0107     RK3228_CPUCLK_RATE(1296000000, 1, 5),
0108     RK3228_CPUCLK_RATE(1200000000, 1, 5),
0109     RK3228_CPUCLK_RATE(1104000000, 1, 5),
0110     RK3228_CPUCLK_RATE(1008000000, 1, 5),
0111     RK3228_CPUCLK_RATE(912000000, 1, 5),
0112     RK3228_CPUCLK_RATE(816000000, 1, 3),
0113     RK3228_CPUCLK_RATE(696000000, 1, 3),
0114     RK3228_CPUCLK_RATE(600000000, 1, 3),
0115     RK3228_CPUCLK_RATE(408000000, 1, 1),
0116     RK3228_CPUCLK_RATE(312000000, 1, 1),
0117     RK3228_CPUCLK_RATE(216000000,  1, 1),
0118     RK3228_CPUCLK_RATE(96000000, 1, 1),
0119 };
0120
0121 static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
0122     .core_reg[0] = RK2928_CLKSEL_CON(0),
0123     .div_core_shift[0] = 0,
0124     .div_core_mask[0] = 0x1f,
0125     .num_cores = 1,
0126     .mux_core_alt = 1,
0127     .mux_core_main = 0,
0128     .mux_core_shift = 6,
0129     .mux_core_mask = 0x1,
0130 };
0131
0132 PNAME(mux_pll_p)        = { "clk_24m", "xin24m" };
0133
0134 PNAME(mux_ddrphy_p)     = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
0135 PNAME(mux_armclk_p)     = { "apll_core", "gpll_core", "dpll_core" };
0136 PNAME(mux_usb480m_phy_p)    = { "usb480m_phy0", "usb480m_phy1" };
0137 PNAME(mux_usb480m_p)        = { "usb480m_phy", "xin24m" };
0138 PNAME(mux_hdmiphy_p)        = { "hdmiphy_phy", "xin24m" };
0139 PNAME(mux_aclk_cpu_src_p)   = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
0140
0141 PNAME(mux_pll_src_4plls_p)  = { "cpll", "gpll", "hdmiphy", "usb480m" };
0142 PNAME(mux_pll_src_3plls_p)  = { "cpll", "gpll", "hdmiphy" };
0143 PNAME(mux_pll_src_2plls_p)  = { "cpll", "gpll" };
0144 PNAME(mux_sclk_hdmi_cec_p)  = { "cpll", "gpll", "xin24m" };
0145 PNAME(mux_aclk_peri_src_p)  = { "cpll_peri", "gpll_peri", "hdmiphy_peri" };
0146 PNAME(mux_mmc_src_p)        = { "cpll", "gpll", "xin24m", "usb480m" };
0147 PNAME(mux_pll_src_cpll_gpll_usb480m_p)  = { "cpll", "gpll", "usb480m" };
0148
0149 PNAME(mux_sclk_rga_p)       = { "gpll", "cpll", "sclk_rga_src" };
0150
0151 PNAME(mux_sclk_vop_src_p)   = { "gpll_vop", "cpll_vop" };
0152 PNAME(mux_dclk_vop_p)       = { "hdmiphy", "sclk_vop_pre" };
0153
0154 PNAME(mux_i2s0_p)       = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
0155 PNAME(mux_i2s1_pre_p)       = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" };
0156 PNAME(mux_i2s_out_p)        = { "i2s1_pre", "xin12m" };
0157 PNAME(mux_i2s2_p)       = { "i2s2_src", "i2s2_frac", "xin12m" };
0158 PNAME(mux_sclk_spdif_p)     = { "sclk_spdif_src", "spdif_frac", "xin12m" };
0159
0160 PNAME(mux_uart0_p)      = { "uart0_src", "uart0_frac", "xin24m" };
0161 PNAME(mux_uart1_p)      = { "uart1_src", "uart1_frac", "xin24m" };
0162 PNAME(mux_uart2_p)      = { "uart2_src", "uart2_frac", "xin24m" };
0163
0164 PNAME(mux_sclk_mac_extclk_p)    = { "ext_gmac", "phy_50m_out" };
0165 PNAME(mux_sclk_gmac_pre_p)  = { "sclk_gmac_src", "sclk_mac_extclk" };
0166 PNAME(mux_sclk_macphy_p)    = { "sclk_gmac_src", "ext_gmac" };
0167
0168 static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
0169     [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
0170              RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates),
0171     [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3),
0172              RK2928_MODE_CON, 4, 6, 0, NULL),
0173     [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
0174              RK2928_MODE_CON, 8, 8, 0, NULL),
0175     [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
0176              RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates),
0177 };
0178
0179 #define MFLAGS CLK_MUX_HIWORD_MASK
0180 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
0181 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
0182
0183 static struct rockchip_clk_branch rk3228_i2s0_fracmux __initdata =
0184     MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
0185             RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
0186
0187 static struct rockchip_clk_branch rk3228_i2s1_fracmux __initdata =
0188     MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
0189             RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
0190
0191 static struct rockchip_clk_branch rk3228_i2s2_fracmux __initdata =
0192     MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
0193             RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
0194
0195 static struct rockchip_clk_branch rk3228_spdif_fracmux __initdata =
0196     MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
0197             RK2928_CLKSEL_CON(6), 8, 2, MFLAGS);
0198
0199 static struct rockchip_clk_branch rk3228_uart0_fracmux __initdata =
0200     MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
0201             RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
0202
0203 static struct rockchip_clk_branch rk3228_uart1_fracmux __initdata =
0204     MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
0205             RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
0206
0207 static struct rockchip_clk_branch rk3228_uart2_fracmux __initdata =
0208     MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
0209             RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
0210
0211 static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
0212     /*
0213      * Clock-Architecture Diagram 1
0214      */
0215
0216     DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
0217             RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
0218
0219     /* PD_DDR */
0220     GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
0221             RK2928_CLKGATE_CON(0), 2, GFLAGS),
0222     GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
0223             RK2928_CLKGATE_CON(0), 2, GFLAGS),
0224     GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
0225             RK2928_CLKGATE_CON(0), 2, GFLAGS),
0226     COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
0227             RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
0228             RK2928_CLKGATE_CON(7), 1, GFLAGS),
0229     GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
0230             RK2928_CLKGATE_CON(8), 5, GFLAGS),
0231     FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
0232             RK2928_CLKGATE_CON(7), 0, GFLAGS),
0233
0234     /* PD_CORE */
0235     GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
0236             RK2928_CLKGATE_CON(0), 6, GFLAGS),
0237     GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
0238             RK2928_CLKGATE_CON(0), 6, GFLAGS),
0239     GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
0240             RK2928_CLKGATE_CON(0), 6, GFLAGS),
0241     COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
0242             RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
0243             RK2928_CLKGATE_CON(4), 1, GFLAGS),
0244     COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED,
0245             RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
0246             RK2928_CLKGATE_CON(4), 0, GFLAGS),
0247
0248     /* PD_MISC */
0249     MUX(SCLK_HDMI_PHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
0250             RK2928_MISC_CON, 13, 1, MFLAGS),
0251     MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
0252             RK2928_MISC_CON, 14, 1, MFLAGS),
0253     MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
0254             RK2928_MISC_CON, 15, 1, MFLAGS),
0255
0256     /* PD_BUS */
0257     GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED,
0258             RK2928_CLKGATE_CON(0), 1, GFLAGS),
0259     GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
0260             RK2928_CLKGATE_CON(0), 1, GFLAGS),
0261     GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
0262             RK2928_CLKGATE_CON(0), 1, GFLAGS),
0263     COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
0264             RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
0265     GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
0266             RK2928_CLKGATE_CON(6), 0, GFLAGS),
0267     COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0,
0268             RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
0269             RK2928_CLKGATE_CON(6), 1, GFLAGS),
0270     COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0,
0271             RK2928_CLKSEL_CON(1), 12, 3, DFLAGS,
0272             RK2928_CLKGATE_CON(6), 2, GFLAGS),
0273     GATE(PCLK_CPU, "pclk_cpu", "pclk_bus_src", 0,
0274             RK2928_CLKGATE_CON(6), 3, GFLAGS),
0275     GATE(0, "pclk_phy_pre", "pclk_bus_src", 0,
0276             RK2928_CLKGATE_CON(6), 4, GFLAGS),
0277     GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0,
0278             RK2928_CLKGATE_CON(6), 13, GFLAGS),
0279
0280     /* PD_VIDEO */
0281     COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
0282             RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS,
0283             RK2928_CLKGATE_CON(3), 11, GFLAGS),
0284     FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
0285             RK2928_CLKGATE_CON(4), 4, GFLAGS),
0286
0287     COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
0288             RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
0289             RK2928_CLKGATE_CON(3), 2, GFLAGS),
0290     FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
0291             RK2928_CLKGATE_CON(4), 5, GFLAGS),
0292
0293     COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
0294             RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
0295             RK2928_CLKGATE_CON(3), 3, GFLAGS),
0296
0297     COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_pll_src_4plls_p, 0,
0298             RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, 8, 5, DFLAGS,
0299             RK2928_CLKGATE_CON(3), 4, GFLAGS),
0300
0301     /* PD_VIO */
0302     COMPOSITE(ACLK_IEP_PRE, "aclk_iep_pre", mux_pll_src_4plls_p, 0,
0303             RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, 0, 5, DFLAGS,
0304             RK2928_CLKGATE_CON(3), 0, GFLAGS),
0305     DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_iep_pre", 0,
0306             RK2928_CLKSEL_CON(2), 0, 5, DFLAGS),
0307
0308     COMPOSITE(ACLK_HDCP_PRE, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,
0309             RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS,
0310             RK2928_CLKGATE_CON(1), 4, GFLAGS),
0311
0312     MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0,
0313             RK2928_CLKSEL_CON(33), 13, 2, MFLAGS),
0314     COMPOSITE_NOMUX(ACLK_RGA_PRE, "aclk_rga_pre", "sclk_rga_src", 0,
0315             RK2928_CLKSEL_CON(33), 8, 5, DFLAGS,
0316             RK2928_CLKGATE_CON(1), 2, GFLAGS),
0317     COMPOSITE(SCLK_RGA, "sclk_rga", mux_sclk_rga_p, 0,
0318             RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS,
0319             RK2928_CLKGATE_CON(3), 6, GFLAGS),
0320
0321     COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_pll_src_4plls_p, 0,
0322             RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, 0, 5, DFLAGS,
0323             RK2928_CLKGATE_CON(1), 1, GFLAGS),
0324
0325     COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_3plls_p, 0,
0326             RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS,
0327             RK2928_CLKGATE_CON(3), 5, GFLAGS),
0328
0329     GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
0330             RK2928_CLKGATE_CON(3), 7, GFLAGS),
0331
0332     COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
0333             RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, 0, 14, DFLAGS,
0334             RK2928_CLKGATE_CON(3), 8, GFLAGS),
0335
0336     /* PD_PERI */
0337     GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
0338             RK2928_CLKGATE_CON(2), 0, GFLAGS),
0339     GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
0340             RK2928_CLKGATE_CON(2), 0, GFLAGS),
0341     GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
0342             RK2928_CLKGATE_CON(2), 0, GFLAGS),
0343     COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
0344             RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS),
0345     COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
0346             RK2928_CLKSEL_CON(10), 12, 3, DFLAGS,
0347             RK2928_CLKGATE_CON(5), 2, GFLAGS),
0348     COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
0349             RK2928_CLKSEL_CON(10), 8, 2, DFLAGS,
0350             RK2928_CLKGATE_CON(5), 1, GFLAGS),
0351     GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
0352             RK2928_CLKGATE_CON(5), 0, GFLAGS),
0353
0354     GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
0355             RK2928_CLKGATE_CON(6), 5, GFLAGS),
0356     GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
0357             RK2928_CLKGATE_CON(6), 6, GFLAGS),
0358     GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
0359             RK2928_CLKGATE_CON(6), 7, GFLAGS),
0360     GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
0361             RK2928_CLKGATE_CON(6), 8, GFLAGS),
0362     GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
0363             RK2928_CLKGATE_CON(6), 9, GFLAGS),
0364     GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
0365             RK2928_CLKGATE_CON(6), 10, GFLAGS),
0366
0367     COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0,
0368             RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, 0, 5, DFLAGS,
0369             RK2928_CLKGATE_CON(2), 7, GFLAGS),
0370
0371     COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_2plls_p, 0,
0372             RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS,
0373             RK2928_CLKGATE_CON(2), 6, GFLAGS),
0374
0375     GATE(SCLK_HSADC, "sclk_hsadc", "ext_hsadc", 0,
0376             RK2928_CLKGATE_CON(10), 12, GFLAGS),
0377
0378     COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
0379             RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
0380             RK2928_CLKGATE_CON(2), 15, GFLAGS),
0381
0382     COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
0383             RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
0384             RK2928_CLKGATE_CON(2), 11, GFLAGS),
0385
0386     COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0,
0387             RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
0388             RK2928_CLKGATE_CON(2), 13, GFLAGS),
0389     DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
0390             RK2928_CLKSEL_CON(12), 0, 8, DFLAGS),
0391
0392     COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
0393             RK2928_CLKSEL_CON(11), 12, 2, MFLAGS,
0394             RK2928_CLKGATE_CON(2), 14, GFLAGS),
0395     DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
0396             RK2928_CLKSEL_CON(12), 8, 8, DFLAGS),
0397
0398     /*
0399      * Clock-Architecture Diagram 2
0400      */
0401
0402     GATE(0, "gpll_vop", "gpll", 0,
0403             RK2928_CLKGATE_CON(3), 1, GFLAGS),
0404     GATE(0, "cpll_vop", "cpll", 0,
0405             RK2928_CLKGATE_CON(3), 1, GFLAGS),
0406     MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
0407             RK2928_CLKSEL_CON(27), 0, 1, MFLAGS),
0408     DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0,
0409             RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
0410     DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
0411             RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
0412     MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
0413             RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
0414
0415     FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
0416
0417     COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
0418             RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS,
0419             RK2928_CLKGATE_CON(0), 3, GFLAGS),
0420     COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
0421             RK2928_CLKSEL_CON(8), 0,
0422             RK2928_CLKGATE_CON(0), 4, GFLAGS,
0423             &rk3228_i2s0_fracmux),
0424     GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
0425             RK2928_CLKGATE_CON(0), 5, GFLAGS),
0426
0427     COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
0428             RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS,
0429             RK2928_CLKGATE_CON(0), 10, GFLAGS),
0430     COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
0431             RK2928_CLKSEL_CON(7), 0,
0432             RK2928_CLKGATE_CON(0), 11, GFLAGS,
0433             &rk3228_i2s1_fracmux),
0434     GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
0435             RK2928_CLKGATE_CON(0), 14, GFLAGS),
0436     COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
0437             RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
0438             RK2928_CLKGATE_CON(0), 13, GFLAGS),
0439
0440     COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
0441             RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS,
0442             RK2928_CLKGATE_CON(0), 7, GFLAGS),
0443     COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
0444             RK2928_CLKSEL_CON(30), 0,
0445             RK2928_CLKGATE_CON(0), 8, GFLAGS,
0446             &rk3228_i2s2_fracmux),
0447     GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
0448             RK2928_CLKGATE_CON(0), 9, GFLAGS),
0449
0450     COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0,
0451             RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
0452             RK2928_CLKGATE_CON(2), 10, GFLAGS),
0453     COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
0454             RK2928_CLKSEL_CON(20), 0,
0455             RK2928_CLKGATE_CON(2), 12, GFLAGS,
0456             &rk3228_spdif_fracmux),
0457
0458     GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
0459             RK2928_CLKGATE_CON(1), 3, GFLAGS),
0460
0461     GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0,
0462             RK2928_CLKGATE_CON(1), 5, GFLAGS),
0463     GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 0,
0464             RK2928_CLKGATE_CON(1), 6, GFLAGS),
0465
0466     COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
0467             RK2928_CLKSEL_CON(24), 6, 10, DFLAGS,
0468             RK2928_CLKGATE_CON(2), 8, GFLAGS),
0469
0470     COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_4plls_p, 0,
0471             RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS,
0472             RK2928_CLKGATE_CON(3), 13, GFLAGS),
0473
0474     COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0,
0475             RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
0476             RK2928_CLKGATE_CON(2), 9, GFLAGS),
0477
0478     /* PD_UART */
0479     COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
0480             RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
0481             RK2928_CLKGATE_CON(1), 8, GFLAGS),
0482     COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
0483             RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
0484             RK2928_CLKGATE_CON(1), 10, GFLAGS),
0485     COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p,
0486             0, RK2928_CLKSEL_CON(15), 12, 2,
0487             MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS),
0488     COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
0489             RK2928_CLKSEL_CON(17), 0,
0490             RK2928_CLKGATE_CON(1), 9, GFLAGS,
0491             &rk3228_uart0_fracmux),
0492     COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
0493             RK2928_CLKSEL_CON(18), 0,
0494             RK2928_CLKGATE_CON(1), 11, GFLAGS,
0495             &rk3228_uart1_fracmux),
0496     COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
0497             RK2928_CLKSEL_CON(19), 0,
0498             RK2928_CLKGATE_CON(1), 13, GFLAGS,
0499             &rk3228_uart2_fracmux),
0500
0501     COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
0502             RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS,
0503             RK2928_CLKGATE_CON(1), 0, GFLAGS),
0504
0505     COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_2plls_p, 0,
0506             RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS,
0507             RK2928_CLKGATE_CON(1), 7, GFLAGS),
0508     MUX(SCLK_MAC_EXTCLK, "sclk_mac_extclk", mux_sclk_mac_extclk_p, 0,
0509             RK2928_CLKSEL_CON(29), 10, 1, MFLAGS),
0510     MUX(SCLK_MAC, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0,
0511             RK2928_CLKSEL_CON(5), 5, 1, MFLAGS),
0512     GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac_pre", 0,
0513             RK2928_CLKGATE_CON(5), 4, GFLAGS),
0514     GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac_pre", 0,
0515             RK2928_CLKGATE_CON(5), 3, GFLAGS),
0516     GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac_pre", 0,
0517             RK2928_CLKGATE_CON(5), 5, GFLAGS),
0518     GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac_pre", 0,
0519             RK2928_CLKGATE_CON(5), 6, GFLAGS),
0520     COMPOSITE(SCLK_MAC_PHY, "sclk_macphy", mux_sclk_macphy_p, 0,
0521             RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS,
0522             RK2928_CLKGATE_CON(5), 7, GFLAGS),
0523     COMPOSITE(SCLK_MAC_OUT, "sclk_gmac_out", mux_pll_src_2plls_p, 0,
0524             RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS,
0525             RK2928_CLKGATE_CON(2), 2, GFLAGS),
0526
0527     /*
0528      * Clock-Architecture Diagram 3
0529      */
0530
0531     /* PD_VOP */
0532     GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
0533     GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),
0534     GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
0535     GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
0536
0537     GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
0538     GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
0539
0540     GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
0541     GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),
0542
0543     GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
0544     GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
0545     GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
0546     GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
0547     GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
0548     GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),
0549     GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
0550     GATE(HCLK_HDCP_MMU, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
0551     GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
0552     GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
0553     GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
0554
0555     /* PD_PERI */
0556     GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS),
0557     GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS),
0558
0559     GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS),
0560     GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS),
0561     GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
0562     GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
0563     GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
0564     GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),
0565     GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
0566     GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),
0567     GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
0568     GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
0569     GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),
0570     GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
0571     GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
0572
0573     GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
0574     GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),
0575
0576     /* PD_GPU */
0577     GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
0578     GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
0579
0580     /* PD_BUS */
0581     GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
0582     GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
0583     GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
0584     GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
0585
0586     GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
0587     GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
0588     GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
0589     GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
0590     GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
0591     GATE(HCLK_TSP, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
0592     GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
0593     GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
0594
0595     GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
0596     GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
0597     GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
0598
0599     GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
0600     GATE(PCLK_EFUSE_256, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
0601     GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
0602     GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
0603     GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
0604     GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
0605     GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS),
0606     GATE(0, "pclk_stimer", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
0607     GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
0608     GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
0609     GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
0610     GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS),
0611     GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 10, GFLAGS),
0612     GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 11, GFLAGS),
0613     GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),
0614     GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS),
0615     GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS),
0616     GATE(PCLK_TSADC, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS),
0617     GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS),
0618     GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
0619     GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
0620     GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
0621
0622     GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
0623     GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
0624     GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
0625     GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
0626     GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
0627
0628     GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
0629     GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),
0630     GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
0631     GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),
0632     GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
0633     GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),
0634     GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
0635     GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),
0636
0637     /* PD_MMC */
0638     MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
0639     MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),
0640
0641     MMC(SCLK_SDIO_DRV,     "sdio_drv",     "sclk_sdio",  RK3228_SDIO_CON0,  1),
0642     MMC(SCLK_SDIO_SAMPLE,  "sdio_sample",  "sclk_sdio",  RK3228_SDIO_CON1,  0),
0643
0644     MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3228_EMMC_CON0,  1),
0645     MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3228_EMMC_CON1,  0),
0646 };
0647
0648 static const char *const rk3228_critical_clocks[] __initconst = {
0649     "aclk_cpu",
0650     "pclk_cpu",
0651     "hclk_cpu",
0652     "aclk_peri",
0653     "hclk_peri",
0654     "pclk_peri",
0655     "aclk_rga_noc",
0656     "aclk_iep_noc",
0657     "aclk_vop_noc",
0658     "aclk_hdcp_noc",
0659     "hclk_vio_ahb_arbi",
0660     "hclk_vio_noc",
0661     "hclk_vop_noc",
0662     "hclk_host0_arb",
0663     "hclk_host1_arb",
0664     "hclk_host2_arb",
0665     "hclk_otg_pmu",
0666     "aclk_gpu_noc",
0667     "sclk_initmem_mbist",
0668     "aclk_initmem",
0669     "hclk_rom",
0670     "pclk_ddrupctl",
0671     "pclk_ddrmon",
0672     "pclk_msch_noc",
0673     "pclk_stimer",
0674     "pclk_ddrphy",
0675     "pclk_acodecphy",
0676     "pclk_phy_noc",
0677     "aclk_vpu_noc",
0678     "aclk_rkvdec_noc",
0679     "hclk_vpu_noc",
0680     "hclk_rkvdec_noc",
0681 };
0682
0683 static void __init rk3228_clk_init(struct device_node *np)
0684 {
0685     struct rockchip_clk_provider *ctx;
0686     void __iomem *reg_base;
0687
0688     reg_base = of_iomap(np, 0);
0689     if (!reg_base) {
0690         pr_err("%s: could not map cru region\n", __func__);
0691         return;
0692     }
0693
0694     ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
0695     if (IS_ERR(ctx)) {
0696         pr_err("%s: rockchip clk init failed\n", __func__);
0697         iounmap(reg_base);
0698         return;
0699     }
0700
0701     rockchip_clk_register_plls(ctx, rk3228_pll_clks,
0702                    ARRAY_SIZE(rk3228_pll_clks),
0703                    RK3228_GRF_SOC_STATUS0);
0704     rockchip_clk_register_branches(ctx, rk3228_clk_branches,
0705                   ARRAY_SIZE(rk3228_clk_branches));
0706     rockchip_clk_protect_critical(rk3228_critical_clocks,
0707                       ARRAY_SIZE(rk3228_critical_clocks));
0708
0709     rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
0710             mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
0711             &rk3228_cpuclk_data, rk3228_cpuclk_rates,
0712             ARRAY_SIZE(rk3228_cpuclk_rates));
0713
0714     rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
0715                   ROCKCHIP_SOFTRST_HIWORD_MASK);
0716
0717     rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, NULL);
0718
0719     rockchip_clk_of_add_provider(np, ctx);
0720 }
0721 CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);