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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2014 MundoReader S.L.
0004  * Author: Heiko Stuebner <heiko@sntech.de>
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/clk-provider.h>
0009 #include <linux/io.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <dt-bindings/clock/rk3188-cru-common.h>
0013 #include "clk.h"
0014 
0015 #define RK3066_GRF_SOC_STATUS   0x15c
0016 #define RK3188_GRF_SOC_STATUS   0xac
0017 
0018 enum rk3188_plls {
0019     apll, cpll, dpll, gpll,
0020 };
0021 
0022 static struct rockchip_pll_rate_table rk3188_pll_rates[] = {
0023     RK3066_PLL_RATE(2208000000, 1, 92, 1),
0024     RK3066_PLL_RATE(2184000000, 1, 91, 1),
0025     RK3066_PLL_RATE(2160000000, 1, 90, 1),
0026     RK3066_PLL_RATE(2136000000, 1, 89, 1),
0027     RK3066_PLL_RATE(2112000000, 1, 88, 1),
0028     RK3066_PLL_RATE(2088000000, 1, 87, 1),
0029     RK3066_PLL_RATE(2064000000, 1, 86, 1),
0030     RK3066_PLL_RATE(2040000000, 1, 85, 1),
0031     RK3066_PLL_RATE(2016000000, 1, 84, 1),
0032     RK3066_PLL_RATE(1992000000, 1, 83, 1),
0033     RK3066_PLL_RATE(1968000000, 1, 82, 1),
0034     RK3066_PLL_RATE(1944000000, 1, 81, 1),
0035     RK3066_PLL_RATE(1920000000, 1, 80, 1),
0036     RK3066_PLL_RATE(1896000000, 1, 79, 1),
0037     RK3066_PLL_RATE(1872000000, 1, 78, 1),
0038     RK3066_PLL_RATE(1848000000, 1, 77, 1),
0039     RK3066_PLL_RATE(1824000000, 1, 76, 1),
0040     RK3066_PLL_RATE(1800000000, 1, 75, 1),
0041     RK3066_PLL_RATE(1776000000, 1, 74, 1),
0042     RK3066_PLL_RATE(1752000000, 1, 73, 1),
0043     RK3066_PLL_RATE(1728000000, 1, 72, 1),
0044     RK3066_PLL_RATE(1704000000, 1, 71, 1),
0045     RK3066_PLL_RATE(1680000000, 1, 70, 1),
0046     RK3066_PLL_RATE(1656000000, 1, 69, 1),
0047     RK3066_PLL_RATE(1632000000, 1, 68, 1),
0048     RK3066_PLL_RATE(1608000000, 1, 67, 1),
0049     RK3066_PLL_RATE(1560000000, 1, 65, 1),
0050     RK3066_PLL_RATE(1512000000, 1, 63, 1),
0051     RK3066_PLL_RATE(1488000000, 1, 62, 1),
0052     RK3066_PLL_RATE(1464000000, 1, 61, 1),
0053     RK3066_PLL_RATE(1440000000, 1, 60, 1),
0054     RK3066_PLL_RATE(1416000000, 1, 59, 1),
0055     RK3066_PLL_RATE(1392000000, 1, 58, 1),
0056     RK3066_PLL_RATE(1368000000, 1, 57, 1),
0057     RK3066_PLL_RATE(1344000000, 1, 56, 1),
0058     RK3066_PLL_RATE(1320000000, 1, 55, 1),
0059     RK3066_PLL_RATE(1296000000, 1, 54, 1),
0060     RK3066_PLL_RATE(1272000000, 1, 53, 1),
0061     RK3066_PLL_RATE(1248000000, 1, 52, 1),
0062     RK3066_PLL_RATE(1224000000, 1, 51, 1),
0063     RK3066_PLL_RATE(1200000000, 1, 50, 1),
0064     RK3066_PLL_RATE(1188000000, 2, 99, 1),
0065     RK3066_PLL_RATE(1176000000, 1, 49, 1),
0066     RK3066_PLL_RATE(1128000000, 1, 47, 1),
0067     RK3066_PLL_RATE(1104000000, 1, 46, 1),
0068     RK3066_PLL_RATE(1008000000, 1, 84, 2),
0069     RK3066_PLL_RATE( 912000000, 1, 76, 2),
0070     RK3066_PLL_RATE( 891000000, 8, 594, 2),
0071     RK3066_PLL_RATE( 888000000, 1, 74, 2),
0072     RK3066_PLL_RATE( 816000000, 1, 68, 2),
0073     RK3066_PLL_RATE( 798000000, 2, 133, 2),
0074     RK3066_PLL_RATE( 792000000, 1, 66, 2),
0075     RK3066_PLL_RATE( 768000000, 1, 64, 2),
0076     RK3066_PLL_RATE( 742500000, 8, 495, 2),
0077     RK3066_PLL_RATE( 696000000, 1, 58, 2),
0078     RK3066_PLL_RATE( 600000000, 1, 50, 2),
0079     RK3066_PLL_RATE( 594000000, 2, 198, 4),
0080     RK3066_PLL_RATE( 552000000, 1, 46, 2),
0081     RK3066_PLL_RATE( 504000000, 1, 84, 4),
0082     RK3066_PLL_RATE( 456000000, 1, 76, 4),
0083     RK3066_PLL_RATE( 408000000, 1, 68, 4),
0084     RK3066_PLL_RATE( 400000000, 3, 100, 2),
0085     RK3066_PLL_RATE( 384000000, 2, 128, 4),
0086     RK3066_PLL_RATE( 360000000, 1, 60, 4),
0087     RK3066_PLL_RATE( 312000000, 1, 52, 4),
0088     RK3066_PLL_RATE( 300000000, 1, 50, 4),
0089     RK3066_PLL_RATE( 297000000, 2, 198, 8),
0090     RK3066_PLL_RATE( 252000000, 1, 84, 8),
0091     RK3066_PLL_RATE( 216000000, 1, 72, 8),
0092     RK3066_PLL_RATE( 148500000, 2, 99, 8),
0093     RK3066_PLL_RATE( 126000000, 1, 84, 16),
0094     RK3066_PLL_RATE(  48000000, 1, 64, 32),
0095     { /* sentinel */ },
0096 };
0097 
0098 #define RK3066_DIV_CORE_PERIPH_MASK 0x3
0099 #define RK3066_DIV_CORE_PERIPH_SHIFT    6
0100 #define RK3066_DIV_ACLK_CORE_MASK   0x7
0101 #define RK3066_DIV_ACLK_CORE_SHIFT  0
0102 #define RK3066_DIV_ACLK_HCLK_MASK   0x3
0103 #define RK3066_DIV_ACLK_HCLK_SHIFT  8
0104 #define RK3066_DIV_ACLK_PCLK_MASK   0x3
0105 #define RK3066_DIV_ACLK_PCLK_SHIFT  12
0106 #define RK3066_DIV_AHB2APB_MASK     0x3
0107 #define RK3066_DIV_AHB2APB_SHIFT    14
0108 
0109 #define RK3066_CLKSEL0(_core_peri)                  \
0110     {                               \
0111         .reg = RK2928_CLKSEL_CON(0),                \
0112         .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
0113                 RK3066_DIV_CORE_PERIPH_SHIFT)       \
0114     }
0115 #define RK3066_CLKSEL1(_aclk_core, _aclk_hclk, _aclk_pclk, _ahb2apb)    \
0116     {                               \
0117         .reg = RK2928_CLKSEL_CON(1),                \
0118         .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
0119                 RK3066_DIV_ACLK_CORE_SHIFT) |       \
0120                HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
0121                 RK3066_DIV_ACLK_HCLK_SHIFT) |       \
0122                HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
0123                 RK3066_DIV_ACLK_PCLK_SHIFT) |       \
0124                HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \
0125                 RK3066_DIV_AHB2APB_SHIFT),      \
0126     }
0127 
0128 #define RK3066_CPUCLK_RATE(_prate, _core_peri, _acore, _ahclk, _apclk, _h2p) \
0129     {                               \
0130         .prate = _prate,                    \
0131         .divs = {                       \
0132             RK3066_CLKSEL0(_core_peri),         \
0133             RK3066_CLKSEL1(_acore, _ahclk, _apclk, _h2p),   \
0134         },                          \
0135     }
0136 
0137 static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = {
0138     RK3066_CPUCLK_RATE(1416000000, 2, 3, 1, 2, 1),
0139     RK3066_CPUCLK_RATE(1200000000, 2, 3, 1, 2, 1),
0140     RK3066_CPUCLK_RATE(1008000000, 2, 2, 1, 2, 1),
0141     RK3066_CPUCLK_RATE( 816000000, 2, 2, 1, 2, 1),
0142     RK3066_CPUCLK_RATE( 600000000, 1, 2, 1, 2, 1),
0143     RK3066_CPUCLK_RATE( 504000000, 1, 1, 1, 2, 1),
0144     RK3066_CPUCLK_RATE( 312000000, 0, 1, 1, 1, 0),
0145 };
0146 
0147 static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = {
0148     .core_reg[0] = RK2928_CLKSEL_CON(0),
0149     .div_core_shift[0] = 0,
0150     .div_core_mask[0] = 0x1f,
0151     .num_cores = 1,
0152     .mux_core_alt = 1,
0153     .mux_core_main = 0,
0154     .mux_core_shift = 8,
0155     .mux_core_mask = 0x1,
0156 };
0157 
0158 #define RK3188_DIV_ACLK_CORE_MASK   0x7
0159 #define RK3188_DIV_ACLK_CORE_SHIFT  3
0160 
0161 #define RK3188_CLKSEL1(_aclk_core)      \
0162     {                   \
0163         .reg = RK2928_CLKSEL_CON(1),    \
0164         .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
0165                  RK3188_DIV_ACLK_CORE_SHIFT) \
0166     }
0167 #define RK3188_CPUCLK_RATE(_prate, _core_peri, _aclk_core)  \
0168     {                           \
0169         .prate = _prate,                \
0170         .divs = {                   \
0171             RK3066_CLKSEL0(_core_peri),     \
0172             RK3188_CLKSEL1(_aclk_core),     \
0173         },                      \
0174     }
0175 
0176 static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = {
0177     RK3188_CPUCLK_RATE(1608000000, 2, 3),
0178     RK3188_CPUCLK_RATE(1416000000, 2, 3),
0179     RK3188_CPUCLK_RATE(1200000000, 2, 3),
0180     RK3188_CPUCLK_RATE(1008000000, 2, 3),
0181     RK3188_CPUCLK_RATE( 816000000, 2, 3),
0182     RK3188_CPUCLK_RATE( 600000000, 1, 3),
0183     RK3188_CPUCLK_RATE( 504000000, 1, 3),
0184     RK3188_CPUCLK_RATE( 312000000, 0, 1),
0185 };
0186 
0187 static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = {
0188     .core_reg[0] = RK2928_CLKSEL_CON(0),
0189     .div_core_shift[0] = 9,
0190     .div_core_mask[0] = 0x1f,
0191     .num_cores = 1,
0192     .mux_core_alt = 1,
0193     .mux_core_main = 0,
0194     .mux_core_shift = 8,
0195     .mux_core_mask = 0x1,
0196 };
0197 
0198 PNAME(mux_pll_p)        = { "xin24m", "xin32k" };
0199 PNAME(mux_armclk_p)     = { "apll", "gpll_armclk" };
0200 PNAME(mux_ddrphy_p)     = { "dpll", "gpll_ddr" };
0201 PNAME(mux_pll_src_gpll_cpll_p)  = { "gpll", "cpll" };
0202 PNAME(mux_pll_src_cpll_gpll_p)  = { "cpll", "gpll" };
0203 PNAME(mux_aclk_cpu_p)       = { "apll", "gpll" };
0204 PNAME(mux_sclk_cif0_p)      = { "cif0_pre", "xin24m" };
0205 PNAME(mux_sclk_i2s0_p)      = { "i2s0_pre", "i2s0_frac", "xin12m" };
0206 PNAME(mux_sclk_spdif_p)     = { "spdif_pre", "spdif_frac", "xin12m" };
0207 PNAME(mux_sclk_uart0_p)     = { "uart0_pre", "uart0_frac", "xin24m" };
0208 PNAME(mux_sclk_uart1_p)     = { "uart1_pre", "uart1_frac", "xin24m" };
0209 PNAME(mux_sclk_uart2_p)     = { "uart2_pre", "uart2_frac", "xin24m" };
0210 PNAME(mux_sclk_uart3_p)     = { "uart3_pre", "uart3_frac", "xin24m" };
0211 PNAME(mux_sclk_hsadc_p)     = { "hsadc_src", "hsadc_frac", "ext_hsadc" };
0212 PNAME(mux_mac_p)        = { "gpll", "dpll" };
0213 PNAME(mux_sclk_macref_p)    = { "mac_src", "ext_rmii" };
0214 
0215 static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = {
0216     [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
0217              RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
0218     [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
0219              RK2928_MODE_CON, 4, 4, 0, NULL),
0220     [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
0221              RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
0222     [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
0223              RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
0224 };
0225 
0226 static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
0227     [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
0228              RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
0229     [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
0230              RK2928_MODE_CON, 4, 5, 0, NULL),
0231     [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
0232              RK2928_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
0233     [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
0234              RK2928_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
0235 };
0236 
0237 #define MFLAGS CLK_MUX_HIWORD_MASK
0238 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
0239 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
0240 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
0241 
0242 /* 2 ^ (val + 1) */
0243 static struct clk_div_table div_core_peri_t[] = {
0244     { .val = 0, .div = 2 },
0245     { .val = 1, .div = 4 },
0246     { .val = 2, .div = 8 },
0247     { .val = 3, .div = 16 },
0248     { /* sentinel */ },
0249 };
0250 
0251 static struct rockchip_clk_branch common_hsadc_out_fracmux __initdata =
0252     MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0,
0253             RK2928_CLKSEL_CON(22), 4, 2, MFLAGS);
0254 
0255 static struct rockchip_clk_branch common_spdif_fracmux __initdata =
0256     MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
0257             RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
0258 
0259 static struct rockchip_clk_branch common_uart0_fracmux __initdata =
0260     MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, CLK_SET_RATE_PARENT,
0261             RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
0262 
0263 static struct rockchip_clk_branch common_uart1_fracmux __initdata =
0264     MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, CLK_SET_RATE_PARENT,
0265             RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
0266 
0267 static struct rockchip_clk_branch common_uart2_fracmux __initdata =
0268     MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, CLK_SET_RATE_PARENT,
0269             RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
0270 
0271 static struct rockchip_clk_branch common_uart3_fracmux __initdata =
0272     MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, CLK_SET_RATE_PARENT,
0273             RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
0274 
0275 static struct rockchip_clk_branch common_clk_branches[] __initdata = {
0276     /*
0277      * Clock-Architecture Diagram 2
0278      */
0279 
0280     GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
0281 
0282     /* these two are set by the cpuclk and should not be changed */
0283     COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri", "armclk", 0,
0284             RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
0285             div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS),
0286 
0287     COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
0288             RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
0289             RK2928_CLKGATE_CON(3), 9, GFLAGS),
0290     GATE(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0,
0291             RK2928_CLKGATE_CON(3), 10, GFLAGS),
0292     COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
0293             RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
0294             RK2928_CLKGATE_CON(3), 11, GFLAGS),
0295     GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0,
0296             RK2928_CLKGATE_CON(3), 12, GFLAGS),
0297 
0298     GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
0299             RK2928_CLKGATE_CON(1), 7, GFLAGS),
0300     COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
0301             RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
0302             RK2928_CLKGATE_CON(0), 2, GFLAGS),
0303 
0304     GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
0305             RK2928_CLKGATE_CON(0), 3, GFLAGS),
0306 
0307     GATE(0, "atclk_cpu", "pclk_cpu_pre", 0,
0308             RK2928_CLKGATE_CON(0), 6, GFLAGS),
0309     GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_pre", 0,
0310             RK2928_CLKGATE_CON(0), 5, GFLAGS),
0311     GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
0312             RK2928_CLKGATE_CON(0), 4, GFLAGS),
0313 
0314     COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
0315             RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
0316             RK2928_CLKGATE_CON(3), 0, GFLAGS),
0317     COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
0318             RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS,
0319             RK2928_CLKGATE_CON(1), 4, GFLAGS),
0320 
0321     GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0,
0322             RK2928_CLKGATE_CON(2), 1, GFLAGS),
0323     COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", 0,
0324             RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
0325             RK2928_CLKGATE_CON(2), 2, GFLAGS),
0326     COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", 0,
0327             RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
0328             RK2928_CLKGATE_CON(2), 3, GFLAGS),
0329 
0330     MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
0331             RK2928_CLKSEL_CON(29), 0, 1, MFLAGS),
0332     COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0,
0333             RK2928_CLKSEL_CON(29), 1, 5, DFLAGS,
0334             RK2928_CLKGATE_CON(3), 7, GFLAGS),
0335     MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0,
0336             RK2928_CLKSEL_CON(29), 7, 1, MFLAGS),
0337 
0338     GATE(0, "pclkin_cif0", "ext_cif0", 0,
0339             RK2928_CLKGATE_CON(3), 3, GFLAGS),
0340     INVERTER(0, "pclk_cif0", "pclkin_cif0",
0341             RK2928_CLKSEL_CON(30), 8, IFLAGS),
0342 
0343     FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
0344 
0345     /*
0346      * the 480m are generated inside the usb block from these clocks,
0347      * but they are also a source for the hsicphy clock.
0348      */
0349     GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
0350             RK2928_CLKGATE_CON(1), 5, GFLAGS),
0351     GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
0352             RK2928_CLKGATE_CON(1), 6, GFLAGS),
0353 
0354     COMPOSITE(0, "mac_src", mux_mac_p, 0,
0355             RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS,
0356             RK2928_CLKGATE_CON(2), 5, GFLAGS),
0357     MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
0358             RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
0359     GATE(0, "sclk_mac_lbtest", "sclk_macref", 0,
0360             RK2928_CLKGATE_CON(2), 12, GFLAGS),
0361 
0362     COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
0363             RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
0364             RK2928_CLKGATE_CON(2), 6, GFLAGS),
0365     COMPOSITE_FRACMUX(0, "hsadc_frac", "hsadc_src", 0,
0366             RK2928_CLKSEL_CON(23), 0,
0367             RK2928_CLKGATE_CON(2), 7, GFLAGS,
0368             &common_hsadc_out_fracmux),
0369     INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
0370             RK2928_CLKSEL_CON(22), 7, IFLAGS),
0371 
0372     COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
0373             RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
0374             RK2928_CLKGATE_CON(2), 8, GFLAGS),
0375 
0376     COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
0377             RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
0378             RK2928_CLKGATE_CON(0), 13, GFLAGS),
0379     COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT,
0380             RK2928_CLKSEL_CON(9), 0,
0381             RK2928_CLKGATE_CON(0), 14, GFLAGS,
0382             &common_spdif_fracmux),
0383 
0384     /*
0385      * Clock-Architecture Diagram 4
0386      */
0387 
0388     GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0,
0389             RK2928_CLKGATE_CON(2), 4, GFLAGS),
0390 
0391     COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
0392             RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,
0393             RK2928_CLKGATE_CON(2), 9, GFLAGS),
0394     COMPOSITE_NOMUX(SCLK_SPI1, "sclk_spi1", "pclk_peri", 0,
0395             RK2928_CLKSEL_CON(25), 8, 7, DFLAGS,
0396             RK2928_CLKGATE_CON(2), 10, GFLAGS),
0397 
0398     COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc", "hclk_peri", 0,
0399             RK2928_CLKSEL_CON(11), 0, 6, DFLAGS,
0400             RK2928_CLKGATE_CON(2), 11, GFLAGS),
0401     COMPOSITE_NOMUX(SCLK_SDIO, "sclk_sdio", "hclk_peri", 0,
0402             RK2928_CLKSEL_CON(12), 0, 6, DFLAGS,
0403             RK2928_CLKGATE_CON(2), 13, GFLAGS),
0404     COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0,
0405             RK2928_CLKSEL_CON(12), 8, 6, DFLAGS,
0406             RK2928_CLKGATE_CON(2), 14, GFLAGS),
0407 
0408     MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0,
0409             RK2928_CLKSEL_CON(12), 15, 1, MFLAGS),
0410     COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0,
0411             RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
0412             RK2928_CLKGATE_CON(1), 8, GFLAGS),
0413     COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", CLK_SET_RATE_PARENT,
0414             RK2928_CLKSEL_CON(17), 0,
0415             RK2928_CLKGATE_CON(1), 9, GFLAGS,
0416             &common_uart0_fracmux),
0417     COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
0418             RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
0419             RK2928_CLKGATE_CON(1), 10, GFLAGS),
0420     COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", CLK_SET_RATE_PARENT,
0421             RK2928_CLKSEL_CON(18), 0,
0422             RK2928_CLKGATE_CON(1), 11, GFLAGS,
0423             &common_uart1_fracmux),
0424     COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
0425             RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
0426             RK2928_CLKGATE_CON(1), 12, GFLAGS),
0427     COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", CLK_SET_RATE_PARENT,
0428             RK2928_CLKSEL_CON(19), 0,
0429             RK2928_CLKGATE_CON(1), 13, GFLAGS,
0430             &common_uart2_fracmux),
0431     COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
0432             RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
0433             RK2928_CLKGATE_CON(1), 14, GFLAGS),
0434     COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", CLK_SET_RATE_PARENT,
0435             RK2928_CLKSEL_CON(20), 0,
0436             RK2928_CLKGATE_CON(1), 15, GFLAGS,
0437             &common_uart3_fracmux),
0438 
0439     GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS),
0440 
0441     GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS),
0442     GATE(SCLK_TIMER1, "timer1", "xin24m", 0, RK2928_CLKGATE_CON(1), 1, GFLAGS),
0443 
0444     /* clk_core_pre gates */
0445     GATE(0, "core_dbg", "armclk", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
0446 
0447     /* aclk_cpu gates */
0448     GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
0449     GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
0450     GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
0451 
0452     /* hclk_cpu gates */
0453     GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
0454     GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
0455     GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS),
0456     /* hclk_ahb2apb is part of a clk branch */
0457     GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
0458     GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
0459     GATE(HCLK_LCDC1, "hclk_lcdc1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
0460     GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
0461     GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS),
0462     GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
0463 
0464     /* hclk_peri gates */
0465     GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
0466     GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),
0467     GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS),
0468     GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
0469     GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
0470     GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS),
0471     GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
0472     GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS),
0473     GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS),
0474     GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
0475     GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
0476     GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 12, GFLAGS),
0477 
0478     /* aclk_lcdc0_pre gates */
0479     GATE(0, "aclk_vio0", "aclk_lcdc0_pre", 0, RK2928_CLKGATE_CON(6), 13, GFLAGS),
0480     GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS),
0481     GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS),
0482     GATE(ACLK_IPP, "aclk_ipp", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 8, GFLAGS),
0483 
0484     /* aclk_lcdc1_pre gates */
0485     GATE(0, "aclk_vio1", "aclk_lcdc1_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
0486     GATE(ACLK_LCDC1, "aclk_lcdc1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 3, GFLAGS),
0487     GATE(ACLK_RGA, "aclk_rga", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
0488 
0489     /* atclk_cpu gates */
0490     GATE(0, "atclk", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 3, GFLAGS),
0491     GATE(0, "trace", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
0492 
0493     /* pclk_cpu gates */
0494     GATE(PCLK_PWM01, "pclk_pwm01", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
0495     GATE(PCLK_TIMER0, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
0496     GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
0497     GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
0498     GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
0499     GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
0500     GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
0501     GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS),
0502     GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS),
0503     GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
0504     GATE(PCLK_PUBL, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
0505     GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
0506     GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
0507     GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS),
0508 
0509     /* aclk_peri */
0510     GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
0511     GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS),
0512     GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS),
0513     GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
0514     GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
0515 
0516     /* pclk_peri gates */
0517     GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
0518     GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS),
0519     GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
0520     GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
0521     GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 13, GFLAGS),
0522     GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
0523     GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
0524     GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
0525     GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
0526     GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
0527     GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
0528     GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
0529 };
0530 
0531 PNAME(mux_rk3066_lcdc0_p)   = { "dclk_lcdc0_src", "xin27m" };
0532 PNAME(mux_rk3066_lcdc1_p)   = { "dclk_lcdc1_src", "xin27m" };
0533 PNAME(mux_sclk_cif1_p)      = { "cif1_pre", "xin24m" };
0534 PNAME(mux_sclk_i2s1_p)      = { "i2s1_pre", "i2s1_frac", "xin12m" };
0535 PNAME(mux_sclk_i2s2_p)      = { "i2s2_pre", "i2s2_frac", "xin12m" };
0536 
0537 static struct clk_div_table div_aclk_cpu_t[] = {
0538     { .val = 0, .div = 1 },
0539     { .val = 1, .div = 2 },
0540     { .val = 2, .div = 3 },
0541     { .val = 3, .div = 4 },
0542     { .val = 4, .div = 8 },
0543     { /* sentinel */ },
0544 };
0545 
0546 static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata =
0547     MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
0548             RK2928_CLKSEL_CON(2), 8, 2, MFLAGS);
0549 
0550 static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata =
0551     MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, CLK_SET_RATE_PARENT,
0552             RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
0553 
0554 static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata =
0555     MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, CLK_SET_RATE_PARENT,
0556             RK2928_CLKSEL_CON(4), 8, 2, MFLAGS);
0557 
0558 static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
0559     DIVTBL(0, "aclk_cpu_pre", "armclk", 0,
0560             RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t),
0561     DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
0562             RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
0563                                 | CLK_DIVIDER_READ_ONLY),
0564     DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
0565             RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
0566                                | CLK_DIVIDER_READ_ONLY),
0567     COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
0568             RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO
0569                                 | CLK_DIVIDER_READ_ONLY,
0570             RK2928_CLKGATE_CON(4), 9, GFLAGS),
0571 
0572     GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED,
0573             RK2928_CLKGATE_CON(9), 4, GFLAGS),
0574 
0575     COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,
0576             RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
0577             RK2928_CLKGATE_CON(2), 0, GFLAGS),
0578 
0579     COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,
0580             RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
0581             RK2928_CLKGATE_CON(3), 1, GFLAGS),
0582     MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT,
0583             RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),
0584     COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,
0585             RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
0586             RK2928_CLKGATE_CON(3), 2, GFLAGS),
0587     MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT,
0588             RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),
0589 
0590     COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0,
0591             RK2928_CLKSEL_CON(29), 8, 5, DFLAGS,
0592             RK2928_CLKGATE_CON(3), 8, GFLAGS),
0593     MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0,
0594             RK2928_CLKSEL_CON(29), 15, 1, MFLAGS),
0595 
0596     GATE(0, "pclkin_cif1", "ext_cif1", 0,
0597             RK2928_CLKGATE_CON(3), 4, GFLAGS),
0598     INVERTER(0, "pclk_cif1", "pclkin_cif1",
0599             RK2928_CLKSEL_CON(30), 12, IFLAGS),
0600 
0601     COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
0602             RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS,
0603             RK2928_CLKGATE_CON(3), 13, GFLAGS),
0604     GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
0605             RK2928_CLKGATE_CON(5), 15, GFLAGS),
0606 
0607     GATE(SCLK_TIMER2, "timer2", "xin24m", 0,
0608             RK2928_CLKGATE_CON(3), 2, GFLAGS),
0609 
0610     COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
0611             RK2928_CLKSEL_CON(34), 0, 16, DFLAGS,
0612             RK2928_CLKGATE_CON(2), 15, GFLAGS),
0613 
0614     MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
0615             RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
0616     COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
0617             RK2928_CLKSEL_CON(2), 0, 7, DFLAGS,
0618             RK2928_CLKGATE_CON(0), 7, GFLAGS),
0619     COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
0620             RK2928_CLKSEL_CON(6), 0,
0621             RK2928_CLKGATE_CON(0), 8, GFLAGS,
0622             &rk3066a_i2s0_fracmux),
0623     COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
0624             RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
0625             RK2928_CLKGATE_CON(0), 9, GFLAGS),
0626     COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", CLK_SET_RATE_PARENT,
0627             RK2928_CLKSEL_CON(7), 0,
0628             RK2928_CLKGATE_CON(0), 10, GFLAGS,
0629             &rk3066a_i2s1_fracmux),
0630     COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
0631             RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
0632             RK2928_CLKGATE_CON(0), 11, GFLAGS),
0633     COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", CLK_SET_RATE_PARENT,
0634             RK2928_CLKSEL_CON(8), 0,
0635             RK2928_CLKGATE_CON(0), 12, GFLAGS,
0636             &rk3066a_i2s2_fracmux),
0637 
0638     GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
0639     GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
0640     GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
0641     GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
0642     GATE(HCLK_HDMI, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
0643 
0644     GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
0645             RK2928_CLKGATE_CON(5), 14, GFLAGS),
0646 
0647     GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
0648 
0649     GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS),
0650     GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
0651     GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
0652     GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
0653     GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
0654 
0655     GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
0656     GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 13, GFLAGS),
0657 };
0658 
0659 static struct clk_div_table div_rk3188_aclk_core_t[] = {
0660     { .val = 0, .div = 1 },
0661     { .val = 1, .div = 2 },
0662     { .val = 2, .div = 3 },
0663     { .val = 3, .div = 4 },
0664     { .val = 4, .div = 8 },
0665     { /* sentinel */ },
0666 };
0667 
0668 PNAME(mux_hsicphy_p)        = { "sclk_otgphy0_480m", "sclk_otgphy1_480m",
0669                     "gpll", "cpll" };
0670 
0671 static struct rockchip_clk_branch rk3188_i2s0_fracmux __initdata =
0672     MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
0673             RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
0674 
0675 static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
0676     COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
0677             RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
0678             div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
0679 
0680     /* do not source aclk_cpu_pre from the apll, to keep complexity down */
0681     COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT,
0682             RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS),
0683     DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
0684             RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
0685     DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
0686             RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
0687     COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
0688             RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
0689             RK2928_CLKGATE_CON(4), 9, GFLAGS),
0690 
0691     GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED,
0692             RK2928_CLKGATE_CON(9), 4, GFLAGS),
0693 
0694     COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
0695             RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
0696             RK2928_CLKGATE_CON(2), 0, GFLAGS),
0697 
0698     COMPOSITE(DCLK_LCDC0, "dclk_lcdc0", mux_pll_src_cpll_gpll_p, 0,
0699             RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
0700             RK2928_CLKGATE_CON(3), 1, GFLAGS),
0701     COMPOSITE(DCLK_LCDC1, "dclk_lcdc1", mux_pll_src_cpll_gpll_p, 0,
0702             RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
0703             RK2928_CLKGATE_CON(3), 2, GFLAGS),
0704 
0705     COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
0706             RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS,
0707             RK2928_CLKGATE_CON(3), 15, GFLAGS),
0708     GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
0709             RK2928_CLKGATE_CON(9), 7, GFLAGS),
0710 
0711     GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS),
0712     GATE(SCLK_TIMER3, "timer3", "xin24m", 0, RK2928_CLKGATE_CON(1), 2, GFLAGS),
0713     GATE(SCLK_TIMER4, "timer4", "xin24m", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
0714     GATE(SCLK_TIMER5, "timer5", "xin24m", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
0715     GATE(SCLK_TIMER6, "timer6", "xin24m", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
0716 
0717     COMPOSITE_NODIV(0, "sclk_hsicphy_480m", mux_hsicphy_p, 0,
0718             RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
0719             RK2928_CLKGATE_CON(3), 6, GFLAGS),
0720     DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
0721             RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),
0722 
0723     MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
0724             RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
0725     COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
0726             RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
0727             RK2928_CLKGATE_CON(0), 9, GFLAGS),
0728     COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
0729             RK2928_CLKSEL_CON(7), 0,
0730             RK2928_CLKGATE_CON(0), 10, GFLAGS,
0731             &rk3188_i2s0_fracmux),
0732 
0733     GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
0734     GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
0735     GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
0736 
0737     GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
0738             RK2928_CLKGATE_CON(7), 3, GFLAGS),
0739     GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
0740 
0741     GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
0742 
0743     GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
0744     GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
0745 
0746     GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
0747 };
0748 
0749 static const char *const rk3188_critical_clocks[] __initconst = {
0750     "aclk_cpu",
0751     "aclk_peri",
0752     "hclk_peri",
0753     "pclk_cpu",
0754     "pclk_peri",
0755     "hclk_cpubus",
0756     "hclk_vio_bus",
0757     "sclk_mac_lbtest",
0758 };
0759 
0760 static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)
0761 {
0762     struct rockchip_clk_provider *ctx;
0763     void __iomem *reg_base;
0764 
0765     reg_base = of_iomap(np, 0);
0766     if (!reg_base) {
0767         pr_err("%s: could not map cru region\n", __func__);
0768         return ERR_PTR(-ENOMEM);
0769     }
0770 
0771     ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
0772     if (IS_ERR(ctx)) {
0773         pr_err("%s: rockchip clk init failed\n", __func__);
0774         iounmap(reg_base);
0775         return ERR_PTR(-ENOMEM);
0776     }
0777 
0778     rockchip_clk_register_branches(ctx, common_clk_branches,
0779                   ARRAY_SIZE(common_clk_branches));
0780 
0781     rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
0782                   ROCKCHIP_SOFTRST_HIWORD_MASK);
0783 
0784     rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
0785 
0786     return ctx;
0787 }
0788 
0789 static void __init rk3066a_clk_init(struct device_node *np)
0790 {
0791     struct rockchip_clk_provider *ctx;
0792 
0793     ctx = rk3188_common_clk_init(np);
0794     if (IS_ERR(ctx))
0795         return;
0796 
0797     rockchip_clk_register_plls(ctx, rk3066_pll_clks,
0798                    ARRAY_SIZE(rk3066_pll_clks),
0799                    RK3066_GRF_SOC_STATUS);
0800     rockchip_clk_register_branches(ctx, rk3066a_clk_branches,
0801                   ARRAY_SIZE(rk3066a_clk_branches));
0802     rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
0803             mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
0804             &rk3066_cpuclk_data, rk3066_cpuclk_rates,
0805             ARRAY_SIZE(rk3066_cpuclk_rates));
0806     rockchip_clk_protect_critical(rk3188_critical_clocks,
0807                       ARRAY_SIZE(rk3188_critical_clocks));
0808     rockchip_clk_of_add_provider(np, ctx);
0809 }
0810 CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
0811 
0812 static void __init rk3188a_clk_init(struct device_node *np)
0813 {
0814     struct rockchip_clk_provider *ctx;
0815     struct clk *clk1, *clk2;
0816     unsigned long rate;
0817     int ret;
0818 
0819     ctx = rk3188_common_clk_init(np);
0820     if (IS_ERR(ctx))
0821         return;
0822 
0823     rockchip_clk_register_plls(ctx, rk3188_pll_clks,
0824                    ARRAY_SIZE(rk3188_pll_clks),
0825                    RK3188_GRF_SOC_STATUS);
0826     rockchip_clk_register_branches(ctx, rk3188_clk_branches,
0827                   ARRAY_SIZE(rk3188_clk_branches));
0828     rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
0829                   mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
0830                   &rk3188_cpuclk_data, rk3188_cpuclk_rates,
0831                   ARRAY_SIZE(rk3188_cpuclk_rates));
0832 
0833     /* reparent aclk_cpu_pre from apll */
0834     clk1 = __clk_lookup("aclk_cpu_pre");
0835     clk2 = __clk_lookup("gpll");
0836     if (clk1 && clk2) {
0837         rate = clk_get_rate(clk1);
0838 
0839         ret = clk_set_parent(clk1, clk2);
0840         if (ret < 0)
0841             pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n",
0842                 __func__);
0843 
0844         clk_set_rate(clk1, rate);
0845     } else {
0846         pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n",
0847             __func__);
0848     }
0849 
0850     rockchip_clk_protect_critical(rk3188_critical_clocks,
0851                       ARRAY_SIZE(rk3188_critical_clocks));
0852     rockchip_clk_of_add_provider(np, ctx);
0853 }
0854 CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init);
0855 
0856 static void __init rk3188_clk_init(struct device_node *np)
0857 {
0858     int i;
0859 
0860     for (i = 0; i < ARRAY_SIZE(rk3188_pll_clks); i++) {
0861         struct rockchip_pll_clock *pll = &rk3188_pll_clks[i];
0862         struct rockchip_pll_rate_table *rate;
0863 
0864         if (!pll->rate_table)
0865             continue;
0866 
0867         rate = pll->rate_table;
0868         while (rate->rate > 0) {
0869             rate->nb = 1;
0870             rate++;
0871         }
0872     }
0873 
0874     rk3188a_clk_init(np);
0875 }
0876 CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru", rk3188_clk_init);
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