clk/rockchip/clk-rk3128.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
0004  * Author: Elaine <zhangqing@rock-chips.com>
0005  */
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/io.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/syscore_ops.h>
0012 #include <dt-bindings/clock/rk3128-cru.h>
0013 #include "clk.h"
0014
0015 #define RK3128_GRF_SOC_STATUS0  0x14c
0016
0017 enum rk3128_plls {
0018     apll, dpll, cpll, gpll,
0019 };
0020
0021 static struct rockchip_pll_rate_table rk3128_pll_rates[] = {
0022     /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
0023     RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
0024     RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
0025     RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
0026     RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
0027     RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
0028     RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
0029     RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
0030     RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
0031     RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
0032     RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
0033     RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
0034     RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
0035     RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
0036     RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
0037     RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
0038     RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
0039     RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
0040     RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
0041     RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
0042     RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
0043     RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
0044     RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
0045     RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
0046     RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
0047     RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
0048     RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
0049     RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
0050     RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
0051     RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
0052     RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
0053     RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
0054     RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
0055     RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
0056     RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
0057     RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
0058     RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
0059     RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
0060     RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
0061     RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
0062     RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
0063     RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
0064     RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
0065     { /* sentinel */ },
0066 };
0067
0068 #define RK3128_DIV_CPU_MASK     0x1f
0069 #define RK3128_DIV_CPU_SHIFT        8
0070
0071 #define RK3128_DIV_PERI_MASK        0xf
0072 #define RK3128_DIV_PERI_SHIFT       0
0073 #define RK3128_DIV_ACLK_MASK        0x7
0074 #define RK3128_DIV_ACLK_SHIFT       4
0075 #define RK3128_DIV_HCLK_MASK        0x3
0076 #define RK3128_DIV_HCLK_SHIFT       8
0077 #define RK3128_DIV_PCLK_MASK        0x7
0078 #define RK3128_DIV_PCLK_SHIFT       12
0079
0080 #define RK3128_CLKSEL1(_core_aclk_div, _pclk_dbg_div)           \
0081 {                                   \
0082     .reg = RK2928_CLKSEL_CON(1),                    \
0083     .val = HIWORD_UPDATE(_pclk_dbg_div, RK3128_DIV_PERI_MASK,   \
0084                  RK3128_DIV_PERI_SHIFT) |           \
0085            HIWORD_UPDATE(_core_aclk_div, RK3128_DIV_ACLK_MASK,  \
0086                  RK3128_DIV_ACLK_SHIFT),            \
0087 }
0088
0089 #define RK3128_CPUCLK_RATE(_prate, _core_aclk_div, _pclk_dbg_div)   \
0090 {                                   \
0091     .prate = _prate,                        \
0092     .divs = {                           \
0093         RK3128_CLKSEL1(_core_aclk_div, _pclk_dbg_div),      \
0094     },                              \
0095 }
0096
0097 static struct rockchip_cpuclk_rate_table rk3128_cpuclk_rates[] __initdata = {
0098     RK3128_CPUCLK_RATE(1800000000, 1, 7),
0099     RK3128_CPUCLK_RATE(1704000000, 1, 7),
0100     RK3128_CPUCLK_RATE(1608000000, 1, 7),
0101     RK3128_CPUCLK_RATE(1512000000, 1, 7),
0102     RK3128_CPUCLK_RATE(1488000000, 1, 5),
0103     RK3128_CPUCLK_RATE(1416000000, 1, 5),
0104     RK3128_CPUCLK_RATE(1392000000, 1, 5),
0105     RK3128_CPUCLK_RATE(1296000000, 1, 5),
0106     RK3128_CPUCLK_RATE(1200000000, 1, 5),
0107     RK3128_CPUCLK_RATE(1104000000, 1, 5),
0108     RK3128_CPUCLK_RATE(1008000000, 1, 5),
0109     RK3128_CPUCLK_RATE(912000000, 1, 5),
0110     RK3128_CPUCLK_RATE(816000000, 1, 3),
0111     RK3128_CPUCLK_RATE(696000000, 1, 3),
0112     RK3128_CPUCLK_RATE(600000000, 1, 3),
0113     RK3128_CPUCLK_RATE(408000000, 1, 1),
0114     RK3128_CPUCLK_RATE(312000000, 1, 1),
0115     RK3128_CPUCLK_RATE(216000000,  1, 1),
0116     RK3128_CPUCLK_RATE(96000000, 1, 1),
0117 };
0118
0119 static const struct rockchip_cpuclk_reg_data rk3128_cpuclk_data = {
0120     .core_reg[0] = RK2928_CLKSEL_CON(0),
0121     .div_core_shift[0] = 0,
0122     .div_core_mask[0] = 0x1f,
0123     .num_cores = 1,
0124     .mux_core_alt = 1,
0125     .mux_core_main = 0,
0126     .mux_core_shift = 7,
0127     .mux_core_mask = 0x1,
0128 };
0129
0130 PNAME(mux_pll_p)        = { "clk_24m", "xin24m" };
0131
0132 PNAME(mux_ddrphy_p)     = { "dpll_ddr", "gpll_div2_ddr" };
0133 PNAME(mux_armclk_p)     = { "apll_core", "gpll_div2_core" };
0134 PNAME(mux_usb480m_p)        = { "usb480m_phy", "xin24m" };
0135 PNAME(mux_aclk_cpu_src_p)   = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
0136
0137 PNAME(mux_pll_src_5plls_p)  = { "cpll", "gpll", "gpll_div2", "gpll_div3", "usb480m" };
0138 PNAME(mux_pll_src_4plls_p)  = { "cpll", "gpll", "gpll_div2", "usb480m" };
0139 PNAME(mux_pll_src_3plls_p)  = { "cpll", "gpll", "gpll_div2" };
0140
0141 PNAME(mux_aclk_peri_src_p)  = { "gpll_peri", "cpll_peri", "gpll_div2_peri", "gpll_div3_peri" };
0142 PNAME(mux_mmc_src_p)        = { "cpll", "gpll", "gpll_div2", "xin24m" };
0143 PNAME(mux_clk_cif_out_src_p)        = { "clk_cif_src", "xin24m" };
0144 PNAME(mux_sclk_vop_src_p)   = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
0145
0146 PNAME(mux_i2s0_p)       = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
0147 PNAME(mux_i2s1_pre_p)       = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" };
0148 PNAME(mux_i2s_out_p)        = { "i2s1_pre", "xin12m" };
0149 PNAME(mux_sclk_spdif_p)     = { "sclk_spdif_src", "spdif_frac", "xin12m" };
0150
0151 PNAME(mux_uart0_p)      = { "uart0_src", "uart0_frac", "xin24m" };
0152 PNAME(mux_uart1_p)      = { "uart1_src", "uart1_frac", "xin24m" };
0153 PNAME(mux_uart2_p)      = { "uart2_src", "uart2_frac", "xin24m" };
0154
0155 PNAME(mux_sclk_gmac_p)  = { "sclk_gmac_src", "gmac_clkin" };
0156 PNAME(mux_sclk_sfc_src_p)   = { "cpll", "gpll", "gpll_div2", "xin24m" };
0157
0158 static struct rockchip_pll_clock rk3128_pll_clks[] __initdata = {
0159     [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
0160              RK2928_MODE_CON, 0, 1, 0, rk3128_pll_rates),
0161     [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
0162              RK2928_MODE_CON, 4, 0, 0, NULL),
0163     [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
0164              RK2928_MODE_CON, 8, 2, 0, rk3128_pll_rates),
0165     [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
0166              RK2928_MODE_CON, 12, 3, ROCKCHIP_PLL_SYNC_RATE, rk3128_pll_rates),
0167 };
0168
0169 #define MFLAGS CLK_MUX_HIWORD_MASK
0170 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
0171 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
0172
0173 static struct rockchip_clk_branch rk3128_i2s0_fracmux __initdata =
0174     MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
0175             RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
0176
0177 static struct rockchip_clk_branch rk3128_i2s1_fracmux __initdata =
0178     MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
0179             RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
0180
0181 static struct rockchip_clk_branch rk3128_spdif_fracmux __initdata =
0182     MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
0183             RK2928_CLKSEL_CON(6), 8, 2, MFLAGS);
0184
0185 static struct rockchip_clk_branch rk3128_uart0_fracmux __initdata =
0186     MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
0187             RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
0188
0189 static struct rockchip_clk_branch rk3128_uart1_fracmux __initdata =
0190     MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
0191             RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
0192
0193 static struct rockchip_clk_branch rk3128_uart2_fracmux __initdata =
0194     MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
0195             RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
0196
0197 static struct rockchip_clk_branch common_clk_branches[] __initdata = {
0198     /*
0199      * Clock-Architecture Diagram 1
0200      */
0201
0202     FACTOR(PLL_GPLL_DIV2, "gpll_div2", "gpll", 0, 1, 2),
0203     FACTOR(PLL_GPLL_DIV3, "gpll_div3", "gpll", 0, 1, 3),
0204
0205     DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
0206             RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
0207
0208     /* PD_DDR */
0209     GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
0210             RK2928_CLKGATE_CON(0), 2, GFLAGS),
0211     GATE(0, "gpll_div2_ddr", "gpll_div2", CLK_IGNORE_UNUSED,
0212             RK2928_CLKGATE_CON(0), 2, GFLAGS),
0213     COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
0214             RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
0215     FACTOR(SCLK_DDRC, "clk_ddrc", "ddrphy2x", 0, 1, 2),
0216     FACTOR(0, "clk_ddrphy", "ddrphy2x", 0, 1, 2),
0217
0218     /* PD_CORE */
0219     GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
0220             RK2928_CLKGATE_CON(0), 6, GFLAGS),
0221     GATE(0, "gpll_div2_core", "gpll_div2", CLK_IGNORE_UNUSED,
0222             RK2928_CLKGATE_CON(0), 6, GFLAGS),
0223     COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
0224             RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
0225             RK2928_CLKGATE_CON(0), 0, GFLAGS),
0226     COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED,
0227             RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
0228             RK2928_CLKGATE_CON(0), 7, GFLAGS),
0229
0230     /* PD_MISC */
0231     MUX(SCLK_USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
0232             RK2928_MISC_CON, 15, 1, MFLAGS),
0233
0234     /* PD_CPU */
0235     COMPOSITE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
0236             RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
0237             RK2928_CLKGATE_CON(0), 1, GFLAGS),
0238     GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
0239             RK2928_CLKGATE_CON(0), 3, GFLAGS),
0240     COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0,
0241             RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
0242             RK2928_CLKGATE_CON(0), 4, GFLAGS),
0243     COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", 0,
0244             RK2928_CLKSEL_CON(1), 12, 2, DFLAGS,
0245             RK2928_CLKGATE_CON(0), 5, GFLAGS),
0246     COMPOSITE_NOMUX(SCLK_CRYPTO, "clk_crypto", "aclk_cpu_src", 0,
0247             RK2928_CLKSEL_CON(24), 0, 2, DFLAGS,
0248             RK2928_CLKGATE_CON(0), 12, GFLAGS),
0249
0250     /* PD_VIDEO */
0251     COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_5plls_p, 0,
0252             RK2928_CLKSEL_CON(32), 5, 3, MFLAGS, 0, 5, DFLAGS,
0253             RK2928_CLKGATE_CON(3), 9, GFLAGS),
0254     FACTOR(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0, 1, 4),
0255
0256     COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_5plls_p, 0,
0257             RK2928_CLKSEL_CON(32), 13, 3, MFLAGS, 8, 5, DFLAGS,
0258             RK2928_CLKGATE_CON(3), 11, GFLAGS),
0259     FACTOR_GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0, 1, 4,
0260             RK2928_CLKGATE_CON(3), 12, GFLAGS),
0261
0262     COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_5plls_p, 0,
0263             RK2928_CLKSEL_CON(34), 13, 3, MFLAGS, 8, 5, DFLAGS,
0264             RK2928_CLKGATE_CON(3), 10, GFLAGS),
0265
0266     /* PD_VIO */
0267     COMPOSITE(ACLK_VIO0, "aclk_vio0", mux_pll_src_5plls_p, 0,
0268             RK2928_CLKSEL_CON(31), 5, 3, MFLAGS, 0, 5, DFLAGS,
0269             RK2928_CLKGATE_CON(3), 0, GFLAGS),
0270     COMPOSITE(ACLK_VIO1, "aclk_vio1", mux_pll_src_5plls_p, 0,
0271             RK2928_CLKSEL_CON(31), 13, 3, MFLAGS, 8, 5, DFLAGS,
0272             RK2928_CLKGATE_CON(1), 4, GFLAGS),
0273     COMPOSITE(HCLK_VIO, "hclk_vio", mux_pll_src_4plls_p, 0,
0274             RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
0275             RK2928_CLKGATE_CON(0), 11, GFLAGS),
0276
0277     /* PD_PERI */
0278     GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
0279             RK2928_CLKGATE_CON(2), 0, GFLAGS),
0280     GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
0281             RK2928_CLKGATE_CON(2), 0, GFLAGS),
0282     GATE(0, "gpll_div2_peri", "gpll_div2", CLK_IGNORE_UNUSED,
0283             RK2928_CLKGATE_CON(2), 0, GFLAGS),
0284     GATE(0, "gpll_div3_peri", "gpll_div3", CLK_IGNORE_UNUSED,
0285             RK2928_CLKGATE_CON(2), 0, GFLAGS),
0286     COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
0287             RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS),
0288     COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
0289             RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
0290             RK2928_CLKGATE_CON(2), 3, GFLAGS),
0291     COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
0292             RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
0293             RK2928_CLKGATE_CON(2), 2, GFLAGS),
0294     GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
0295             RK2928_CLKGATE_CON(2), 1, GFLAGS),
0296
0297     GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
0298             RK2928_CLKGATE_CON(10), 3, GFLAGS),
0299     GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
0300             RK2928_CLKGATE_CON(10), 4, GFLAGS),
0301     GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
0302             RK2928_CLKGATE_CON(10), 5, GFLAGS),
0303     GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
0304             RK2928_CLKGATE_CON(10), 6, GFLAGS),
0305     GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
0306             RK2928_CLKGATE_CON(10), 7, GFLAGS),
0307     GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
0308             RK2928_CLKGATE_CON(10), 8, GFLAGS),
0309
0310     GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
0311             RK2928_CLKGATE_CON(10), 0, GFLAGS),
0312     GATE(SCLK_PVTM_GPU, "clk_pvtm_gpu", "xin24m", 0,
0313             RK2928_CLKGATE_CON(10), 1, GFLAGS),
0314     GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0,
0315             RK2928_CLKGATE_CON(10), 2, GFLAGS),
0316     GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED,
0317             RK2928_CLKGATE_CON(2), 15, GFLAGS),
0318
0319     COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
0320             RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
0321             RK2928_CLKGATE_CON(2), 11, GFLAGS),
0322
0323     COMPOSITE(SCLK_SDIO, "sclk_sdio", mux_mmc_src_p, 0,
0324             RK2928_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
0325             RK2928_CLKGATE_CON(2), 13, GFLAGS),
0326
0327     COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
0328             RK2928_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
0329             RK2928_CLKGATE_CON(2), 14, GFLAGS),
0330
0331     DIV(SCLK_PVTM, "clk_pvtm", "clk_pvtm_func", 0,
0332             RK2928_CLKSEL_CON(2), 0, 7, DFLAGS),
0333
0334     /*
0335      * Clock-Architecture Diagram 2
0336      */
0337     COMPOSITE(DCLK_VOP, "dclk_vop", mux_sclk_vop_src_p, 0,
0338             RK2928_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
0339             RK2928_CLKGATE_CON(3), 1, GFLAGS),
0340     COMPOSITE(SCLK_VOP, "sclk_vop", mux_sclk_vop_src_p, 0,
0341             RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS,
0342             RK2928_CLKGATE_CON(3), 2, GFLAGS),
0343     COMPOSITE(DCLK_EBC, "dclk_ebc", mux_pll_src_3plls_p, 0,
0344             RK2928_CLKSEL_CON(23), 0, 2, MFLAGS, 8, 8, DFLAGS,
0345             RK2928_CLKGATE_CON(3), 4, GFLAGS),
0346
0347     FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
0348
0349     COMPOSITE_NODIV(SCLK_CIF_SRC, "sclk_cif_src", mux_pll_src_4plls_p, 0,
0350             RK2928_CLKSEL_CON(29), 0, 2, MFLAGS,
0351             RK2928_CLKGATE_CON(3), 7, GFLAGS),
0352     MUX(SCLK_CIF_OUT_SRC, "sclk_cif_out_src", mux_clk_cif_out_src_p, 0,
0353             RK2928_CLKSEL_CON(13), 14, 2, MFLAGS),
0354     DIV(SCLK_CIF_OUT, "sclk_cif_out", "sclk_cif_out_src", 0,
0355             RK2928_CLKSEL_CON(29), 2, 5, DFLAGS),
0356
0357     COMPOSITE(0, "i2s0_src", mux_pll_src_3plls_p, 0,
0358             RK2928_CLKSEL_CON(9), 14, 2, MFLAGS, 0, 7, DFLAGS,
0359             RK2928_CLKGATE_CON(4), 4, GFLAGS),
0360     COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
0361             RK2928_CLKSEL_CON(8), 0,
0362             RK2928_CLKGATE_CON(4), 5, GFLAGS,
0363             &rk3128_i2s0_fracmux),
0364     GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
0365             RK2928_CLKGATE_CON(4), 6, GFLAGS),
0366
0367     COMPOSITE(0, "i2s1_src", mux_pll_src_3plls_p, 0,
0368             RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
0369             RK2928_CLKGATE_CON(0), 9, GFLAGS),
0370     COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
0371             RK2928_CLKSEL_CON(7), 0,
0372             RK2928_CLKGATE_CON(0), 10, GFLAGS,
0373             &rk3128_i2s1_fracmux),
0374     GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
0375             RK2928_CLKGATE_CON(0), 14, GFLAGS),
0376     COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
0377             RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
0378             RK2928_CLKGATE_CON(0), 13, GFLAGS),
0379
0380     COMPOSITE(0, "sclk_spdif_src", mux_pll_src_3plls_p, 0,
0381             RK2928_CLKSEL_CON(6), 14, 2, MFLAGS, 0, 7, DFLAGS,
0382             RK2928_CLKGATE_CON(2), 10, GFLAGS),
0383     COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
0384             RK2928_CLKSEL_CON(20), 0,
0385             RK2928_CLKGATE_CON(2), 12, GFLAGS,
0386             &rk3128_spdif_fracmux),
0387
0388     GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
0389             RK2928_CLKGATE_CON(1), 3, GFLAGS),
0390
0391     GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", 0,
0392             RK2928_CLKGATE_CON(1), 5, GFLAGS),
0393     GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin12m", 0,
0394             RK2928_CLKGATE_CON(1), 6, GFLAGS),
0395
0396     COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
0397             RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
0398             RK2928_CLKGATE_CON(2), 8, GFLAGS),
0399
0400     COMPOSITE(ACLK_GPU, "aclk_gpu", mux_pll_src_5plls_p, 0,
0401             RK2928_CLKSEL_CON(34), 5, 3, MFLAGS, 0, 5, DFLAGS,
0402             RK2928_CLKGATE_CON(3), 13, GFLAGS),
0403
0404     COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_3plls_p, 0,
0405             RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS,
0406             RK2928_CLKGATE_CON(2), 9, GFLAGS),
0407
0408     /* PD_UART */
0409     COMPOSITE(0, "uart0_src", mux_pll_src_4plls_p, 0,
0410             RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
0411             RK2928_CLKGATE_CON(1), 8, GFLAGS),
0412     MUX(0, "uart12_src", mux_pll_src_4plls_p, 0,
0413             RK2928_CLKSEL_CON(13), 14, 2, MFLAGS),
0414     COMPOSITE_NOMUX(0, "uart1_src", "uart12_src", 0,
0415             RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
0416             RK2928_CLKGATE_CON(1), 10, GFLAGS),
0417     COMPOSITE_NOMUX(0, "uart2_src", "uart12_src", 0,
0418             RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
0419             RK2928_CLKGATE_CON(1), 13, GFLAGS),
0420     COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
0421             RK2928_CLKSEL_CON(17), 0,
0422             RK2928_CLKGATE_CON(1), 9, GFLAGS,
0423             &rk3128_uart0_fracmux),
0424     COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
0425             RK2928_CLKSEL_CON(18), 0,
0426             RK2928_CLKGATE_CON(1), 11, GFLAGS,
0427             &rk3128_uart1_fracmux),
0428     COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
0429             RK2928_CLKSEL_CON(19), 0,
0430             RK2928_CLKGATE_CON(1), 13, GFLAGS,
0431             &rk3128_uart2_fracmux),
0432
0433     COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_3plls_p, 0,
0434             RK2928_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
0435             RK2928_CLKGATE_CON(1), 7, GFLAGS),
0436     MUX(SCLK_MAC, "sclk_gmac", mux_sclk_gmac_p, 0,
0437             RK2928_CLKSEL_CON(5), 15, 1, MFLAGS),
0438     GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac", 0,
0439             RK2928_CLKGATE_CON(2), 5, GFLAGS),
0440     GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac", 0,
0441             RK2928_CLKGATE_CON(2), 4, GFLAGS),
0442     GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac", 0,
0443             RK2928_CLKGATE_CON(2), 6, GFLAGS),
0444     GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac", 0,
0445             RK2928_CLKGATE_CON(2), 7, GFLAGS),
0446
0447     COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_3plls_p, 0,
0448             RK2928_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS,
0449             RK2928_CLKGATE_CON(1), 14, GFLAGS),
0450
0451     COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
0452             RK2928_CLKSEL_CON(2), 14, 2, MFLAGS, 8, 5, DFLAGS,
0453             RK2928_CLKGATE_CON(10), 15, GFLAGS),
0454
0455     COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "cpll", 0,
0456             RK2928_CLKSEL_CON(29), 8, 6, DFLAGS,
0457             RK2928_CLKGATE_CON(1), 0, GFLAGS),
0458
0459     /*
0460      * Clock-Architecture Diagram 3
0461      */
0462
0463     /* PD_VOP */
0464     GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS),
0465     GATE(ACLK_CIF, "aclk_cif", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS),
0466     GATE(ACLK_RGA, "aclk_rga", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
0467     GATE(0, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS),
0468
0469     GATE(ACLK_IEP, "aclk_iep", "aclk_vio1", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
0470     GATE(0, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 10, GFLAGS),
0471
0472     GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
0473     GATE(PCLK_MIPI, "pclk_mipi", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
0474     GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
0475     GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
0476     GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
0477     GATE(0, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS),
0478     GATE(HCLK_CIF, "hclk_cif", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
0479     GATE(HCLK_EBC, "hclk_ebc", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS),
0480
0481     /* PD_PERI */
0482     GATE(0, "aclk_peri_axi", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
0483     GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(10), 10, GFLAGS),
0484     GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
0485     GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS),
0486     GATE(0, "aclk_cpu_to_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
0487
0488     GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
0489     GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
0490     GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
0491     GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS),
0492     GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
0493     GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 13, GFLAGS),
0494     GATE(0, "hclk_peri_ahb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS),
0495     GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
0496     GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 12, GFLAGS),
0497     GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
0498     GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
0499     GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
0500     GATE(0, "hclk_emmc_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 6, GFLAGS),
0501     GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
0502     GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_peri", 0, RK2928_CLKGATE_CON(10), 14, GFLAGS),
0503
0504     GATE(PCLK_SIM_CARD, "pclk_sim_card", "pclk_peri", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),
0505     GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
0506     GATE(0, "pclk_peri_axi", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
0507     GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
0508     GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
0509     GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
0510     GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
0511     GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
0512     GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
0513     GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
0514     GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
0515     GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
0516     GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
0517     GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
0518     GATE(PCLK_EFUSE, "pclk_efuse", "pclk_peri", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS),
0519     GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 7, GFLAGS),
0520     GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
0521     GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
0522     GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
0523     GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
0524
0525     /* PD_BUS */
0526     GATE(0, "aclk_initmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
0527     GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
0528
0529     GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS),
0530     GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
0531
0532     GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
0533     GATE(0, "pclk_ddrupctl", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 7, GFLAGS),
0534     GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
0535     GATE(0, "pclk_mipiphy", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 0, GFLAGS),
0536
0537     GATE(0, "pclk_pmu", "pclk_pmu_pre", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
0538     GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS),
0539
0540     /* PD_MMC */
0541     MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
0542     MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),
0543
0544     MMC(SCLK_SDIO_DRV,     "sdio_drv",     "sclk_sdio",  RK3228_SDIO_CON0,  1),
0545     MMC(SCLK_SDIO_SAMPLE,  "sdio_sample",  "sclk_sdio",  RK3228_SDIO_CON1,  0),
0546
0547     MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3228_EMMC_CON0,  1),
0548     MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3228_EMMC_CON1,  0),
0549 };
0550
0551 static struct rockchip_clk_branch rk3126_clk_branches[] __initdata = {
0552     GATE(0, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS),
0553     GATE(0, "pclk_s_efuse", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
0554     GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 8, GFLAGS),
0555 };
0556
0557 static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = {
0558     COMPOSITE(SCLK_SFC, "sclk_sfc", mux_sclk_sfc_src_p, 0,
0559             RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
0560             RK2928_CLKGATE_CON(3), 15, GFLAGS),
0561
0562     GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
0563     GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
0564 };
0565
0566 static const char *const rk3128_critical_clocks[] __initconst = {
0567     "aclk_cpu",
0568     "hclk_cpu",
0569     "pclk_cpu",
0570     "aclk_peri",
0571     "hclk_peri",
0572     "pclk_peri",
0573     "pclk_pmu",
0574     "sclk_timer5",
0575 };
0576
0577 static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np)
0578 {
0579     struct rockchip_clk_provider *ctx;
0580     void __iomem *reg_base;
0581
0582     reg_base = of_iomap(np, 0);
0583     if (!reg_base) {
0584         pr_err("%s: could not map cru region\n", __func__);
0585         return ERR_PTR(-ENOMEM);
0586     }
0587
0588     ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
0589     if (IS_ERR(ctx)) {
0590         pr_err("%s: rockchip clk init failed\n", __func__);
0591         iounmap(reg_base);
0592         return ERR_PTR(-ENOMEM);
0593     }
0594
0595     rockchip_clk_register_plls(ctx, rk3128_pll_clks,
0596                    ARRAY_SIZE(rk3128_pll_clks),
0597                    RK3128_GRF_SOC_STATUS0);
0598     rockchip_clk_register_branches(ctx, common_clk_branches,
0599                   ARRAY_SIZE(common_clk_branches));
0600
0601     rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
0602             mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
0603             &rk3128_cpuclk_data, rk3128_cpuclk_rates,
0604             ARRAY_SIZE(rk3128_cpuclk_rates));
0605
0606     rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
0607                   ROCKCHIP_SOFTRST_HIWORD_MASK);
0608
0609     rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
0610
0611     return ctx;
0612 }
0613
0614 static void __init rk3126_clk_init(struct device_node *np)
0615 {
0616     struct rockchip_clk_provider *ctx;
0617
0618     ctx = rk3128_common_clk_init(np);
0619     if (IS_ERR(ctx))
0620         return;
0621
0622     rockchip_clk_register_branches(ctx, rk3126_clk_branches,
0623                        ARRAY_SIZE(rk3126_clk_branches));
0624     rockchip_clk_protect_critical(rk3128_critical_clocks,
0625                       ARRAY_SIZE(rk3128_critical_clocks));
0626
0627     rockchip_clk_of_add_provider(np, ctx);
0628 }
0629
0630 CLK_OF_DECLARE(rk3126_cru, "rockchip,rk3126-cru", rk3126_clk_init);
0631
0632 static void __init rk3128_clk_init(struct device_node *np)
0633 {
0634     struct rockchip_clk_provider *ctx;
0635
0636     ctx = rk3128_common_clk_init(np);
0637     if (IS_ERR(ctx))
0638         return;
0639
0640     rockchip_clk_register_branches(ctx, rk3128_clk_branches,
0641                        ARRAY_SIZE(rk3128_clk_branches));
0642     rockchip_clk_protect_critical(rk3128_critical_clocks,
0643                       ARRAY_SIZE(rk3128_critical_clocks));
0644
0645     rockchip_clk_of_add_provider(np, ctx);
0646 }
0647
0648 CLK_OF_DECLARE(rk3128_cru, "rockchip,rk3128-cru", rk3128_clk_init);