clk/rockchip/clk-rk3036.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2014 MundoReader S.L.
0004  * Author: Heiko Stuebner <heiko@sntech.de>
0005  *
0006  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
0007  * Author: Xing Zheng <zhengxing@rock-chips.com>
0008  */
0009
0010 #include <linux/clk-provider.h>
0011 #include <linux/io.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/syscore_ops.h>
0015 #include <dt-bindings/clock/rk3036-cru.h>
0016 #include "clk.h"
0017
0018 #define RK3036_GRF_SOC_STATUS0  0x14c
0019
0020 enum rk3036_plls {
0021     apll, dpll, gpll,
0022 };
0023
0024 static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
0025     /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
0026     RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
0027     RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
0028     RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
0029     RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
0030     RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
0031     RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
0032     RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
0033     RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
0034     RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
0035     RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
0036     RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
0037     RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
0038     RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
0039     RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
0040     RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
0041     RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
0042     RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
0043     RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
0044     RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
0045     RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
0046     RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
0047     RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
0048     RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
0049     RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
0050     RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
0051     RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
0052     RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
0053     RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
0054     RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
0055     RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
0056     RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
0057     RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
0058     RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
0059     RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
0060     RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
0061     RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
0062     RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
0063     RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
0064     RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
0065     RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
0066     RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
0067     RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
0068     { /* sentinel */ },
0069 };
0070
0071 #define RK3036_DIV_CPU_MASK     0x1f
0072 #define RK3036_DIV_CPU_SHIFT        8
0073
0074 #define RK3036_DIV_PERI_MASK        0xf
0075 #define RK3036_DIV_PERI_SHIFT       0
0076 #define RK3036_DIV_ACLK_MASK        0x7
0077 #define RK3036_DIV_ACLK_SHIFT       4
0078 #define RK3036_DIV_HCLK_MASK        0x3
0079 #define RK3036_DIV_HCLK_SHIFT       8
0080 #define RK3036_DIV_PCLK_MASK        0x7
0081 #define RK3036_DIV_PCLK_SHIFT       12
0082
0083 #define RK3036_CLKSEL1(_core_periph_div)                    \
0084     {                                   \
0085         .reg = RK2928_CLKSEL_CON(1),                    \
0086         .val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK,    \
0087                 RK3036_DIV_PERI_SHIFT)              \
0088     }
0089
0090 #define RK3036_CPUCLK_RATE(_prate, _core_periph_div)            \
0091     {                               \
0092         .prate = _prate,                    \
0093         .divs = {                       \
0094             RK3036_CLKSEL1(_core_periph_div),       \
0095         },                          \
0096     }
0097
0098 static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = {
0099     RK3036_CPUCLK_RATE(816000000, 4),
0100     RK3036_CPUCLK_RATE(600000000, 4),
0101     RK3036_CPUCLK_RATE(312000000, 4),
0102 };
0103
0104 static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
0105     .core_reg[0] = RK2928_CLKSEL_CON(0),
0106     .div_core_shift[0] = 0,
0107     .div_core_mask[0] = 0x1f,
0108     .num_cores = 1,
0109     .mux_core_alt = 1,
0110     .mux_core_main = 0,
0111     .mux_core_shift = 7,
0112     .mux_core_mask = 0x1,
0113 };
0114
0115 PNAME(mux_pll_p)        = { "xin24m", "xin24m" };
0116
0117 PNAME(mux_armclk_p)     = { "apll", "gpll_armclk" };
0118 PNAME(mux_busclk_p)     = { "apll", "dpll_cpu", "gpll_cpu" };
0119 PNAME(mux_ddrphy_p)     = { "dpll_ddr", "gpll_ddr" };
0120 PNAME(mux_pll_src_3plls_p)  = { "apll", "dpll", "gpll" };
0121 PNAME(mux_timer_p)      = { "xin24m", "pclk_peri_src" };
0122
0123 PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
0124 PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p)   = { "dummy_apll", "dpll", "gpll", "xin24m" };
0125
0126 PNAME(mux_mmc_src_p)    = { "apll", "dpll", "gpll", "xin24m" };
0127 PNAME(mux_i2s_pre_p)    = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
0128 PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
0129 PNAME(mux_spdif_p)  = { "spdif_src", "spdif_frac", "xin12m" };
0130 PNAME(mux_uart0_p)  = { "uart0_src", "uart0_frac", "xin24m" };
0131 PNAME(mux_uart1_p)  = { "uart1_src", "uart1_frac", "xin24m" };
0132 PNAME(mux_uart2_p)  = { "uart2_src", "uart2_frac", "xin24m" };
0133 PNAME(mux_mac_p)    = { "mac_pll_src", "rmii_clkin" };
0134 PNAME(mux_dclk_p)   = { "dclk_lcdc", "dclk_cru" };
0135
0136 static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = {
0137     [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
0138              RK2928_MODE_CON, 0, 5, 0, rk3036_pll_rates),
0139     [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
0140              RK2928_MODE_CON, 4, 4, 0, NULL),
0141     [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
0142              RK2928_MODE_CON, 12, 6, ROCKCHIP_PLL_SYNC_RATE, rk3036_pll_rates),
0143 };
0144
0145 #define MFLAGS CLK_MUX_HIWORD_MASK
0146 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
0147 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
0148
0149 static struct rockchip_clk_branch rk3036_uart0_fracmux __initdata =
0150     MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
0151             RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
0152
0153 static struct rockchip_clk_branch rk3036_uart1_fracmux __initdata =
0154     MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
0155             RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
0156
0157 static struct rockchip_clk_branch rk3036_uart2_fracmux __initdata =
0158     MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
0159             RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
0160
0161 static struct rockchip_clk_branch rk3036_i2s_fracmux __initdata =
0162     MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
0163             RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
0164
0165 static struct rockchip_clk_branch rk3036_spdif_fracmux __initdata =
0166     MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
0167             RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
0168
0169 static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
0170     /*
0171      * Clock-Architecture Diagram 1
0172      */
0173
0174     GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,
0175             RK2928_CLKGATE_CON(0), 6, GFLAGS),
0176
0177     FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
0178
0179     /*
0180      * Clock-Architecture Diagram 2
0181      */
0182
0183     GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
0184             RK2928_CLKGATE_CON(0), 2, GFLAGS),
0185     GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
0186             RK2928_CLKGATE_CON(0), 8, GFLAGS),
0187     COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
0188             RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
0189     FACTOR(0, "ddrphy", "ddrphy2x", 0, 1, 2),
0190
0191     COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
0192             RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
0193             RK2928_CLKGATE_CON(0), 7, GFLAGS),
0194     COMPOSITE_NOMUX(0, "aclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
0195             RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
0196             RK2928_CLKGATE_CON(0), 7, GFLAGS),
0197
0198     GATE(0, "dpll_cpu", "dpll", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
0199     GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
0200     COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_busclk_p, 0,
0201             RK2928_CLKSEL_CON(0), 14, 2, MFLAGS, 8, 5, DFLAGS),
0202     GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
0203             RK2928_CLKGATE_CON(0), 3, GFLAGS),
0204     COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
0205             RK2928_CLKSEL_CON(1), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
0206             RK2928_CLKGATE_CON(0), 5, GFLAGS),
0207     COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
0208             RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
0209             RK2928_CLKGATE_CON(0), 4, GFLAGS),
0210
0211     COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
0212             RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,
0213             RK2928_CLKGATE_CON(2), 0, GFLAGS),
0214
0215     GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
0216             RK2928_CLKGATE_CON(2), 1, GFLAGS),
0217     DIV(0, "pclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED,
0218             RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
0219     GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", 0,
0220             RK2928_CLKGATE_CON(2), 3, GFLAGS),
0221     DIV(0, "hclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED,
0222             RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
0223     GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", 0,
0224             RK2928_CLKGATE_CON(2), 2, GFLAGS),
0225
0226     COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED,
0227             RK2928_CLKSEL_CON(2), 4, 1, MFLAGS,
0228             RK2928_CLKGATE_CON(1), 0, GFLAGS),
0229     COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1", mux_timer_p, CLK_IGNORE_UNUSED,
0230             RK2928_CLKSEL_CON(2), 5, 1, MFLAGS,
0231             RK2928_CLKGATE_CON(1), 1, GFLAGS),
0232     COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2", mux_timer_p, CLK_IGNORE_UNUSED,
0233             RK2928_CLKSEL_CON(2), 6, 1, MFLAGS,
0234             RK2928_CLKGATE_CON(2), 4, GFLAGS),
0235     COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3", mux_timer_p, CLK_IGNORE_UNUSED,
0236             RK2928_CLKSEL_CON(2), 7, 1, MFLAGS,
0237             RK2928_CLKGATE_CON(2), 5, GFLAGS),
0238
0239     MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
0240             RK2928_CLKSEL_CON(13), 10, 2, MFLAGS),
0241     COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0,
0242             RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
0243             RK2928_CLKGATE_CON(1), 8, GFLAGS),
0244     COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0,
0245             RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
0246             RK2928_CLKGATE_CON(1), 10, GFLAGS),
0247     COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,
0248             RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
0249             RK2928_CLKGATE_CON(1), 12, GFLAGS),
0250     COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
0251             RK2928_CLKSEL_CON(17), 0,
0252             RK2928_CLKGATE_CON(1), 9, GFLAGS,
0253             &rk3036_uart0_fracmux),
0254     COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
0255             RK2928_CLKSEL_CON(18), 0,
0256             RK2928_CLKGATE_CON(1), 11, GFLAGS,
0257             &rk3036_uart1_fracmux),
0258     COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
0259             RK2928_CLKSEL_CON(19), 0,
0260             RK2928_CLKGATE_CON(1), 13, GFLAGS,
0261             &rk3036_uart2_fracmux),
0262
0263     COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_3plls_p, 0,
0264             RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
0265             RK2928_CLKGATE_CON(3), 11, GFLAGS),
0266     FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4,
0267             RK2928_CLKGATE_CON(3), 12, GFLAGS),
0268
0269     COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,
0270             RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS,
0271             RK2928_CLKGATE_CON(10), 6, GFLAGS),
0272
0273     COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0,
0274             RK2928_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
0275             RK2928_CLKGATE_CON(1), 4, GFLAGS),
0276     COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0,
0277             RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
0278             RK2928_CLKGATE_CON(0), 11, GFLAGS),
0279     COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0,
0280             RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS,
0281             RK2928_CLKGATE_CON(3), 2, GFLAGS),
0282
0283     COMPOSITE_NODIV(0, "sclk_sdmmc_src", mux_mmc_src_p, 0,
0284             RK2928_CLKSEL_CON(12), 8, 2, MFLAGS,
0285             RK2928_CLKGATE_CON(2), 11, GFLAGS),
0286     DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0,
0287             RK2928_CLKSEL_CON(11), 0, 7, DFLAGS),
0288
0289     COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
0290             RK2928_CLKSEL_CON(12), 10, 2, MFLAGS,
0291             RK2928_CLKGATE_CON(2), 13, GFLAGS),
0292     DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
0293             RK2928_CLKSEL_CON(11), 8, 7, DFLAGS),
0294
0295     COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
0296             RK2928_CLKSEL_CON(12), 12, 2, MFLAGS, 0, 7, DFLAGS,
0297             RK2928_CLKGATE_CON(2), 14, GFLAGS),
0298
0299     MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3036_SDMMC_CON0, 1),
0300     MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3036_SDMMC_CON1, 0),
0301
0302     MMC(SCLK_SDIO_DRV,     "sdio_drv",     "sclk_sdio",  RK3036_SDIO_CON0, 1),
0303     MMC(SCLK_SDIO_SAMPLE,  "sdio_sample",  "sclk_sdio",  RK3036_SDIO_CON1, 0),
0304
0305     MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3036_EMMC_CON0,  1),
0306     MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3036_EMMC_CON1,  0),
0307
0308     COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,
0309             RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
0310             RK2928_CLKGATE_CON(0), 9, GFLAGS),
0311     COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
0312             RK2928_CLKSEL_CON(7), 0,
0313             RK2928_CLKGATE_CON(0), 10, GFLAGS,
0314             &rk3036_i2s_fracmux),
0315     COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout", mux_i2s_clkout_p, 0,
0316             RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
0317             RK2928_CLKGATE_CON(0), 13, GFLAGS),
0318     GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT,
0319             RK2928_CLKGATE_CON(0), 14, GFLAGS),
0320
0321     COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,
0322             RK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS,
0323             RK2928_CLKGATE_CON(2), 10, GFLAGS),
0324     COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0,
0325             RK2928_CLKSEL_CON(9), 0,
0326             RK2928_CLKGATE_CON(2), 12, GFLAGS,
0327             &rk3036_spdif_fracmux),
0328
0329     GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
0330             RK2928_CLKGATE_CON(1), 5, GFLAGS),
0331
0332     COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0,
0333             RK2928_CLKSEL_CON(34), 8, 2, MFLAGS, 0, 5, DFLAGS,
0334             RK2928_CLKGATE_CON(3), 13, GFLAGS),
0335
0336     COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_3plls_p, 0,
0337             RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS,
0338             RK2928_CLKGATE_CON(2), 9, GFLAGS),
0339
0340     COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
0341             RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS,
0342             RK2928_CLKGATE_CON(10), 4, GFLAGS),
0343
0344     COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_dmyapll_dpll_gpll_xin24_p, 0,
0345             RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
0346             RK2928_CLKGATE_CON(10), 5, GFLAGS),
0347
0348     COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT,
0349             RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
0350     MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
0351             RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
0352
0353     COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,
0354             RK2928_CLKSEL_CON(21), 4, 5, DFLAGS,
0355             RK2928_CLKGATE_CON(2), 6, GFLAGS),
0356     FACTOR(0, "sclk_macref_out", "hclk_peri_src", 0, 1, 2),
0357
0358     MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
0359             RK2928_CLKSEL_CON(31), 0, 1, MFLAGS),
0360
0361     /*
0362      * Clock-Architecture Diagram 3
0363      */
0364
0365     /* aclk_cpu gates */
0366     GATE(0, "sclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
0367     GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
0368
0369     /* hclk_cpu gates */
0370     GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS),
0371
0372     /* pclk_cpu gates */
0373     GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
0374     GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
0375     GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
0376     GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
0377
0378     /* aclk_vio gates */
0379     GATE(ACLK_VIO, "aclk_vio", "aclk_disp1_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS),
0380     GATE(ACLK_LCDC, "aclk_lcdc", "aclk_disp1_pre", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
0381
0382     GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS),
0383     GATE(HCLK_LCDC, "hclk_lcdc", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
0384
0385
0386     /* xin24m gates */
0387     GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS),
0388     GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK2928_CLKGATE_CON(10), 1, GFLAGS),
0389
0390     /* aclk_peri gates */
0391     GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
0392     GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
0393     GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
0394     GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS),
0395
0396     /* hclk_peri gates */
0397     GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
0398     GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS),
0399     GATE(0, "hclk_peri_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS),
0400     GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
0401     GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
0402     GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
0403     GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
0404     GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
0405     GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS),
0406     GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
0407     GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
0408     GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
0409
0410     /* pclk_peri gates */
0411     GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
0412     GATE(0, "pclk_efuse", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 2, GFLAGS),
0413     GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
0414     GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
0415     GATE(PCLK_SPI, "pclk_spi", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
0416     GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
0417     GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
0418     GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
0419     GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
0420     GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
0421     GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
0422     GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
0423     GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
0424     GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
0425     GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
0426 };
0427
0428 static const char *const rk3036_critical_clocks[] __initconst = {
0429     "aclk_cpu",
0430     "aclk_peri",
0431     "hclk_peri",
0432     "pclk_peri",
0433     "pclk_ddrupctl",
0434 };
0435
0436 static void __init rk3036_clk_init(struct device_node *np)
0437 {
0438     struct rockchip_clk_provider *ctx;
0439     void __iomem *reg_base;
0440     struct clk *clk;
0441
0442     reg_base = of_iomap(np, 0);
0443     if (!reg_base) {
0444         pr_err("%s: could not map cru region\n", __func__);
0445         return;
0446     }
0447
0448     /*
0449      * Make uart_pll_clk a child of the gpll, as all other sources are
0450      * not that usable / stable.
0451      */
0452     writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10),
0453                reg_base + RK2928_CLKSEL_CON(13));
0454
0455     ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
0456     if (IS_ERR(ctx)) {
0457         pr_err("%s: rockchip clk init failed\n", __func__);
0458         iounmap(reg_base);
0459         return;
0460     }
0461
0462     clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
0463     if (IS_ERR(clk))
0464         pr_warn("%s: could not register clock usb480m: %ld\n",
0465             __func__, PTR_ERR(clk));
0466
0467     rockchip_clk_register_plls(ctx, rk3036_pll_clks,
0468                    ARRAY_SIZE(rk3036_pll_clks),
0469                    RK3036_GRF_SOC_STATUS0);
0470     rockchip_clk_register_branches(ctx, rk3036_clk_branches,
0471                   ARRAY_SIZE(rk3036_clk_branches));
0472     rockchip_clk_protect_critical(rk3036_critical_clocks,
0473                       ARRAY_SIZE(rk3036_critical_clocks));
0474
0475     rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
0476             mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
0477             &rk3036_cpuclk_data, rk3036_cpuclk_rates,
0478             ARRAY_SIZE(rk3036_cpuclk_rates));
0479
0480     rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
0481                   ROCKCHIP_SOFTRST_HIWORD_MASK);
0482
0483     rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);
0484
0485     rockchip_clk_of_add_provider(np, ctx);
0486 }
0487 CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru", rk3036_clk_init);