clk/rockchip/clk-px30.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
0004  * Author: Elaine Zhang<zhangqing@rock-chips.com>
0005  */
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/io.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/syscore_ops.h>
0012 #include <dt-bindings/clock/px30-cru.h>
0013 #include "clk.h"
0014
0015 #define PX30_GRF_SOC_STATUS0        0x480
0016
0017 enum px30_plls {
0018     apll, dpll, cpll, npll, apll_b_h, apll_b_l,
0019 };
0020
0021 enum px30_pmu_plls {
0022     gpll,
0023 };
0024
0025 static struct rockchip_pll_rate_table px30_pll_rates[] = {
0026     /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
0027     RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
0028     RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
0029     RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
0030     RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
0031     RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
0032     RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
0033     RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
0034     RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
0035     RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
0036     RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
0037     RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
0038     RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
0039     RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
0040     RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
0041     RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
0042     RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
0043     RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
0044     RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
0045     RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
0046     RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
0047     RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
0048     RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
0049     RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
0050     RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
0051     RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
0052     RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
0053     RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
0054     RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
0055     RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
0056     RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
0057     RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
0058     RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
0059     RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
0060     RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
0061     RK3036_PLL_RATE(624000000, 1, 52, 2, 1, 1, 0),
0062     RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
0063     RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
0064     RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
0065     RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
0066     RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
0067     RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
0068     RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
0069     RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
0070     { /* sentinel */ },
0071 };
0072
0073 #define PX30_DIV_ACLKM_MASK     0x7
0074 #define PX30_DIV_ACLKM_SHIFT        12
0075 #define PX30_DIV_PCLK_DBG_MASK  0xf
0076 #define PX30_DIV_PCLK_DBG_SHIFT 8
0077
0078 #define PX30_CLKSEL0(_aclk_core, _pclk_dbg)             \
0079 {                                   \
0080     .reg = PX30_CLKSEL_CON(0),                  \
0081     .val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK,       \
0082                  PX30_DIV_ACLKM_SHIFT) |            \
0083            HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK, \
0084                  PX30_DIV_PCLK_DBG_SHIFT),      \
0085 }
0086
0087 #define PX30_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg)     \
0088 {                                   \
0089     .prate = _prate,                        \
0090     .divs = {                           \
0091         PX30_CLKSEL0(_aclk_core, _pclk_dbg),            \
0092     },                              \
0093 }
0094
0095 static struct rockchip_cpuclk_rate_table px30_cpuclk_rates[] __initdata = {
0096     PX30_CPUCLK_RATE(1608000000, 1, 7),
0097     PX30_CPUCLK_RATE(1584000000, 1, 7),
0098     PX30_CPUCLK_RATE(1560000000, 1, 7),
0099     PX30_CPUCLK_RATE(1536000000, 1, 7),
0100     PX30_CPUCLK_RATE(1512000000, 1, 7),
0101     PX30_CPUCLK_RATE(1488000000, 1, 5),
0102     PX30_CPUCLK_RATE(1464000000, 1, 5),
0103     PX30_CPUCLK_RATE(1440000000, 1, 5),
0104     PX30_CPUCLK_RATE(1416000000, 1, 5),
0105     PX30_CPUCLK_RATE(1392000000, 1, 5),
0106     PX30_CPUCLK_RATE(1368000000, 1, 5),
0107     PX30_CPUCLK_RATE(1344000000, 1, 5),
0108     PX30_CPUCLK_RATE(1320000000, 1, 5),
0109     PX30_CPUCLK_RATE(1296000000, 1, 5),
0110     PX30_CPUCLK_RATE(1272000000, 1, 5),
0111     PX30_CPUCLK_RATE(1248000000, 1, 5),
0112     PX30_CPUCLK_RATE(1224000000, 1, 5),
0113     PX30_CPUCLK_RATE(1200000000, 1, 5),
0114     PX30_CPUCLK_RATE(1104000000, 1, 5),
0115     PX30_CPUCLK_RATE(1008000000, 1, 5),
0116     PX30_CPUCLK_RATE(912000000, 1, 5),
0117     PX30_CPUCLK_RATE(816000000, 1, 3),
0118     PX30_CPUCLK_RATE(696000000, 1, 3),
0119     PX30_CPUCLK_RATE(600000000, 1, 3),
0120     PX30_CPUCLK_RATE(408000000, 1, 1),
0121     PX30_CPUCLK_RATE(312000000, 1, 1),
0122     PX30_CPUCLK_RATE(216000000,  1, 1),
0123     PX30_CPUCLK_RATE(96000000, 1, 1),
0124 };
0125
0126 static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = {
0127     .core_reg[0] = PX30_CLKSEL_CON(0),
0128     .div_core_shift[0] = 0,
0129     .div_core_mask[0] = 0xf,
0130     .num_cores = 1,
0131     .mux_core_alt = 1,
0132     .mux_core_main = 0,
0133     .mux_core_shift = 7,
0134     .mux_core_mask = 0x1,
0135 };
0136
0137 PNAME(mux_pll_p)        = { "xin24m"};
0138 PNAME(mux_usb480m_p)        = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
0139 PNAME(mux_armclk_p)     = { "apll_core", "gpll_core" };
0140 PNAME(mux_ddrphy_p)     = { "dpll_ddr", "gpll_ddr" };
0141 PNAME(mux_ddrstdby_p)       = { "clk_ddrphy1x", "clk_stdby_2wrap" };
0142 PNAME(mux_4plls_p)      = { "gpll", "dummy_cpll", "usb480m", "npll" };
0143 PNAME(mux_cpll_npll_p)      = { "cpll", "npll" };
0144 PNAME(mux_npll_cpll_p)      = { "npll", "cpll" };
0145 PNAME(mux_gpll_cpll_p)      = { "gpll", "dummy_cpll" };
0146 PNAME(mux_gpll_npll_p)      = { "gpll", "npll" };
0147 PNAME(mux_gpll_xin24m_p)        = { "gpll", "xin24m"};
0148 PNAME(mux_gpll_cpll_npll_p)     = { "gpll", "dummy_cpll", "npll" };
0149 PNAME(mux_gpll_cpll_npll_xin24m_p)  = { "gpll", "dummy_cpll", "npll", "xin24m" };
0150 PNAME(mux_gpll_xin24m_npll_p)       = { "gpll", "xin24m", "npll"};
0151 PNAME(mux_pdm_p)        = { "clk_pdm_src", "clk_pdm_frac" };
0152 PNAME(mux_i2s0_tx_p)        = { "clk_i2s0_tx_src", "clk_i2s0_tx_frac", "mclk_i2s0_tx_in", "xin12m"};
0153 PNAME(mux_i2s0_rx_p)        = { "clk_i2s0_rx_src", "clk_i2s0_rx_frac", "mclk_i2s0_rx_in", "xin12m"};
0154 PNAME(mux_i2s1_p)       = { "clk_i2s1_src", "clk_i2s1_frac", "i2s1_clkin", "xin12m"};
0155 PNAME(mux_i2s2_p)       = { "clk_i2s2_src", "clk_i2s2_frac", "i2s2_clkin", "xin12m"};
0156 PNAME(mux_i2s0_tx_out_p)    = { "clk_i2s0_tx", "xin12m", "clk_i2s0_rx"};
0157 PNAME(mux_i2s0_rx_out_p)    = { "clk_i2s0_rx", "xin12m", "clk_i2s0_tx"};
0158 PNAME(mux_i2s1_out_p)       = { "clk_i2s1", "xin12m"};
0159 PNAME(mux_i2s2_out_p)       = { "clk_i2s2", "xin12m"};
0160 PNAME(mux_i2s0_tx_rx_p)     = { "clk_i2s0_tx_mux", "clk_i2s0_rx_mux"};
0161 PNAME(mux_i2s0_rx_tx_p)     = { "clk_i2s0_rx_mux", "clk_i2s0_tx_mux"};
0162 PNAME(mux_uart_src_p)       = { "gpll", "xin24m", "usb480m", "npll" };
0163 PNAME(mux_uart1_p)      = { "clk_uart1_src", "clk_uart1_np5", "clk_uart1_frac" };
0164 PNAME(mux_uart2_p)      = { "clk_uart2_src", "clk_uart2_np5", "clk_uart2_frac" };
0165 PNAME(mux_uart3_p)      = { "clk_uart3_src", "clk_uart3_np5", "clk_uart3_frac" };
0166 PNAME(mux_uart4_p)      = { "clk_uart4_src", "clk_uart4_np5", "clk_uart4_frac" };
0167 PNAME(mux_uart5_p)      = { "clk_uart5_src", "clk_uart5_np5", "clk_uart5_frac" };
0168 PNAME(mux_cif_out_p)        = { "xin24m", "dummy_cpll", "npll", "usb480m" };
0169 PNAME(mux_dclk_vopb_p)      = { "dclk_vopb_src", "dclk_vopb_frac", "xin24m" };
0170 PNAME(mux_dclk_vopl_p)      = { "dclk_vopl_src", "dclk_vopl_frac", "xin24m" };
0171 PNAME(mux_nandc_p)      = { "clk_nandc_div", "clk_nandc_div50" };
0172 PNAME(mux_sdio_p)       = { "clk_sdio_div", "clk_sdio_div50" };
0173 PNAME(mux_emmc_p)       = { "clk_emmc_div", "clk_emmc_div50" };
0174 PNAME(mux_sdmmc_p)      = { "clk_sdmmc_div", "clk_sdmmc_div50" };
0175 PNAME(mux_gmac_p)       = { "clk_gmac_src", "gmac_clkin" };
0176 PNAME(mux_gmac_rmii_sel_p)  = { "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx_div2" };
0177 PNAME(mux_rtc32k_pmu_p)     = { "xin32k", "pmu_pvtm_32k", "clk_rtc32k_frac", };
0178 PNAME(mux_wifi_pmu_p)       = { "xin24m", "clk_wifi_pmu_src" };
0179 PNAME(mux_uart0_pmu_p)      = { "clk_uart0_pmu_src", "clk_uart0_np5", "clk_uart0_frac" };
0180 PNAME(mux_usbphy_ref_p)     = { "xin24m", "clk_ref24m_pmu" };
0181 PNAME(mux_mipidsiphy_ref_p) = { "xin24m", "clk_ref24m_pmu" };
0182 PNAME(mux_gpu_p)        = { "clk_gpu_div", "clk_gpu_np5" };
0183
0184 static struct rockchip_pll_clock px30_pll_clks[] __initdata = {
0185     [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
0186              0, PX30_PLL_CON(0),
0187              PX30_MODE_CON, 0, 0, 0, px30_pll_rates),
0188     [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
0189              0, PX30_PLL_CON(8),
0190              PX30_MODE_CON, 4, 1, 0, NULL),
0191     [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
0192              0, PX30_PLL_CON(16),
0193              PX30_MODE_CON, 2, 2, 0, px30_pll_rates),
0194     [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
0195              0, PX30_PLL_CON(24),
0196              PX30_MODE_CON, 6, 4, 0, px30_pll_rates),
0197 };
0198
0199 static struct rockchip_pll_clock px30_pmu_pll_clks[] __initdata = {
0200     [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll",  mux_pll_p, 0, PX30_PMU_PLL_CON(0),
0201              PX30_PMU_MODE, 0, 3, 0, px30_pll_rates),
0202 };
0203
0204 #define MFLAGS CLK_MUX_HIWORD_MASK
0205 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
0206 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
0207
0208 static struct rockchip_clk_branch px30_pdm_fracmux __initdata =
0209     MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
0210             PX30_CLKSEL_CON(26), 15, 1, MFLAGS);
0211
0212 static struct rockchip_clk_branch px30_i2s0_tx_fracmux __initdata =
0213     MUX(0, "clk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
0214             PX30_CLKSEL_CON(28), 10, 2, MFLAGS);
0215
0216 static struct rockchip_clk_branch px30_i2s0_rx_fracmux __initdata =
0217     MUX(0, "clk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
0218             PX30_CLKSEL_CON(58), 10, 2, MFLAGS);
0219
0220 static struct rockchip_clk_branch px30_i2s1_fracmux __initdata =
0221     MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
0222             PX30_CLKSEL_CON(30), 10, 2, MFLAGS);
0223
0224 static struct rockchip_clk_branch px30_i2s2_fracmux __initdata =
0225     MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
0226             PX30_CLKSEL_CON(32), 10, 2, MFLAGS);
0227
0228 static struct rockchip_clk_branch px30_uart1_fracmux __initdata =
0229     MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
0230             PX30_CLKSEL_CON(35), 14, 2, MFLAGS);
0231
0232 static struct rockchip_clk_branch px30_uart2_fracmux __initdata =
0233     MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
0234             PX30_CLKSEL_CON(38), 14, 2, MFLAGS);
0235
0236 static struct rockchip_clk_branch px30_uart3_fracmux __initdata =
0237     MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
0238             PX30_CLKSEL_CON(41), 14, 2, MFLAGS);
0239
0240 static struct rockchip_clk_branch px30_uart4_fracmux __initdata =
0241     MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
0242             PX30_CLKSEL_CON(44), 14, 2, MFLAGS);
0243
0244 static struct rockchip_clk_branch px30_uart5_fracmux __initdata =
0245     MUX(0, "clk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
0246             PX30_CLKSEL_CON(47), 14, 2, MFLAGS);
0247
0248 static struct rockchip_clk_branch px30_dclk_vopb_fracmux __initdata =
0249     MUX(0, "dclk_vopb_mux", mux_dclk_vopb_p, CLK_SET_RATE_PARENT,
0250             PX30_CLKSEL_CON(5), 14, 2, MFLAGS);
0251
0252 static struct rockchip_clk_branch px30_dclk_vopl_fracmux __initdata =
0253     MUX(0, "dclk_vopl_mux", mux_dclk_vopl_p, CLK_SET_RATE_PARENT,
0254             PX30_CLKSEL_CON(8), 14, 2, MFLAGS);
0255
0256 static struct rockchip_clk_branch px30_rtc32k_pmu_fracmux __initdata =
0257     MUX(SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT,
0258             PX30_PMU_CLKSEL_CON(0), 14, 2, MFLAGS);
0259
0260 static struct rockchip_clk_branch px30_uart0_pmu_fracmux __initdata =
0261     MUX(0, "clk_uart0_pmu_mux", mux_uart0_pmu_p, CLK_SET_RATE_PARENT,
0262             PX30_PMU_CLKSEL_CON(4), 14, 2, MFLAGS);
0263
0264 static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
0265     /*
0266      * Clock-Architecture Diagram 1
0267      */
0268
0269     MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
0270             PX30_MODE_CON, 8, 2, MFLAGS),
0271     FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
0272
0273     /*
0274      * Clock-Architecture Diagram 3
0275      */
0276
0277     /* PD_CORE */
0278     GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
0279             PX30_CLKGATE_CON(0), 0, GFLAGS),
0280     GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
0281             PX30_CLKGATE_CON(0), 0, GFLAGS),
0282     COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
0283             PX30_CLKSEL_CON(0), 8, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
0284             PX30_CLKGATE_CON(0), 2, GFLAGS),
0285     COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
0286             PX30_CLKSEL_CON(0), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
0287             PX30_CLKGATE_CON(0), 1, GFLAGS),
0288     GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
0289             PX30_CLKGATE_CON(0), 4, GFLAGS),
0290     GATE(0, "aclk_core_prf", "aclk_core", CLK_IGNORE_UNUSED,
0291             PX30_CLKGATE_CON(17), 5, GFLAGS),
0292     GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
0293             PX30_CLKGATE_CON(0), 5, GFLAGS),
0294     GATE(0, "pclk_core_dbg", "pclk_dbg", CLK_IGNORE_UNUSED,
0295             PX30_CLKGATE_CON(0), 6, GFLAGS),
0296     GATE(0, "pclk_core_grf", "pclk_dbg", CLK_IGNORE_UNUSED,
0297             PX30_CLKGATE_CON(17), 6, GFLAGS),
0298
0299     GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
0300             PX30_CLKGATE_CON(0), 3, GFLAGS),
0301     GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0,
0302             PX30_CLKGATE_CON(17), 4, GFLAGS),
0303
0304     /* PD_GPU */
0305     COMPOSITE_NODIV(0, "clk_gpu_src", mux_4plls_p, 0,
0306             PX30_CLKSEL_CON(1), 6, 2, MFLAGS,
0307             PX30_CLKGATE_CON(0), 8, GFLAGS),
0308     COMPOSITE_NOMUX(0, "clk_gpu_div", "clk_gpu_src", 0,
0309             PX30_CLKSEL_CON(1), 0, 4, DFLAGS,
0310             PX30_CLKGATE_CON(0), 12, GFLAGS),
0311     COMPOSITE_NOMUX_HALFDIV(0, "clk_gpu_np5", "clk_gpu_src", 0,
0312             PX30_CLKSEL_CON(1), 8, 4, DFLAGS,
0313             PX30_CLKGATE_CON(0), 9, GFLAGS),
0314     COMPOSITE_NODIV(SCLK_GPU, "clk_gpu", mux_gpu_p, CLK_SET_RATE_PARENT,
0315             PX30_CLKSEL_CON(1), 15, 1, MFLAGS,
0316             PX30_CLKGATE_CON(0), 10, GFLAGS),
0317     COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu", CLK_IGNORE_UNUSED,
0318             PX30_CLKSEL_CON(1), 13, 2, DFLAGS,
0319             PX30_CLKGATE_CON(17), 10, GFLAGS),
0320     GATE(0, "aclk_gpu_niu", "aclk_gpu", CLK_IGNORE_UNUSED,
0321             PX30_CLKGATE_CON(0), 11, GFLAGS),
0322     GATE(0, "aclk_gpu_prf", "aclk_gpu", CLK_IGNORE_UNUSED,
0323             PX30_CLKGATE_CON(17), 8, GFLAGS),
0324     GATE(0, "pclk_gpu_grf", "aclk_gpu", CLK_IGNORE_UNUSED,
0325             PX30_CLKGATE_CON(17), 9, GFLAGS),
0326
0327     /*
0328      * Clock-Architecture Diagram 4
0329      */
0330
0331     /* PD_DDR */
0332     GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
0333             PX30_CLKGATE_CON(0), 7, GFLAGS),
0334     GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
0335             PX30_CLKGATE_CON(0), 13, GFLAGS),
0336     COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, CLK_IGNORE_UNUSED,
0337             PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
0338     COMPOSITE_NOGATE(0, "clk_ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
0339             PX30_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 3, DFLAGS),
0340     FACTOR_GATE(0, "clk_ddrphy1x", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
0341             PX30_CLKGATE_CON(0), 14, GFLAGS),
0342     FACTOR_GATE(0, "clk_stdby_2wrap", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
0343             PX30_CLKGATE_CON(1), 0, GFLAGS),
0344     COMPOSITE_NODIV(0, "clk_ddrstdby", mux_ddrstdby_p, CLK_IGNORE_UNUSED,
0345             PX30_CLKSEL_CON(2), 4, 1, MFLAGS,
0346             PX30_CLKGATE_CON(1), 13, GFLAGS),
0347     GATE(0, "aclk_split", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
0348             PX30_CLKGATE_CON(1), 15, GFLAGS),
0349     GATE(0, "clk_msch", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
0350             PX30_CLKGATE_CON(1), 8, GFLAGS),
0351     GATE(0, "aclk_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
0352             PX30_CLKGATE_CON(1), 5, GFLAGS),
0353     GATE(0, "clk_core_ddrc", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
0354             PX30_CLKGATE_CON(1), 6, GFLAGS),
0355     GATE(0, "aclk_cmd_buff", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
0356             PX30_CLKGATE_CON(1), 6, GFLAGS),
0357     GATE(0, "clk_ddrmon", "clk_ddrphy1x", CLK_IGNORE_UNUSED,
0358             PX30_CLKGATE_CON(1), 11, GFLAGS),
0359
0360     GATE(0, "clk_ddrmon_timer", "xin24m", CLK_IGNORE_UNUSED,
0361             PX30_CLKGATE_CON(0), 15, GFLAGS),
0362
0363     COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IGNORE_UNUSED,
0364             PX30_CLKSEL_CON(2), 8, 5, DFLAGS,
0365             PX30_CLKGATE_CON(1), 1, GFLAGS),
0366     GATE(0, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED,
0367             PX30_CLKGATE_CON(1), 10, GFLAGS),
0368     GATE(0, "pclk_ddrc", "pclk_ddr", CLK_IGNORE_UNUSED,
0369             PX30_CLKGATE_CON(1), 7, GFLAGS),
0370     GATE(0, "pclk_msch", "pclk_ddr", CLK_IGNORE_UNUSED,
0371             PX30_CLKGATE_CON(1), 9, GFLAGS),
0372     GATE(0, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED,
0373             PX30_CLKGATE_CON(1), 12, GFLAGS),
0374     GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
0375             PX30_CLKGATE_CON(1), 14, GFLAGS),
0376     GATE(0, "pclk_cmdbuff", "pclk_ddr", CLK_IGNORE_UNUSED,
0377             PX30_CLKGATE_CON(1), 3, GFLAGS),
0378
0379     /*
0380      * Clock-Architecture Diagram 5
0381      */
0382
0383     /* PD_VI */
0384     COMPOSITE(ACLK_VI_PRE, "aclk_vi_pre", mux_gpll_cpll_npll_p, 0,
0385             PX30_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
0386             PX30_CLKGATE_CON(4), 8, GFLAGS),
0387     COMPOSITE_NOMUX(HCLK_VI_PRE, "hclk_vi_pre", "aclk_vi_pre", 0,
0388             PX30_CLKSEL_CON(11), 8, 4, DFLAGS,
0389             PX30_CLKGATE_CON(4), 12, GFLAGS),
0390     COMPOSITE(SCLK_ISP, "clk_isp", mux_gpll_cpll_npll_p, 0,
0391             PX30_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
0392             PX30_CLKGATE_CON(4), 9, GFLAGS),
0393     COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_cif_out_p, 0,
0394             PX30_CLKSEL_CON(13), 6, 2, MFLAGS, 0, 6, DFLAGS,
0395             PX30_CLKGATE_CON(4), 11, GFLAGS),
0396     GATE(PCLK_ISP, "pclkin_isp", "ext_pclkin", 0,
0397             PX30_CLKGATE_CON(4), 13, GFLAGS),
0398     GATE(PCLK_CIF, "pclkin_cif", "ext_pclkin", 0,
0399             PX30_CLKGATE_CON(4), 14, GFLAGS),
0400
0401     /*
0402      * Clock-Architecture Diagram 6
0403      */
0404
0405     /* PD_VO */
0406     COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", mux_gpll_cpll_npll_p, 0,
0407             PX30_CLKSEL_CON(3), 6, 2, MFLAGS, 0, 5, DFLAGS,
0408             PX30_CLKGATE_CON(2), 0, GFLAGS),
0409     COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo_pre", 0,
0410             PX30_CLKSEL_CON(3), 8, 4, DFLAGS,
0411             PX30_CLKGATE_CON(2), 12, GFLAGS),
0412     COMPOSITE_NOMUX(PCLK_VO_PRE, "pclk_vo_pre", "aclk_vo_pre", 0,
0413             PX30_CLKSEL_CON(3), 12, 4, DFLAGS,
0414             PX30_CLKGATE_CON(2), 13, GFLAGS),
0415     COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_npll_p, 0,
0416             PX30_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS,
0417             PX30_CLKGATE_CON(2), 1, GFLAGS),
0418
0419     COMPOSITE(SCLK_VOPB_PWM, "clk_vopb_pwm", mux_gpll_xin24m_p, 0,
0420             PX30_CLKSEL_CON(7), 7, 1, MFLAGS, 0, 7, DFLAGS,
0421             PX30_CLKGATE_CON(2), 5, GFLAGS),
0422     COMPOSITE(0, "dclk_vopb_src", mux_cpll_npll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0423             PX30_CLKSEL_CON(5), 11, 1, MFLAGS, 0, 8, DFLAGS,
0424             PX30_CLKGATE_CON(2), 2, GFLAGS),
0425     COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src", CLK_SET_RATE_PARENT,
0426             PX30_CLKSEL_CON(6), 0,
0427             PX30_CLKGATE_CON(2), 3, GFLAGS,
0428             &px30_dclk_vopb_fracmux),
0429     GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT,
0430             PX30_CLKGATE_CON(2), 4, GFLAGS),
0431     COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0,
0432             PX30_CLKSEL_CON(8), 11, 1, MFLAGS, 0, 8, DFLAGS,
0433             PX30_CLKGATE_CON(2), 6, GFLAGS),
0434     COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT,
0435             PX30_CLKSEL_CON(9), 0,
0436             PX30_CLKGATE_CON(2), 7, GFLAGS,
0437             &px30_dclk_vopl_fracmux),
0438     GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT,
0439             PX30_CLKGATE_CON(2), 8, GFLAGS),
0440
0441     /* PD_VPU */
0442     COMPOSITE(0, "aclk_vpu_pre", mux_gpll_cpll_npll_p, 0,
0443             PX30_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
0444             PX30_CLKGATE_CON(4), 0, GFLAGS),
0445     COMPOSITE_NOMUX(0, "hclk_vpu_pre", "aclk_vpu_pre", 0,
0446             PX30_CLKSEL_CON(10), 8, 4, DFLAGS,
0447             PX30_CLKGATE_CON(4), 2, GFLAGS),
0448     COMPOSITE(SCLK_CORE_VPU, "sclk_core_vpu", mux_gpll_cpll_npll_p, 0,
0449             PX30_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 5, DFLAGS,
0450             PX30_CLKGATE_CON(4), 1, GFLAGS),
0451
0452     /*
0453      * Clock-Architecture Diagram 7
0454      */
0455
0456     COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_gpll_cpll_p, 0,
0457             PX30_CLKSEL_CON(14), 15, 1, MFLAGS,
0458             PX30_CLKGATE_CON(5), 7, GFLAGS),
0459     COMPOSITE_NOMUX(ACLK_PERI_PRE, "aclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED,
0460             PX30_CLKSEL_CON(14), 0, 5, DFLAGS,
0461             PX30_CLKGATE_CON(5), 8, GFLAGS),
0462     DIV(HCLK_PERI_PRE, "hclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED,
0463             PX30_CLKSEL_CON(14), 8, 5, DFLAGS),
0464
0465     /* PD_MMC_NAND */
0466     GATE(HCLK_MMC_NAND, "hclk_mmc_nand", "hclk_peri_pre", 0,
0467             PX30_CLKGATE_CON(6), 0, GFLAGS),
0468     COMPOSITE(SCLK_NANDC_DIV, "clk_nandc_div", mux_gpll_cpll_npll_p, 0,
0469             PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
0470             PX30_CLKGATE_CON(5), 11, GFLAGS),
0471     COMPOSITE(SCLK_NANDC_DIV50, "clk_nandc_div50", mux_gpll_cpll_npll_p, 0,
0472             PX30_CLKSEL_CON(15), 6, 2, MFLAGS, 8, 5, DFLAGS,
0473             PX30_CLKGATE_CON(5), 12, GFLAGS),
0474     COMPOSITE_NODIV(SCLK_NANDC, "clk_nandc", mux_nandc_p,
0475             CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0476             PX30_CLKSEL_CON(15), 15, 1, MFLAGS,
0477             PX30_CLKGATE_CON(5), 13, GFLAGS),
0478
0479     COMPOSITE(SCLK_SDIO_DIV, "clk_sdio_div", mux_gpll_cpll_npll_xin24m_p, 0,
0480             PX30_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS,
0481             PX30_CLKGATE_CON(6), 1, GFLAGS),
0482     COMPOSITE_DIV_OFFSET(SCLK_SDIO_DIV50, "clk_sdio_div50",
0483             mux_gpll_cpll_npll_xin24m_p, 0,
0484             PX30_CLKSEL_CON(18), 14, 2, MFLAGS,
0485             PX30_CLKSEL_CON(19), 0, 8, DFLAGS,
0486             PX30_CLKGATE_CON(6), 2, GFLAGS),
0487     COMPOSITE_NODIV(SCLK_SDIO, "clk_sdio", mux_sdio_p,
0488             CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0489             PX30_CLKSEL_CON(19), 15, 1, MFLAGS,
0490             PX30_CLKGATE_CON(6), 3, GFLAGS),
0491
0492     COMPOSITE(SCLK_EMMC_DIV, "clk_emmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
0493             PX30_CLKSEL_CON(20), 14, 2, MFLAGS, 0, 8, DFLAGS,
0494             PX30_CLKGATE_CON(6), 4, GFLAGS),
0495     COMPOSITE_DIV_OFFSET(SCLK_EMMC_DIV50, "clk_emmc_div50", mux_gpll_cpll_npll_xin24m_p, 0,
0496             PX30_CLKSEL_CON(20), 14, 2, MFLAGS,
0497             PX30_CLKSEL_CON(21), 0, 8, DFLAGS,
0498             PX30_CLKGATE_CON(6), 5, GFLAGS),
0499     COMPOSITE_NODIV(SCLK_EMMC, "clk_emmc", mux_emmc_p,
0500             CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0501             PX30_CLKSEL_CON(21), 15, 1, MFLAGS,
0502             PX30_CLKGATE_CON(6), 6, GFLAGS),
0503
0504     COMPOSITE(SCLK_SFC, "clk_sfc", mux_gpll_cpll_p, 0,
0505             PX30_CLKSEL_CON(22), 7, 1, MFLAGS, 0, 7, DFLAGS,
0506             PX30_CLKGATE_CON(6), 7, GFLAGS),
0507
0508     MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
0509         PX30_SDMMC_CON0, 1),
0510     MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
0511         PX30_SDMMC_CON1, 1),
0512
0513     MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
0514         PX30_SDIO_CON0, 1),
0515     MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
0516         PX30_SDIO_CON1, 1),
0517
0518     MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
0519         PX30_EMMC_CON0, 1),
0520     MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
0521         PX30_EMMC_CON1, 1),
0522
0523     /* PD_SDCARD */
0524     GATE(0, "hclk_sdmmc_pre", "hclk_peri_pre", 0,
0525             PX30_CLKGATE_CON(6), 12, GFLAGS),
0526     COMPOSITE(SCLK_SDMMC_DIV, "clk_sdmmc_div", mux_gpll_cpll_npll_xin24m_p, 0,
0527             PX30_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS,
0528             PX30_CLKGATE_CON(6), 13, GFLAGS),
0529     COMPOSITE_DIV_OFFSET(SCLK_SDMMC_DIV50, "clk_sdmmc_div50", mux_gpll_cpll_npll_xin24m_p, 0,
0530             PX30_CLKSEL_CON(16), 14, 2, MFLAGS,
0531             PX30_CLKSEL_CON(17), 0, 8, DFLAGS,
0532             PX30_CLKGATE_CON(6), 14, GFLAGS),
0533     COMPOSITE_NODIV(SCLK_SDMMC, "clk_sdmmc", mux_sdmmc_p,
0534             CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0535             PX30_CLKSEL_CON(17), 15, 1, MFLAGS,
0536             PX30_CLKGATE_CON(6), 15, GFLAGS),
0537
0538     /* PD_USB */
0539     GATE(HCLK_USB, "hclk_usb", "hclk_peri_pre", 0,
0540             PX30_CLKGATE_CON(7), 2, GFLAGS),
0541     GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k_pmu", 0,
0542             PX30_CLKGATE_CON(7), 3, GFLAGS),
0543
0544     /* PD_GMAC */
0545     COMPOSITE(SCLK_GMAC_SRC, "clk_gmac_src", mux_gpll_cpll_npll_p, 0,
0546             PX30_CLKSEL_CON(22), 14, 2, MFLAGS, 8, 5, DFLAGS,
0547             PX30_CLKGATE_CON(7), 11, GFLAGS),
0548     MUX(SCLK_GMAC, "clk_gmac", mux_gmac_p,  CLK_SET_RATE_PARENT,
0549             PX30_CLKSEL_CON(23), 6, 1, MFLAGS),
0550     GATE(SCLK_MAC_REF, "clk_mac_ref", "clk_gmac", 0,
0551             PX30_CLKGATE_CON(7), 15, GFLAGS),
0552     GATE(SCLK_GMAC_RX_TX, "clk_gmac_rx_tx", "clk_gmac", 0,
0553             PX30_CLKGATE_CON(7), 13, GFLAGS),
0554     FACTOR(0, "clk_gmac_rx_tx_div2", "clk_gmac_rx_tx", 0, 1, 2),
0555     FACTOR(0, "clk_gmac_rx_tx_div20", "clk_gmac_rx_tx", 0, 1, 20),
0556     MUX(SCLK_GMAC_RMII, "clk_gmac_rmii_sel", mux_gmac_rmii_sel_p,  CLK_SET_RATE_PARENT,
0557             PX30_CLKSEL_CON(23), 7, 1, MFLAGS),
0558
0559     GATE(0, "aclk_gmac_pre", "aclk_peri_pre", 0,
0560             PX30_CLKGATE_CON(7), 10, GFLAGS),
0561     COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
0562             PX30_CLKSEL_CON(23), 0, 4, DFLAGS,
0563             PX30_CLKGATE_CON(7), 12, GFLAGS),
0564
0565     COMPOSITE(SCLK_MAC_OUT, "clk_mac_out", mux_gpll_cpll_npll_p, 0,
0566             PX30_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
0567             PX30_CLKGATE_CON(8), 5, GFLAGS),
0568
0569     /*
0570      * Clock-Architecture Diagram 8
0571      */
0572
0573     /* PD_BUS */
0574     COMPOSITE_NODIV(ACLK_BUS_SRC, "aclk_bus_src", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
0575             PX30_CLKSEL_CON(23), 15, 1, MFLAGS,
0576             PX30_CLKGATE_CON(8), 6, GFLAGS),
0577     COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED,
0578             PX30_CLKSEL_CON(24), 0, 5, DFLAGS,
0579             PX30_CLKGATE_CON(8), 8, GFLAGS),
0580     COMPOSITE_NOMUX(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED,
0581             PX30_CLKSEL_CON(23), 8, 5, DFLAGS,
0582             PX30_CLKGATE_CON(8), 7, GFLAGS),
0583     COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", CLK_IGNORE_UNUSED,
0584             PX30_CLKSEL_CON(24), 8, 2, DFLAGS,
0585             PX30_CLKGATE_CON(8), 9, GFLAGS),
0586     GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
0587             PX30_CLKGATE_CON(8), 10, GFLAGS),
0588
0589     COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_npll_p, 0,
0590             PX30_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 7, DFLAGS,
0591             PX30_CLKGATE_CON(9), 9, GFLAGS),
0592     COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
0593             PX30_CLKSEL_CON(27), 0,
0594             PX30_CLKGATE_CON(9), 10, GFLAGS,
0595             &px30_pdm_fracmux),
0596     GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT,
0597             PX30_CLKGATE_CON(9), 11, GFLAGS),
0598
0599     COMPOSITE(0, "clk_i2s0_tx_src", mux_gpll_npll_p, 0,
0600             PX30_CLKSEL_CON(28), 8, 1, MFLAGS, 0, 7, DFLAGS,
0601             PX30_CLKGATE_CON(9), 12, GFLAGS),
0602     COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src", CLK_SET_RATE_PARENT,
0603             PX30_CLKSEL_CON(29), 0,
0604             PX30_CLKGATE_CON(9), 13, GFLAGS,
0605             &px30_i2s0_tx_fracmux),
0606     COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT,
0607             PX30_CLKSEL_CON(28), 12, 1, MFLAGS,
0608             PX30_CLKGATE_CON(9), 14, GFLAGS),
0609     COMPOSITE_NODIV(0, "clk_i2s0_tx_out_pre", mux_i2s0_tx_out_p, 0,
0610             PX30_CLKSEL_CON(28), 14, 2, MFLAGS,
0611             PX30_CLKGATE_CON(9), 15, GFLAGS),
0612     GATE(SCLK_I2S0_TX_OUT, "clk_i2s0_tx_out", "clk_i2s0_tx_out_pre", CLK_SET_RATE_PARENT,
0613             PX30_CLKGATE_CON(10), 8, CLK_GATE_HIWORD_MASK),
0614
0615     COMPOSITE(0, "clk_i2s0_rx_src", mux_gpll_npll_p, 0,
0616             PX30_CLKSEL_CON(58), 8, 1, MFLAGS, 0, 7, DFLAGS,
0617             PX30_CLKGATE_CON(17), 0, GFLAGS),
0618     COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src", CLK_SET_RATE_PARENT,
0619             PX30_CLKSEL_CON(59), 0,
0620             PX30_CLKGATE_CON(17), 1, GFLAGS,
0621             &px30_i2s0_rx_fracmux),
0622     COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p, CLK_SET_RATE_PARENT,
0623             PX30_CLKSEL_CON(58), 12, 1, MFLAGS,
0624             PX30_CLKGATE_CON(17), 2, GFLAGS),
0625     COMPOSITE_NODIV(0, "clk_i2s0_rx_out_pre", mux_i2s0_rx_out_p, 0,
0626             PX30_CLKSEL_CON(58), 14, 2, MFLAGS,
0627             PX30_CLKGATE_CON(17), 3, GFLAGS),
0628     GATE(SCLK_I2S0_RX_OUT, "clk_i2s0_rx_out", "clk_i2s0_rx_out_pre", CLK_SET_RATE_PARENT,
0629             PX30_CLKGATE_CON(10), 11, CLK_GATE_HIWORD_MASK),
0630
0631     COMPOSITE(0, "clk_i2s1_src", mux_gpll_npll_p, 0,
0632             PX30_CLKSEL_CON(30), 8, 1, MFLAGS, 0, 7, DFLAGS,
0633             PX30_CLKGATE_CON(10), 0, GFLAGS),
0634     COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_src", CLK_SET_RATE_PARENT,
0635             PX30_CLKSEL_CON(31), 0,
0636             PX30_CLKGATE_CON(10), 1, GFLAGS,
0637             &px30_i2s1_fracmux),
0638     GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
0639             PX30_CLKGATE_CON(10), 2, GFLAGS),
0640     COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, 0,
0641             PX30_CLKSEL_CON(30), 15, 1, MFLAGS,
0642             PX30_CLKGATE_CON(10), 3, GFLAGS),
0643     GATE(SCLK_I2S1_OUT, "clk_i2s1_out", "clk_i2s1_out_pre", CLK_SET_RATE_PARENT,
0644             PX30_CLKGATE_CON(10), 9, CLK_GATE_HIWORD_MASK),
0645
0646     COMPOSITE(0, "clk_i2s2_src", mux_gpll_npll_p, 0,
0647             PX30_CLKSEL_CON(32), 8, 1, MFLAGS, 0, 7, DFLAGS,
0648             PX30_CLKGATE_CON(10), 4, GFLAGS),
0649     COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_src", CLK_SET_RATE_PARENT,
0650             PX30_CLKSEL_CON(33), 0,
0651             PX30_CLKGATE_CON(10), 5, GFLAGS,
0652             &px30_i2s2_fracmux),
0653     GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
0654             PX30_CLKGATE_CON(10), 6, GFLAGS),
0655     COMPOSITE_NODIV(0, "clk_i2s2_out_pre", mux_i2s2_out_p, 0,
0656             PX30_CLKSEL_CON(32), 15, 1, MFLAGS,
0657             PX30_CLKGATE_CON(10), 7, GFLAGS),
0658     GATE(SCLK_I2S2_OUT, "clk_i2s2_out", "clk_i2s2_out_pre", CLK_SET_RATE_PARENT,
0659             PX30_CLKGATE_CON(10), 10, CLK_GATE_HIWORD_MASK),
0660
0661     COMPOSITE(SCLK_UART1_SRC, "clk_uart1_src", mux_uart_src_p, CLK_SET_RATE_NO_REPARENT,
0662             PX30_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 5, DFLAGS,
0663             PX30_CLKGATE_CON(10), 12, GFLAGS),
0664     COMPOSITE_NOMUX_HALFDIV(0, "clk_uart1_np5", "clk_uart1_src", 0,
0665             PX30_CLKSEL_CON(35), 0, 5, DFLAGS,
0666             PX30_CLKGATE_CON(10), 13, GFLAGS),
0667     COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
0668             PX30_CLKSEL_CON(36), 0,
0669             PX30_CLKGATE_CON(10), 14, GFLAGS,
0670             &px30_uart1_fracmux),
0671     GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT,
0672             PX30_CLKGATE_CON(10), 15, GFLAGS),
0673
0674     COMPOSITE(SCLK_UART2_SRC, "clk_uart2_src", mux_uart_src_p, 0,
0675             PX30_CLKSEL_CON(37), 14, 2, MFLAGS, 0, 5, DFLAGS,
0676             PX30_CLKGATE_CON(11), 0, GFLAGS),
0677     COMPOSITE_NOMUX_HALFDIV(0, "clk_uart2_np5", "clk_uart2_src", 0,
0678             PX30_CLKSEL_CON(38), 0, 5, DFLAGS,
0679             PX30_CLKGATE_CON(11), 1, GFLAGS),
0680     COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
0681             PX30_CLKSEL_CON(39), 0,
0682             PX30_CLKGATE_CON(11), 2, GFLAGS,
0683             &px30_uart2_fracmux),
0684     GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
0685             PX30_CLKGATE_CON(11), 3, GFLAGS),
0686
0687     COMPOSITE(0, "clk_uart3_src", mux_uart_src_p, 0,
0688             PX30_CLKSEL_CON(40), 14, 2, MFLAGS, 0, 5, DFLAGS,
0689             PX30_CLKGATE_CON(11), 4, GFLAGS),
0690     COMPOSITE_NOMUX_HALFDIV(0, "clk_uart3_np5", "clk_uart3_src", 0,
0691             PX30_CLKSEL_CON(41), 0, 5, DFLAGS,
0692             PX30_CLKGATE_CON(11), 5, GFLAGS),
0693     COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
0694             PX30_CLKSEL_CON(42), 0,
0695             PX30_CLKGATE_CON(11), 6, GFLAGS,
0696             &px30_uart3_fracmux),
0697     GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT,
0698             PX30_CLKGATE_CON(11), 7, GFLAGS),
0699
0700     COMPOSITE(0, "clk_uart4_src", mux_uart_src_p, 0,
0701             PX30_CLKSEL_CON(43), 14, 2, MFLAGS, 0, 5, DFLAGS,
0702             PX30_CLKGATE_CON(11), 8, GFLAGS),
0703     COMPOSITE_NOMUX_HALFDIV(0, "clk_uart4_np5", "clk_uart4_src", 0,
0704             PX30_CLKSEL_CON(44), 0, 5, DFLAGS,
0705             PX30_CLKGATE_CON(11), 9, GFLAGS),
0706     COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
0707             PX30_CLKSEL_CON(45), 0,
0708             PX30_CLKGATE_CON(11), 10, GFLAGS,
0709             &px30_uart4_fracmux),
0710     GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT,
0711             PX30_CLKGATE_CON(11), 11, GFLAGS),
0712
0713     COMPOSITE(0, "clk_uart5_src", mux_uart_src_p, 0,
0714             PX30_CLKSEL_CON(46), 14, 2, MFLAGS, 0, 5, DFLAGS,
0715             PX30_CLKGATE_CON(11), 12, GFLAGS),
0716     COMPOSITE_NOMUX_HALFDIV(0, "clk_uart5_np5", "clk_uart5_src", 0,
0717             PX30_CLKSEL_CON(47), 0, 5, DFLAGS,
0718             PX30_CLKGATE_CON(11), 13, GFLAGS),
0719     COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
0720             PX30_CLKSEL_CON(48), 0,
0721             PX30_CLKGATE_CON(11), 14, GFLAGS,
0722             &px30_uart5_fracmux),
0723     GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT,
0724             PX30_CLKGATE_CON(11), 15, GFLAGS),
0725
0726     COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_gpll_xin24m_p, 0,
0727             PX30_CLKSEL_CON(49), 7, 1, MFLAGS, 0, 7, DFLAGS,
0728             PX30_CLKGATE_CON(12), 0, GFLAGS),
0729     COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_gpll_xin24m_p, 0,
0730             PX30_CLKSEL_CON(49), 15, 1, MFLAGS, 8, 7, DFLAGS,
0731             PX30_CLKGATE_CON(12), 1, GFLAGS),
0732     COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_gpll_xin24m_p, 0,
0733             PX30_CLKSEL_CON(50), 7, 1, MFLAGS, 0, 7, DFLAGS,
0734             PX30_CLKGATE_CON(12), 2, GFLAGS),
0735     COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_gpll_xin24m_p, 0,
0736             PX30_CLKSEL_CON(50), 15, 1, MFLAGS, 8, 7, DFLAGS,
0737             PX30_CLKGATE_CON(12), 3, GFLAGS),
0738     COMPOSITE(SCLK_PWM0, "clk_pwm0", mux_gpll_xin24m_p, 0,
0739             PX30_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 7, DFLAGS,
0740             PX30_CLKGATE_CON(12), 5, GFLAGS),
0741     COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_gpll_xin24m_p, 0,
0742             PX30_CLKSEL_CON(52), 15, 1, MFLAGS, 8, 7, DFLAGS,
0743             PX30_CLKGATE_CON(12), 6, GFLAGS),
0744     COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
0745             PX30_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 7, DFLAGS,
0746             PX30_CLKGATE_CON(12), 7, GFLAGS),
0747     COMPOSITE(SCLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
0748             PX30_CLKSEL_CON(53), 15, 1, MFLAGS, 8, 7, DFLAGS,
0749             PX30_CLKGATE_CON(12), 8, GFLAGS),
0750
0751     GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
0752             PX30_CLKGATE_CON(13), 0, GFLAGS),
0753     GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
0754             PX30_CLKGATE_CON(13), 1, GFLAGS),
0755     GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
0756             PX30_CLKGATE_CON(13), 2, GFLAGS),
0757     GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
0758             PX30_CLKGATE_CON(13), 3, GFLAGS),
0759     GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
0760             PX30_CLKGATE_CON(13), 4, GFLAGS),
0761     GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
0762             PX30_CLKGATE_CON(13), 5, GFLAGS),
0763
0764     COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "xin24m", 0,
0765             PX30_CLKSEL_CON(54), 0, 11, DFLAGS,
0766             PX30_CLKGATE_CON(12), 9, GFLAGS),
0767     COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
0768             PX30_CLKSEL_CON(55), 0, 11, DFLAGS,
0769             PX30_CLKGATE_CON(12), 10, GFLAGS),
0770     COMPOSITE_NOMUX(SCLK_OTP, "clk_otp", "xin24m", 0,
0771             PX30_CLKSEL_CON(56), 0, 3, DFLAGS,
0772             PX30_CLKGATE_CON(12), 11, GFLAGS),
0773     COMPOSITE_NOMUX(SCLK_OTP_USR, "clk_otp_usr", "clk_otp", 0,
0774             PX30_CLKSEL_CON(56), 4, 2, DFLAGS,
0775             PX30_CLKGATE_CON(13), 6, GFLAGS),
0776
0777     GATE(0, "clk_cpu_boost", "xin24m", CLK_IGNORE_UNUSED,
0778             PX30_CLKGATE_CON(12), 12, GFLAGS),
0779
0780     /* PD_CRYPTO */
0781     GATE(0, "aclk_crypto_pre", "aclk_bus_pre", 0,
0782             PX30_CLKGATE_CON(8), 12, GFLAGS),
0783     GATE(0, "hclk_crypto_pre", "hclk_bus_pre", 0,
0784             PX30_CLKGATE_CON(8), 13, GFLAGS),
0785     COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_npll_p, 0,
0786             PX30_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
0787             PX30_CLKGATE_CON(8), 14, GFLAGS),
0788     COMPOSITE(SCLK_CRYPTO_APK, "clk_crypto_apk", mux_gpll_cpll_npll_p, 0,
0789             PX30_CLKSEL_CON(25), 14, 2, MFLAGS, 8, 5, DFLAGS,
0790             PX30_CLKGATE_CON(8), 15, GFLAGS),
0791
0792     /*
0793      * Clock-Architecture Diagram 9
0794      */
0795
0796     /* PD_BUS_TOP */
0797     GATE(0, "pclk_top_niu", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 0, GFLAGS),
0798     GATE(0, "pclk_top_cru", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 1, GFLAGS),
0799     GATE(PCLK_OTP_PHY, "pclk_otp_phy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 2, GFLAGS),
0800     GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 3, GFLAGS),
0801     GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 4, GFLAGS),
0802     GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 5, GFLAGS),
0803     GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 6, GFLAGS),
0804     GATE(0, "pclk_cpu_hoost", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 7, GFLAGS),
0805
0806     /* PD_VI */
0807     GATE(0, "aclk_vi_niu", "aclk_vi_pre", 0, PX30_CLKGATE_CON(4), 15, GFLAGS),
0808     GATE(ACLK_CIF, "aclk_cif", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 1, GFLAGS),
0809     GATE(ACLK_ISP, "aclk_isp", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 3, GFLAGS),
0810     GATE(0, "hclk_vi_niu", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 0, GFLAGS),
0811     GATE(HCLK_CIF, "hclk_cif", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 2, GFLAGS),
0812     GATE(HCLK_ISP, "hclk_isp", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 4, GFLAGS),
0813
0814     /* PD_VO */
0815     GATE(0, "aclk_vo_niu", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 0, GFLAGS),
0816     GATE(ACLK_VOPB, "aclk_vopb", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 3, GFLAGS),
0817     GATE(ACLK_RGA, "aclk_rga", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 7, GFLAGS),
0818     GATE(ACLK_VOPL, "aclk_vopl", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 5, GFLAGS),
0819
0820     GATE(0, "hclk_vo_niu", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 1, GFLAGS),
0821     GATE(HCLK_VOPB, "hclk_vopb", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 4, GFLAGS),
0822     GATE(HCLK_RGA, "hclk_rga", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 8, GFLAGS),
0823     GATE(HCLK_VOPL, "hclk_vopl", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 6, GFLAGS),
0824
0825     GATE(0, "pclk_vo_niu", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 2, GFLAGS),
0826     GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 9, GFLAGS),
0827
0828     /* PD_BUS */
0829     GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 8, GFLAGS),
0830     GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 11, GFLAGS),
0831     GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS),
0832     GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS),
0833
0834     /* aclk_dmac is controlled by sgrf_soc_con1[11]. */
0835     SGRF_GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre"),
0836
0837     GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS),
0838     GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS),
0839     GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 1, GFLAGS),
0840     GATE(HCLK_I2S0, "hclk_i2s0", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 2, GFLAGS),
0841     GATE(HCLK_I2S1, "hclk_i2s1", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 3, GFLAGS),
0842     GATE(HCLK_I2S2, "hclk_i2s2", "hclk_bus_pre", 0, PX30_CLKGATE_CON(14), 4, GFLAGS),
0843
0844     GATE(0, "pclk_bus_niu", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 10, GFLAGS),
0845     GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 0, GFLAGS),
0846     GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 5, GFLAGS),
0847     GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 6, GFLAGS),
0848     GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 7, GFLAGS),
0849     GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 8, GFLAGS),
0850     GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 9, GFLAGS),
0851     GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 10, GFLAGS),
0852     GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 11, GFLAGS),
0853     GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 12, GFLAGS),
0854     GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 13, GFLAGS),
0855     GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 14, GFLAGS),
0856     GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 15, GFLAGS),
0857     GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 0, GFLAGS),
0858     GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 1, GFLAGS),
0859     GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 2, GFLAGS),
0860     GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 3, GFLAGS),
0861     GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 4, GFLAGS),
0862     GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 5, GFLAGS),
0863     GATE(PCLK_OTP_NS, "pclk_otp_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 6, GFLAGS),
0864     GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 7, GFLAGS),
0865     GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 8, GFLAGS),
0866     GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 9, GFLAGS),
0867     GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 10, GFLAGS),
0868     GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 11, GFLAGS),
0869     GATE(0, "pclk_sgrf", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(15), 12, GFLAGS),
0870
0871     /* PD_VPU */
0872     GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 7, GFLAGS),
0873     GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 6, GFLAGS),
0874     GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 5, GFLAGS),
0875     GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, PX30_CLKGATE_CON(4), 4, GFLAGS),
0876
0877     /* PD_CRYPTO */
0878     GATE(0, "hclk_crypto_niu", "hclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 3, GFLAGS),
0879     GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 5, GFLAGS),
0880     GATE(0, "aclk_crypto_niu", "aclk_crypto_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(9), 2, GFLAGS),
0881     GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_crypto_pre", 0, PX30_CLKGATE_CON(9), 4, GFLAGS),
0882
0883     /* PD_SDCARD */
0884     GATE(0, "hclk_sdmmc_niu", "hclk_sdmmc_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 0, GFLAGS),
0885     GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sdmmc_pre", 0, PX30_CLKGATE_CON(7), 1, GFLAGS),
0886
0887     /* PD_PERI */
0888     GATE(0, "aclk_peri_niu", "aclk_peri_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(5), 9, GFLAGS),
0889
0890     /* PD_MMC_NAND */
0891     GATE(HCLK_NANDC, "hclk_nandc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(5), 15, GFLAGS),
0892     GATE(0, "hclk_mmc_nand_niu", "hclk_mmc_nand", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(6), 8, GFLAGS),
0893     GATE(HCLK_SDIO, "hclk_sdio", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 9, GFLAGS),
0894     GATE(HCLK_EMMC, "hclk_emmc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 10, GFLAGS),
0895     GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 11, GFLAGS),
0896
0897     /* PD_USB */
0898     GATE(0, "hclk_usb_niu", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 4, GFLAGS),
0899     GATE(HCLK_OTG, "hclk_otg", "hclk_usb", 0, PX30_CLKGATE_CON(7), 5, GFLAGS),
0900     GATE(HCLK_HOST, "hclk_host", "hclk_usb", 0, PX30_CLKGATE_CON(7), 6, GFLAGS),
0901     GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 8, GFLAGS),
0902
0903     /* PD_GMAC */
0904     GATE(0, "aclk_gmac_niu", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
0905             PX30_CLKGATE_CON(8), 0, GFLAGS),
0906     GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
0907             PX30_CLKGATE_CON(8), 2, GFLAGS),
0908     GATE(0, "pclk_gmac_niu", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
0909             PX30_CLKGATE_CON(8), 1, GFLAGS),
0910     GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
0911             PX30_CLKGATE_CON(8), 3, GFLAGS),
0912 };
0913
0914 static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {
0915     /*
0916      * Clock-Architecture Diagram 2
0917      */
0918
0919     COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
0920             PX30_PMU_CLKSEL_CON(1), 0,
0921             PX30_PMU_CLKGATE_CON(0), 13, GFLAGS,
0922             &px30_rtc32k_pmu_fracmux),
0923
0924     COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
0925             PX30_PMU_CLKSEL_CON(0), 8, 5, DFLAGS,
0926             PX30_PMU_CLKGATE_CON(0), 12, GFLAGS),
0927
0928     COMPOSITE_NOMUX(0, "clk_wifi_pmu_src", "gpll", 0,
0929             PX30_PMU_CLKSEL_CON(2), 8, 6, DFLAGS,
0930             PX30_PMU_CLKGATE_CON(0), 14, GFLAGS),
0931     COMPOSITE_NODIV(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
0932             PX30_PMU_CLKSEL_CON(2), 15, 1, MFLAGS,
0933             PX30_PMU_CLKGATE_CON(0), 15, GFLAGS),
0934
0935     COMPOSITE(0, "clk_uart0_pmu_src", mux_uart_src_p, 0,
0936             PX30_PMU_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 5, DFLAGS,
0937             PX30_PMU_CLKGATE_CON(1), 0, GFLAGS),
0938     COMPOSITE_NOMUX_HALFDIV(0, "clk_uart0_np5", "clk_uart0_pmu_src", 0,
0939             PX30_PMU_CLKSEL_CON(4), 0, 5, DFLAGS,
0940             PX30_PMU_CLKGATE_CON(1), 1, GFLAGS),
0941     COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT,
0942             PX30_PMU_CLKSEL_CON(5), 0,
0943             PX30_PMU_CLKGATE_CON(1), 2, GFLAGS,
0944             &px30_uart0_pmu_fracmux),
0945     GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
0946             PX30_PMU_CLKGATE_CON(1), 3, GFLAGS),
0947
0948     GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
0949             PX30_PMU_CLKGATE_CON(1), 4, GFLAGS),
0950
0951     COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "gpll", 0,
0952             PX30_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
0953             PX30_PMU_CLKGATE_CON(0), 0, GFLAGS),
0954
0955     COMPOSITE_NOMUX(SCLK_REF24M_PMU, "clk_ref24m_pmu", "gpll", 0,
0956             PX30_PMU_CLKSEL_CON(2), 0, 6, DFLAGS,
0957             PX30_PMU_CLKGATE_CON(1), 8, GFLAGS),
0958     COMPOSITE_NODIV(SCLK_USBPHY_REF, "clk_usbphy_ref", mux_usbphy_ref_p, CLK_SET_RATE_PARENT,
0959             PX30_PMU_CLKSEL_CON(2), 6, 1, MFLAGS,
0960             PX30_PMU_CLKGATE_CON(1), 9, GFLAGS),
0961     COMPOSITE_NODIV(SCLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
0962             PX30_PMU_CLKSEL_CON(2), 7, 1, MFLAGS,
0963             PX30_PMU_CLKGATE_CON(1), 10, GFLAGS),
0964
0965     /*
0966      * Clock-Architecture Diagram 9
0967      */
0968
0969     /* PD_PMU */
0970     GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 1, GFLAGS),
0971     GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 2, GFLAGS),
0972     GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 3, GFLAGS),
0973     GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 4, GFLAGS),
0974     GATE(0, "pclk_pmu_mem", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 5, GFLAGS),
0975     GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 6, GFLAGS),
0976     GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 7, GFLAGS),
0977     GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS),
0978 };
0979
0980 static const char *const px30_cru_critical_clocks[] __initconst = {
0981     "aclk_bus_pre",
0982     "pclk_bus_pre",
0983     "hclk_bus_pre",
0984     "aclk_peri_pre",
0985     "hclk_peri_pre",
0986     "aclk_gpu_niu",
0987     "pclk_top_pre",
0988     "pclk_pmu_pre",
0989     "hclk_usb_niu",
0990     "pclk_vo_niu",
0991     "aclk_vo_niu",
0992     "hclk_vo_niu",
0993     "aclk_vi_niu",
0994     "hclk_vi_niu",
0995     "pll_npll",
0996     "usb480m",
0997     "clk_uart2",
0998     "pclk_uart2",
0999     "pclk_usb_grf",
1000 };
1001
1002 static void __init px30_clk_init(struct device_node *np)
1003 {
1004     struct rockchip_clk_provider *ctx;
1005     void __iomem *reg_base;
1006
1007     reg_base = of_iomap(np, 0);
1008     if (!reg_base) {
1009         pr_err("%s: could not map cru region\n", __func__);
1010         return;
1011     }
1012
1013     ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1014     if (IS_ERR(ctx)) {
1015         pr_err("%s: rockchip clk init failed\n", __func__);
1016         iounmap(reg_base);
1017         return;
1018     }
1019
1020     rockchip_clk_register_plls(ctx, px30_pll_clks,
1021                    ARRAY_SIZE(px30_pll_clks),
1022                    PX30_GRF_SOC_STATUS0);
1023     rockchip_clk_register_branches(ctx, px30_clk_branches,
1024                        ARRAY_SIZE(px30_clk_branches));
1025
1026     rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1027                      mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
1028                      &px30_cpuclk_data, px30_cpuclk_rates,
1029                      ARRAY_SIZE(px30_cpuclk_rates));
1030
1031     rockchip_clk_protect_critical(px30_cru_critical_clocks,
1032                       ARRAY_SIZE(px30_cru_critical_clocks));
1033
1034     rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0),
1035                   ROCKCHIP_SOFTRST_HIWORD_MASK);
1036
1037     rockchip_register_restart_notifier(ctx, PX30_GLB_SRST_FST, NULL);
1038
1039     rockchip_clk_of_add_provider(np, ctx);
1040 }
1041 CLK_OF_DECLARE(px30_cru, "rockchip,px30-cru", px30_clk_init);
1042
1043 static void __init px30_pmu_clk_init(struct device_node *np)
1044 {
1045     struct rockchip_clk_provider *ctx;
1046     void __iomem *reg_base;
1047
1048     reg_base = of_iomap(np, 0);
1049     if (!reg_base) {
1050         pr_err("%s: could not map cru pmu region\n", __func__);
1051         return;
1052     }
1053
1054     ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1055     if (IS_ERR(ctx)) {
1056         pr_err("%s: rockchip pmu clk init failed\n", __func__);
1057         return;
1058     }
1059
1060     rockchip_clk_register_plls(ctx, px30_pmu_pll_clks,
1061                    ARRAY_SIZE(px30_pmu_pll_clks), PX30_GRF_SOC_STATUS0);
1062
1063     rockchip_clk_register_branches(ctx, px30_clk_pmu_branches,
1064                        ARRAY_SIZE(px30_clk_pmu_branches));
1065
1066     rockchip_clk_of_add_provider(np, ctx);
1067 }
1068 CLK_OF_DECLARE(px30_cru_pmu, "rockchip,px30-pmucru", px30_pmu_clk_init);