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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2014 MundoReader S.L.
0004  * Author: Heiko Stuebner <heiko@sntech.de>
0005  *
0006  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
0007  * Author: Xing Zheng <zhengxing@rock-chips.com>
0008  */
0009 
0010 #include <asm/div64.h>
0011 #include <linux/slab.h>
0012 #include <linux/io.h>
0013 #include <linux/delay.h>
0014 #include <linux/clk-provider.h>
0015 #include <linux/iopoll.h>
0016 #include <linux/regmap.h>
0017 #include <linux/clk.h>
0018 #include "clk.h"
0019 
0020 #define PLL_MODE_MASK       0x3
0021 #define PLL_MODE_SLOW       0x0
0022 #define PLL_MODE_NORM       0x1
0023 #define PLL_MODE_DEEP       0x2
0024 #define PLL_RK3328_MODE_MASK    0x1
0025 
0026 struct rockchip_clk_pll {
0027     struct clk_hw       hw;
0028 
0029     struct clk_mux      pll_mux;
0030     const struct clk_ops    *pll_mux_ops;
0031 
0032     struct notifier_block   clk_nb;
0033 
0034     void __iomem        *reg_base;
0035     int         lock_offset;
0036     unsigned int        lock_shift;
0037     enum rockchip_pll_type  type;
0038     u8          flags;
0039     const struct rockchip_pll_rate_table *rate_table;
0040     unsigned int        rate_count;
0041     spinlock_t      *lock;
0042 
0043     struct rockchip_clk_provider *ctx;
0044 };
0045 
0046 #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw)
0047 #define to_rockchip_clk_pll_nb(nb) \
0048             container_of(nb, struct rockchip_clk_pll, clk_nb)
0049 
0050 static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
0051                 struct rockchip_clk_pll *pll, unsigned long rate)
0052 {
0053     const struct rockchip_pll_rate_table  *rate_table = pll->rate_table;
0054     int i;
0055 
0056     for (i = 0; i < pll->rate_count; i++) {
0057         if (rate == rate_table[i].rate)
0058             return &rate_table[i];
0059     }
0060 
0061     return NULL;
0062 }
0063 
0064 static long rockchip_pll_round_rate(struct clk_hw *hw,
0065                 unsigned long drate, unsigned long *prate)
0066 {
0067     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0068     const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
0069     int i;
0070 
0071     /* Assumming rate_table is in descending order */
0072     for (i = 0; i < pll->rate_count; i++) {
0073         if (drate >= rate_table[i].rate)
0074             return rate_table[i].rate;
0075     }
0076 
0077     /* return minimum supported value */
0078     return rate_table[i - 1].rate;
0079 }
0080 
0081 /*
0082  * Wait for the pll to reach the locked state.
0083  * The calling set_rate function is responsible for making sure the
0084  * grf regmap is available.
0085  */
0086 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
0087 {
0088     struct regmap *grf = pll->ctx->grf;
0089     unsigned int val;
0090     int ret;
0091 
0092     ret = regmap_read_poll_timeout(grf, pll->lock_offset, val,
0093                        val & BIT(pll->lock_shift), 0, 1000);
0094     if (ret)
0095         pr_err("%s: timeout waiting for pll to lock\n", __func__);
0096 
0097     return ret;
0098 }
0099 
0100 /*
0101  * PLL used in RK3036
0102  */
0103 
0104 #define RK3036_PLLCON(i)            (i * 0x4)
0105 #define RK3036_PLLCON0_FBDIV_MASK       0xfff
0106 #define RK3036_PLLCON0_FBDIV_SHIFT      0
0107 #define RK3036_PLLCON0_POSTDIV1_MASK        0x7
0108 #define RK3036_PLLCON0_POSTDIV1_SHIFT       12
0109 #define RK3036_PLLCON1_REFDIV_MASK      0x3f
0110 #define RK3036_PLLCON1_REFDIV_SHIFT     0
0111 #define RK3036_PLLCON1_POSTDIV2_MASK        0x7
0112 #define RK3036_PLLCON1_POSTDIV2_SHIFT       6
0113 #define RK3036_PLLCON1_LOCK_STATUS      BIT(10)
0114 #define RK3036_PLLCON1_DSMPD_MASK       0x1
0115 #define RK3036_PLLCON1_DSMPD_SHIFT      12
0116 #define RK3036_PLLCON1_PWRDOWN          BIT(13)
0117 #define RK3036_PLLCON2_FRAC_MASK        0xffffff
0118 #define RK3036_PLLCON2_FRAC_SHIFT       0
0119 
0120 static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll)
0121 {
0122     u32 pllcon;
0123     int ret;
0124 
0125     /*
0126      * Lock time typical 250, max 500 input clock cycles @24MHz
0127      * So define a very safe maximum of 1000us, meaning 24000 cycles.
0128      */
0129     ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),
0130                      pllcon,
0131                      pllcon & RK3036_PLLCON1_LOCK_STATUS,
0132                      0, 1000);
0133     if (ret)
0134         pr_err("%s: timeout waiting for pll to lock\n", __func__);
0135 
0136     return ret;
0137 }
0138 
0139 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
0140                     struct rockchip_pll_rate_table *rate)
0141 {
0142     u32 pllcon;
0143 
0144     pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
0145     rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT)
0146                 & RK3036_PLLCON0_FBDIV_MASK);
0147     rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT)
0148                 & RK3036_PLLCON0_POSTDIV1_MASK);
0149 
0150     pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
0151     rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT)
0152                 & RK3036_PLLCON1_REFDIV_MASK);
0153     rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT)
0154                 & RK3036_PLLCON1_POSTDIV2_MASK);
0155     rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT)
0156                 & RK3036_PLLCON1_DSMPD_MASK);
0157 
0158     pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
0159     rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT)
0160                 & RK3036_PLLCON2_FRAC_MASK);
0161 }
0162 
0163 static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
0164                              unsigned long prate)
0165 {
0166     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0167     struct rockchip_pll_rate_table cur;
0168     u64 rate64 = prate;
0169 
0170     rockchip_rk3036_pll_get_params(pll, &cur);
0171 
0172     rate64 *= cur.fbdiv;
0173     do_div(rate64, cur.refdiv);
0174 
0175     if (cur.dsmpd == 0) {
0176         /* fractional mode */
0177         u64 frac_rate64 = prate * cur.frac;
0178 
0179         do_div(frac_rate64, cur.refdiv);
0180         rate64 += frac_rate64 >> 24;
0181     }
0182 
0183     do_div(rate64, cur.postdiv1);
0184     do_div(rate64, cur.postdiv2);
0185 
0186     return (unsigned long)rate64;
0187 }
0188 
0189 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
0190                 const struct rockchip_pll_rate_table *rate)
0191 {
0192     const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
0193     struct clk_mux *pll_mux = &pll->pll_mux;
0194     struct rockchip_pll_rate_table cur;
0195     u32 pllcon;
0196     int rate_change_remuxed = 0;
0197     int cur_parent;
0198     int ret;
0199 
0200     pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
0201         __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
0202         rate->postdiv2, rate->dsmpd, rate->frac);
0203 
0204     rockchip_rk3036_pll_get_params(pll, &cur);
0205     cur.rate = 0;
0206 
0207     cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
0208     if (cur_parent == PLL_MODE_NORM) {
0209         pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
0210         rate_change_remuxed = 1;
0211     }
0212 
0213     /* update pll values */
0214     writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
0215                       RK3036_PLLCON0_FBDIV_SHIFT) |
0216                HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
0217                          RK3036_PLLCON0_POSTDIV1_SHIFT),
0218                pll->reg_base + RK3036_PLLCON(0));
0219 
0220     writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
0221                            RK3036_PLLCON1_REFDIV_SHIFT) |
0222                HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
0223                              RK3036_PLLCON1_POSTDIV2_SHIFT) |
0224                HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
0225                           RK3036_PLLCON1_DSMPD_SHIFT),
0226                pll->reg_base + RK3036_PLLCON(1));
0227 
0228     /* GPLL CON2 is not HIWORD_MASK */
0229     pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
0230     pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT);
0231     pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
0232     writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
0233 
0234     /* wait for the pll to lock */
0235     ret = rockchip_rk3036_pll_wait_lock(pll);
0236     if (ret) {
0237         pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
0238             __func__);
0239         rockchip_rk3036_pll_set_params(pll, &cur);
0240     }
0241 
0242     if (rate_change_remuxed)
0243         pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
0244 
0245     return ret;
0246 }
0247 
0248 static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate,
0249                     unsigned long prate)
0250 {
0251     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0252     const struct rockchip_pll_rate_table *rate;
0253 
0254     pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
0255          __func__, __clk_get_name(hw->clk), drate, prate);
0256 
0257     /* Get required rate settings from table */
0258     rate = rockchip_get_pll_settings(pll, drate);
0259     if (!rate) {
0260         pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
0261             drate, __clk_get_name(hw->clk));
0262         return -EINVAL;
0263     }
0264 
0265     return rockchip_rk3036_pll_set_params(pll, rate);
0266 }
0267 
0268 static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
0269 {
0270     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0271 
0272     writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
0273            pll->reg_base + RK3036_PLLCON(1));
0274     rockchip_rk3036_pll_wait_lock(pll);
0275 
0276     return 0;
0277 }
0278 
0279 static void rockchip_rk3036_pll_disable(struct clk_hw *hw)
0280 {
0281     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0282 
0283     writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
0284                  RK3036_PLLCON1_PWRDOWN, 0),
0285            pll->reg_base + RK3036_PLLCON(1));
0286 }
0287 
0288 static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw)
0289 {
0290     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0291     u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));
0292 
0293     return !(pllcon & RK3036_PLLCON1_PWRDOWN);
0294 }
0295 
0296 static int rockchip_rk3036_pll_init(struct clk_hw *hw)
0297 {
0298     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0299     const struct rockchip_pll_rate_table *rate;
0300     struct rockchip_pll_rate_table cur;
0301     unsigned long drate;
0302 
0303     if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
0304         return 0;
0305 
0306     drate = clk_hw_get_rate(hw);
0307     rate = rockchip_get_pll_settings(pll, drate);
0308 
0309     /* when no rate setting for the current rate, rely on clk_set_rate */
0310     if (!rate)
0311         return 0;
0312 
0313     rockchip_rk3036_pll_get_params(pll, &cur);
0314 
0315     pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
0316          drate);
0317     pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
0318          cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
0319          cur.dsmpd, cur.frac);
0320     pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
0321          rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
0322          rate->dsmpd, rate->frac);
0323 
0324     if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
0325         rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
0326         rate->dsmpd != cur.dsmpd ||
0327         (!cur.dsmpd && (rate->frac != cur.frac))) {
0328         struct clk *parent = clk_get_parent(hw->clk);
0329 
0330         if (!parent) {
0331             pr_warn("%s: parent of %s not available\n",
0332                 __func__, __clk_get_name(hw->clk));
0333             return 0;
0334         }
0335 
0336         pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
0337              __func__, __clk_get_name(hw->clk));
0338         rockchip_rk3036_pll_set_params(pll, rate);
0339     }
0340 
0341     return 0;
0342 }
0343 
0344 static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = {
0345     .recalc_rate = rockchip_rk3036_pll_recalc_rate,
0346     .enable = rockchip_rk3036_pll_enable,
0347     .disable = rockchip_rk3036_pll_disable,
0348     .is_enabled = rockchip_rk3036_pll_is_enabled,
0349 };
0350 
0351 static const struct clk_ops rockchip_rk3036_pll_clk_ops = {
0352     .recalc_rate = rockchip_rk3036_pll_recalc_rate,
0353     .round_rate = rockchip_pll_round_rate,
0354     .set_rate = rockchip_rk3036_pll_set_rate,
0355     .enable = rockchip_rk3036_pll_enable,
0356     .disable = rockchip_rk3036_pll_disable,
0357     .is_enabled = rockchip_rk3036_pll_is_enabled,
0358     .init = rockchip_rk3036_pll_init,
0359 };
0360 
0361 /*
0362  * PLL used in RK3066, RK3188 and RK3288
0363  */
0364 
0365 #define RK3066_PLL_RESET_DELAY(nr)  ((nr * 500) / 24 + 1)
0366 
0367 #define RK3066_PLLCON(i)        (i * 0x4)
0368 #define RK3066_PLLCON0_OD_MASK      0xf
0369 #define RK3066_PLLCON0_OD_SHIFT     0
0370 #define RK3066_PLLCON0_NR_MASK      0x3f
0371 #define RK3066_PLLCON0_NR_SHIFT     8
0372 #define RK3066_PLLCON1_NF_MASK      0x1fff
0373 #define RK3066_PLLCON1_NF_SHIFT     0
0374 #define RK3066_PLLCON2_NB_MASK      0xfff
0375 #define RK3066_PLLCON2_NB_SHIFT     0
0376 #define RK3066_PLLCON3_RESET        (1 << 5)
0377 #define RK3066_PLLCON3_PWRDOWN      (1 << 1)
0378 #define RK3066_PLLCON3_BYPASS       (1 << 0)
0379 
0380 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll,
0381                     struct rockchip_pll_rate_table *rate)
0382 {
0383     u32 pllcon;
0384 
0385     pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
0386     rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT)
0387                 & RK3066_PLLCON0_NR_MASK) + 1;
0388     rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT)
0389                 & RK3066_PLLCON0_OD_MASK) + 1;
0390 
0391     pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
0392     rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT)
0393                 & RK3066_PLLCON1_NF_MASK) + 1;
0394 
0395     pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
0396     rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT)
0397                 & RK3066_PLLCON2_NB_MASK) + 1;
0398 }
0399 
0400 static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,
0401                              unsigned long prate)
0402 {
0403     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0404     struct rockchip_pll_rate_table cur;
0405     u64 rate64 = prate;
0406     u32 pllcon;
0407 
0408     pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
0409     if (pllcon & RK3066_PLLCON3_BYPASS) {
0410         pr_debug("%s: pll %s is bypassed\n", __func__,
0411             clk_hw_get_name(hw));
0412         return prate;
0413     }
0414 
0415     rockchip_rk3066_pll_get_params(pll, &cur);
0416 
0417     rate64 *= cur.nf;
0418     do_div(rate64, cur.nr);
0419     do_div(rate64, cur.no);
0420 
0421     return (unsigned long)rate64;
0422 }
0423 
0424 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll,
0425                 const struct rockchip_pll_rate_table *rate)
0426 {
0427     const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
0428     struct clk_mux *pll_mux = &pll->pll_mux;
0429     struct rockchip_pll_rate_table cur;
0430     int rate_change_remuxed = 0;
0431     int cur_parent;
0432     int ret;
0433 
0434     pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n",
0435          __func__, rate->rate, rate->nr, rate->no, rate->nf);
0436 
0437     rockchip_rk3066_pll_get_params(pll, &cur);
0438     cur.rate = 0;
0439 
0440     cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
0441     if (cur_parent == PLL_MODE_NORM) {
0442         pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
0443         rate_change_remuxed = 1;
0444     }
0445 
0446     /* enter reset mode */
0447     writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
0448            pll->reg_base + RK3066_PLLCON(3));
0449 
0450     /* update pll values */
0451     writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
0452                        RK3066_PLLCON0_NR_SHIFT) |
0453            HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
0454                        RK3066_PLLCON0_OD_SHIFT),
0455            pll->reg_base + RK3066_PLLCON(0));
0456 
0457     writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
0458                            RK3066_PLLCON1_NF_SHIFT),
0459                pll->reg_base + RK3066_PLLCON(1));
0460     writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK,
0461                            RK3066_PLLCON2_NB_SHIFT),
0462                pll->reg_base + RK3066_PLLCON(2));
0463 
0464     /* leave reset and wait the reset_delay */
0465     writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),
0466            pll->reg_base + RK3066_PLLCON(3));
0467     udelay(RK3066_PLL_RESET_DELAY(rate->nr));
0468 
0469     /* wait for the pll to lock */
0470     ret = rockchip_pll_wait_lock(pll);
0471     if (ret) {
0472         pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
0473             __func__);
0474         rockchip_rk3066_pll_set_params(pll, &cur);
0475     }
0476 
0477     if (rate_change_remuxed)
0478         pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
0479 
0480     return ret;
0481 }
0482 
0483 static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
0484                     unsigned long prate)
0485 {
0486     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0487     const struct rockchip_pll_rate_table *rate;
0488 
0489     pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
0490          __func__, clk_hw_get_name(hw), drate, prate);
0491 
0492     /* Get required rate settings from table */
0493     rate = rockchip_get_pll_settings(pll, drate);
0494     if (!rate) {
0495         pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
0496             drate, clk_hw_get_name(hw));
0497         return -EINVAL;
0498     }
0499 
0500     return rockchip_rk3066_pll_set_params(pll, rate);
0501 }
0502 
0503 static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
0504 {
0505     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0506 
0507     writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
0508            pll->reg_base + RK3066_PLLCON(3));
0509     rockchip_pll_wait_lock(pll);
0510 
0511     return 0;
0512 }
0513 
0514 static void rockchip_rk3066_pll_disable(struct clk_hw *hw)
0515 {
0516     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0517 
0518     writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,
0519                  RK3066_PLLCON3_PWRDOWN, 0),
0520            pll->reg_base + RK3066_PLLCON(3));
0521 }
0522 
0523 static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw)
0524 {
0525     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0526     u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
0527 
0528     return !(pllcon & RK3066_PLLCON3_PWRDOWN);
0529 }
0530 
0531 static int rockchip_rk3066_pll_init(struct clk_hw *hw)
0532 {
0533     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0534     const struct rockchip_pll_rate_table *rate;
0535     struct rockchip_pll_rate_table cur;
0536     unsigned long drate;
0537 
0538     if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
0539         return 0;
0540 
0541     drate = clk_hw_get_rate(hw);
0542     rate = rockchip_get_pll_settings(pll, drate);
0543 
0544     /* when no rate setting for the current rate, rely on clk_set_rate */
0545     if (!rate)
0546         return 0;
0547 
0548     rockchip_rk3066_pll_get_params(pll, &cur);
0549 
0550     pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n",
0551          __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr,
0552          rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb);
0553     if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf
0554                              || rate->nb != cur.nb) {
0555         pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
0556              __func__, clk_hw_get_name(hw));
0557         rockchip_rk3066_pll_set_params(pll, rate);
0558     }
0559 
0560     return 0;
0561 }
0562 
0563 static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
0564     .recalc_rate = rockchip_rk3066_pll_recalc_rate,
0565     .enable = rockchip_rk3066_pll_enable,
0566     .disable = rockchip_rk3066_pll_disable,
0567     .is_enabled = rockchip_rk3066_pll_is_enabled,
0568 };
0569 
0570 static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
0571     .recalc_rate = rockchip_rk3066_pll_recalc_rate,
0572     .round_rate = rockchip_pll_round_rate,
0573     .set_rate = rockchip_rk3066_pll_set_rate,
0574     .enable = rockchip_rk3066_pll_enable,
0575     .disable = rockchip_rk3066_pll_disable,
0576     .is_enabled = rockchip_rk3066_pll_is_enabled,
0577     .init = rockchip_rk3066_pll_init,
0578 };
0579 
0580 /*
0581  * PLL used in RK3399
0582  */
0583 
0584 #define RK3399_PLLCON(i)            (i * 0x4)
0585 #define RK3399_PLLCON0_FBDIV_MASK       0xfff
0586 #define RK3399_PLLCON0_FBDIV_SHIFT      0
0587 #define RK3399_PLLCON1_REFDIV_MASK      0x3f
0588 #define RK3399_PLLCON1_REFDIV_SHIFT     0
0589 #define RK3399_PLLCON1_POSTDIV1_MASK        0x7
0590 #define RK3399_PLLCON1_POSTDIV1_SHIFT       8
0591 #define RK3399_PLLCON1_POSTDIV2_MASK        0x7
0592 #define RK3399_PLLCON1_POSTDIV2_SHIFT       12
0593 #define RK3399_PLLCON2_FRAC_MASK        0xffffff
0594 #define RK3399_PLLCON2_FRAC_SHIFT       0
0595 #define RK3399_PLLCON2_LOCK_STATUS      BIT(31)
0596 #define RK3399_PLLCON3_PWRDOWN          BIT(0)
0597 #define RK3399_PLLCON3_DSMPD_MASK       0x1
0598 #define RK3399_PLLCON3_DSMPD_SHIFT      3
0599 
0600 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)
0601 {
0602     u32 pllcon;
0603     int ret;
0604 
0605     /*
0606      * Lock time typical 250, max 500 input clock cycles @24MHz
0607      * So define a very safe maximum of 1000us, meaning 24000 cycles.
0608      */
0609     ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),
0610                      pllcon,
0611                      pllcon & RK3399_PLLCON2_LOCK_STATUS,
0612                      0, 1000);
0613     if (ret)
0614         pr_err("%s: timeout waiting for pll to lock\n", __func__);
0615 
0616     return ret;
0617 }
0618 
0619 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,
0620                     struct rockchip_pll_rate_table *rate)
0621 {
0622     u32 pllcon;
0623 
0624     pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0));
0625     rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT)
0626                 & RK3399_PLLCON0_FBDIV_MASK);
0627 
0628     pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1));
0629     rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT)
0630                 & RK3399_PLLCON1_REFDIV_MASK);
0631     rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT)
0632                 & RK3399_PLLCON1_POSTDIV1_MASK);
0633     rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT)
0634                 & RK3399_PLLCON1_POSTDIV2_MASK);
0635 
0636     pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
0637     rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT)
0638                 & RK3399_PLLCON2_FRAC_MASK);
0639 
0640     pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3));
0641     rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT)
0642                 & RK3399_PLLCON3_DSMPD_MASK);
0643 }
0644 
0645 static unsigned long rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw,
0646                              unsigned long prate)
0647 {
0648     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0649     struct rockchip_pll_rate_table cur;
0650     u64 rate64 = prate;
0651 
0652     rockchip_rk3399_pll_get_params(pll, &cur);
0653 
0654     rate64 *= cur.fbdiv;
0655     do_div(rate64, cur.refdiv);
0656 
0657     if (cur.dsmpd == 0) {
0658         /* fractional mode */
0659         u64 frac_rate64 = prate * cur.frac;
0660 
0661         do_div(frac_rate64, cur.refdiv);
0662         rate64 += frac_rate64 >> 24;
0663     }
0664 
0665     do_div(rate64, cur.postdiv1);
0666     do_div(rate64, cur.postdiv2);
0667 
0668     return (unsigned long)rate64;
0669 }
0670 
0671 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
0672                 const struct rockchip_pll_rate_table *rate)
0673 {
0674     const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
0675     struct clk_mux *pll_mux = &pll->pll_mux;
0676     struct rockchip_pll_rate_table cur;
0677     u32 pllcon;
0678     int rate_change_remuxed = 0;
0679     int cur_parent;
0680     int ret;
0681 
0682     pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
0683         __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
0684         rate->postdiv2, rate->dsmpd, rate->frac);
0685 
0686     rockchip_rk3399_pll_get_params(pll, &cur);
0687     cur.rate = 0;
0688 
0689     cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
0690     if (cur_parent == PLL_MODE_NORM) {
0691         pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
0692         rate_change_remuxed = 1;
0693     }
0694 
0695     /* update pll values */
0696     writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
0697                           RK3399_PLLCON0_FBDIV_SHIFT),
0698                pll->reg_base + RK3399_PLLCON(0));
0699 
0700     writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK,
0701                            RK3399_PLLCON1_REFDIV_SHIFT) |
0702                HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK,
0703                              RK3399_PLLCON1_POSTDIV1_SHIFT) |
0704                HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK,
0705                              RK3399_PLLCON1_POSTDIV2_SHIFT),
0706                pll->reg_base + RK3399_PLLCON(1));
0707 
0708     /* xPLL CON2 is not HIWORD_MASK */
0709     pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
0710     pllcon &= ~(RK3399_PLLCON2_FRAC_MASK << RK3399_PLLCON2_FRAC_SHIFT);
0711     pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT;
0712     writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2));
0713 
0714     writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK,
0715                         RK3399_PLLCON3_DSMPD_SHIFT),
0716                pll->reg_base + RK3399_PLLCON(3));
0717 
0718     /* wait for the pll to lock */
0719     ret = rockchip_rk3399_pll_wait_lock(pll);
0720     if (ret) {
0721         pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
0722             __func__);
0723         rockchip_rk3399_pll_set_params(pll, &cur);
0724     }
0725 
0726     if (rate_change_remuxed)
0727         pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
0728 
0729     return ret;
0730 }
0731 
0732 static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate,
0733                     unsigned long prate)
0734 {
0735     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0736     const struct rockchip_pll_rate_table *rate;
0737 
0738     pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
0739          __func__, __clk_get_name(hw->clk), drate, prate);
0740 
0741     /* Get required rate settings from table */
0742     rate = rockchip_get_pll_settings(pll, drate);
0743     if (!rate) {
0744         pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
0745             drate, __clk_get_name(hw->clk));
0746         return -EINVAL;
0747     }
0748 
0749     return rockchip_rk3399_pll_set_params(pll, rate);
0750 }
0751 
0752 static int rockchip_rk3399_pll_enable(struct clk_hw *hw)
0753 {
0754     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0755 
0756     writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0),
0757            pll->reg_base + RK3399_PLLCON(3));
0758     rockchip_rk3399_pll_wait_lock(pll);
0759 
0760     return 0;
0761 }
0762 
0763 static void rockchip_rk3399_pll_disable(struct clk_hw *hw)
0764 {
0765     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0766 
0767     writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
0768                  RK3399_PLLCON3_PWRDOWN, 0),
0769            pll->reg_base + RK3399_PLLCON(3));
0770 }
0771 
0772 static int rockchip_rk3399_pll_is_enabled(struct clk_hw *hw)
0773 {
0774     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0775     u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3));
0776 
0777     return !(pllcon & RK3399_PLLCON3_PWRDOWN);
0778 }
0779 
0780 static int rockchip_rk3399_pll_init(struct clk_hw *hw)
0781 {
0782     struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
0783     const struct rockchip_pll_rate_table *rate;
0784     struct rockchip_pll_rate_table cur;
0785     unsigned long drate;
0786 
0787     if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
0788         return 0;
0789 
0790     drate = clk_hw_get_rate(hw);
0791     rate = rockchip_get_pll_settings(pll, drate);
0792 
0793     /* when no rate setting for the current rate, rely on clk_set_rate */
0794     if (!rate)
0795         return 0;
0796 
0797     rockchip_rk3399_pll_get_params(pll, &cur);
0798 
0799     pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
0800          drate);
0801     pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
0802          cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
0803          cur.dsmpd, cur.frac);
0804     pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
0805          rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
0806          rate->dsmpd, rate->frac);
0807 
0808     if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
0809         rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
0810         rate->dsmpd != cur.dsmpd ||
0811         (!cur.dsmpd && (rate->frac != cur.frac))) {
0812         struct clk *parent = clk_get_parent(hw->clk);
0813 
0814         if (!parent) {
0815             pr_warn("%s: parent of %s not available\n",
0816                 __func__, __clk_get_name(hw->clk));
0817             return 0;
0818         }
0819 
0820         pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
0821              __func__, __clk_get_name(hw->clk));
0822         rockchip_rk3399_pll_set_params(pll, rate);
0823     }
0824 
0825     return 0;
0826 }
0827 
0828 static const struct clk_ops rockchip_rk3399_pll_clk_norate_ops = {
0829     .recalc_rate = rockchip_rk3399_pll_recalc_rate,
0830     .enable = rockchip_rk3399_pll_enable,
0831     .disable = rockchip_rk3399_pll_disable,
0832     .is_enabled = rockchip_rk3399_pll_is_enabled,
0833 };
0834 
0835 static const struct clk_ops rockchip_rk3399_pll_clk_ops = {
0836     .recalc_rate = rockchip_rk3399_pll_recalc_rate,
0837     .round_rate = rockchip_pll_round_rate,
0838     .set_rate = rockchip_rk3399_pll_set_rate,
0839     .enable = rockchip_rk3399_pll_enable,
0840     .disable = rockchip_rk3399_pll_disable,
0841     .is_enabled = rockchip_rk3399_pll_is_enabled,
0842     .init = rockchip_rk3399_pll_init,
0843 };
0844 
0845 /*
0846  * Common registering of pll clocks
0847  */
0848 
0849 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
0850         enum rockchip_pll_type pll_type,
0851         const char *name, const char *const *parent_names,
0852         u8 num_parents, int con_offset, int grf_lock_offset,
0853         int lock_shift, int mode_offset, int mode_shift,
0854         struct rockchip_pll_rate_table *rate_table,
0855         unsigned long flags, u8 clk_pll_flags)
0856 {
0857     const char *pll_parents[3];
0858     struct clk_init_data init;
0859     struct rockchip_clk_pll *pll;
0860     struct clk_mux *pll_mux;
0861     struct clk *pll_clk, *mux_clk;
0862     char pll_name[20];
0863 
0864     if ((pll_type != pll_rk3328 && num_parents != 2) ||
0865         (pll_type == pll_rk3328 && num_parents != 1)) {
0866         pr_err("%s: needs two parent clocks\n", __func__);
0867         return ERR_PTR(-EINVAL);
0868     }
0869 
0870     /* name the actual pll */
0871     snprintf(pll_name, sizeof(pll_name), "pll_%s", name);
0872 
0873     pll = kzalloc(sizeof(*pll), GFP_KERNEL);
0874     if (!pll)
0875         return ERR_PTR(-ENOMEM);
0876 
0877     /* create the mux on top of the real pll */
0878     pll->pll_mux_ops = &clk_mux_ops;
0879     pll_mux = &pll->pll_mux;
0880     pll_mux->reg = ctx->reg_base + mode_offset;
0881     pll_mux->shift = mode_shift;
0882     if (pll_type == pll_rk3328)
0883         pll_mux->mask = PLL_RK3328_MODE_MASK;
0884     else
0885         pll_mux->mask = PLL_MODE_MASK;
0886     pll_mux->flags = 0;
0887     pll_mux->lock = &ctx->lock;
0888     pll_mux->hw.init = &init;
0889 
0890     if (pll_type == pll_rk3036 ||
0891         pll_type == pll_rk3066 ||
0892         pll_type == pll_rk3328 ||
0893         pll_type == pll_rk3399)
0894         pll_mux->flags |= CLK_MUX_HIWORD_MASK;
0895 
0896     /* the actual muxing is xin24m, pll-output, xin32k */
0897     pll_parents[0] = parent_names[0];
0898     pll_parents[1] = pll_name;
0899     pll_parents[2] = parent_names[1];
0900 
0901     init.name = name;
0902     init.flags = CLK_SET_RATE_PARENT;
0903     init.ops = pll->pll_mux_ops;
0904     init.parent_names = pll_parents;
0905     if (pll_type == pll_rk3328)
0906         init.num_parents = 2;
0907     else
0908         init.num_parents = ARRAY_SIZE(pll_parents);
0909 
0910     mux_clk = clk_register(NULL, &pll_mux->hw);
0911     if (IS_ERR(mux_clk))
0912         goto err_mux;
0913 
0914     /* now create the actual pll */
0915     init.name = pll_name;
0916 
0917     /* keep all plls untouched for now */
0918     init.flags = flags | CLK_IGNORE_UNUSED;
0919 
0920     init.parent_names = &parent_names[0];
0921     init.num_parents = 1;
0922 
0923     if (rate_table) {
0924         int len;
0925 
0926         /* find count of rates in rate_table */
0927         for (len = 0; rate_table[len].rate != 0; )
0928             len++;
0929 
0930         pll->rate_count = len;
0931         pll->rate_table = kmemdup(rate_table,
0932                     pll->rate_count *
0933                     sizeof(struct rockchip_pll_rate_table),
0934                     GFP_KERNEL);
0935         WARN(!pll->rate_table,
0936             "%s: could not allocate rate table for %s\n",
0937             __func__, name);
0938     }
0939 
0940     switch (pll_type) {
0941     case pll_rk3036:
0942     case pll_rk3328:
0943         if (!pll->rate_table)
0944             init.ops = &rockchip_rk3036_pll_clk_norate_ops;
0945         else
0946             init.ops = &rockchip_rk3036_pll_clk_ops;
0947         break;
0948     case pll_rk3066:
0949         if (!pll->rate_table || IS_ERR(ctx->grf))
0950             init.ops = &rockchip_rk3066_pll_clk_norate_ops;
0951         else
0952             init.ops = &rockchip_rk3066_pll_clk_ops;
0953         break;
0954     case pll_rk3399:
0955         if (!pll->rate_table)
0956             init.ops = &rockchip_rk3399_pll_clk_norate_ops;
0957         else
0958             init.ops = &rockchip_rk3399_pll_clk_ops;
0959         break;
0960     default:
0961         pr_warn("%s: Unknown pll type for pll clk %s\n",
0962             __func__, name);
0963     }
0964 
0965     pll->hw.init = &init;
0966     pll->type = pll_type;
0967     pll->reg_base = ctx->reg_base + con_offset;
0968     pll->lock_offset = grf_lock_offset;
0969     pll->lock_shift = lock_shift;
0970     pll->flags = clk_pll_flags;
0971     pll->lock = &ctx->lock;
0972     pll->ctx = ctx;
0973 
0974     pll_clk = clk_register(NULL, &pll->hw);
0975     if (IS_ERR(pll_clk)) {
0976         pr_err("%s: failed to register pll clock %s : %ld\n",
0977             __func__, name, PTR_ERR(pll_clk));
0978         goto err_pll;
0979     }
0980 
0981     return mux_clk;
0982 
0983 err_pll:
0984     clk_unregister(mux_clk);
0985     mux_clk = pll_clk;
0986 err_mux:
0987     kfree(pll);
0988     return mux_clk;
0989 }
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