clk/rockchip/clk-muxgrf.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002
0003 #include <linux/slab.h>
0004 #include <linux/bitops.h>
0005 #include <linux/regmap.h>
0006 #include <linux/clk.h>
0007 #include <linux/clk-provider.h>
0008 #include "clk.h"
0009
0010 struct rockchip_muxgrf_clock {
0011     struct clk_hw       hw;
0012     struct regmap       *regmap;
0013     u32         reg;
0014     u32         shift;
0015     u32         width;
0016     int         flags;
0017 };
0018
0019 #define to_muxgrf_clock(_hw) container_of(_hw, struct rockchip_muxgrf_clock, hw)
0020
0021 static u8 rockchip_muxgrf_get_parent(struct clk_hw *hw)
0022 {
0023     struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw);
0024     unsigned int mask = GENMASK(mux->width - 1, 0);
0025     unsigned int val;
0026
0027     regmap_read(mux->regmap, mux->reg, &val);
0028
0029     val >>= mux->shift;
0030     val &= mask;
0031
0032     return val;
0033 }
0034
0035 static int rockchip_muxgrf_set_parent(struct clk_hw *hw, u8 index)
0036 {
0037     struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw);
0038     unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
0039     unsigned int val;
0040
0041     val = index;
0042     val <<= mux->shift;
0043
0044     if (mux->flags & CLK_MUX_HIWORD_MASK)
0045         return regmap_write(mux->regmap, mux->reg, val | (mask << 16));
0046     else
0047         return regmap_update_bits(mux->regmap, mux->reg, mask, val);
0048 }
0049
0050 static const struct clk_ops rockchip_muxgrf_clk_ops = {
0051     .get_parent = rockchip_muxgrf_get_parent,
0052     .set_parent = rockchip_muxgrf_set_parent,
0053     .determine_rate = __clk_mux_determine_rate,
0054 };
0055
0056 struct clk *rockchip_clk_register_muxgrf(const char *name,
0057                 const char *const *parent_names, u8 num_parents,
0058                 int flags, struct regmap *regmap, int reg,
0059                 int shift, int width, int mux_flags)
0060 {
0061     struct rockchip_muxgrf_clock *muxgrf_clock;
0062     struct clk_init_data init;
0063     struct clk *clk;
0064
0065     if (IS_ERR(regmap)) {
0066         pr_err("%s: regmap not available\n", __func__);
0067         return ERR_PTR(-ENOTSUPP);
0068     }
0069
0070     muxgrf_clock = kmalloc(sizeof(*muxgrf_clock), GFP_KERNEL);
0071     if (!muxgrf_clock)
0072         return ERR_PTR(-ENOMEM);
0073
0074     init.name = name;
0075     init.flags = flags;
0076     init.num_parents = num_parents;
0077     init.parent_names = parent_names;
0078     init.ops = &rockchip_muxgrf_clk_ops;
0079
0080     muxgrf_clock->hw.init = &init;
0081     muxgrf_clock->regmap = regmap;
0082     muxgrf_clock->reg = reg;
0083     muxgrf_clock->shift = shift;
0084     muxgrf_clock->width = width;
0085     muxgrf_clock->flags = mux_flags;
0086
0087     clk = clk_register(NULL, &muxgrf_clock->hw);
0088     if (IS_ERR(clk))
0089         kfree(muxgrf_clock);
0090
0091     return clk;
0092 }