clk/rockchip/clk-ddr.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
0004  * Author: Lin Huang <hl@rock-chips.com>
0005  */
0006
0007 #include <linux/arm-smccc.h>
0008 #include <linux/clk.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/io.h>
0011 #include <linux/slab.h>
0012 #include <soc/rockchip/rockchip_sip.h>
0013 #include "clk.h"
0014
0015 struct rockchip_ddrclk {
0016     struct clk_hw   hw;
0017     void __iomem    *reg_base;
0018     int     mux_offset;
0019     int     mux_shift;
0020     int     mux_width;
0021     int     div_shift;
0022     int     div_width;
0023     int     ddr_flag;
0024     spinlock_t  *lock;
0025 };
0026
0027 #define to_rockchip_ddrclk_hw(hw) container_of(hw, struct rockchip_ddrclk, hw)
0028
0029 static int rockchip_ddrclk_sip_set_rate(struct clk_hw *hw, unsigned long drate,
0030                     unsigned long prate)
0031 {
0032     struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
0033     unsigned long flags;
0034     struct arm_smccc_res res;
0035
0036     spin_lock_irqsave(ddrclk->lock, flags);
0037     arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, drate, 0,
0038               ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
0039               0, 0, 0, 0, &res);
0040     spin_unlock_irqrestore(ddrclk->lock, flags);
0041
0042     return res.a0;
0043 }
0044
0045 static unsigned long
0046 rockchip_ddrclk_sip_recalc_rate(struct clk_hw *hw,
0047                 unsigned long parent_rate)
0048 {
0049     struct arm_smccc_res res;
0050
0051     arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
0052               ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
0053               0, 0, 0, 0, &res);
0054
0055     return res.a0;
0056 }
0057
0058 static long rockchip_ddrclk_sip_round_rate(struct clk_hw *hw,
0059                        unsigned long rate,
0060                        unsigned long *prate)
0061 {
0062     struct arm_smccc_res res;
0063
0064     arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, rate, 0,
0065               ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
0066               0, 0, 0, 0, &res);
0067
0068     return res.a0;
0069 }
0070
0071 static u8 rockchip_ddrclk_get_parent(struct clk_hw *hw)
0072 {
0073     struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
0074     u32 val;
0075
0076     val = readl(ddrclk->reg_base +
0077             ddrclk->mux_offset) >> ddrclk->mux_shift;
0078     val &= GENMASK(ddrclk->mux_width - 1, 0);
0079
0080     return val;
0081 }
0082
0083 static const struct clk_ops rockchip_ddrclk_sip_ops = {
0084     .recalc_rate = rockchip_ddrclk_sip_recalc_rate,
0085     .set_rate = rockchip_ddrclk_sip_set_rate,
0086     .round_rate = rockchip_ddrclk_sip_round_rate,
0087     .get_parent = rockchip_ddrclk_get_parent,
0088 };
0089
0090 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
0091                      const char *const *parent_names,
0092                      u8 num_parents, int mux_offset,
0093                      int mux_shift, int mux_width,
0094                      int div_shift, int div_width,
0095                      int ddr_flag, void __iomem *reg_base,
0096                      spinlock_t *lock)
0097 {
0098     struct rockchip_ddrclk *ddrclk;
0099     struct clk_init_data init;
0100     struct clk *clk;
0101
0102     ddrclk = kzalloc(sizeof(*ddrclk), GFP_KERNEL);
0103     if (!ddrclk)
0104         return ERR_PTR(-ENOMEM);
0105
0106     init.name = name;
0107     init.parent_names = parent_names;
0108     init.num_parents = num_parents;
0109
0110     init.flags = flags;
0111     init.flags |= CLK_SET_RATE_NO_REPARENT;
0112
0113     switch (ddr_flag) {
0114     case ROCKCHIP_DDRCLK_SIP:
0115         init.ops = &rockchip_ddrclk_sip_ops;
0116         break;
0117     default:
0118         pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
0119         kfree(ddrclk);
0120         return ERR_PTR(-EINVAL);
0121     }
0122
0123     ddrclk->reg_base = reg_base;
0124     ddrclk->lock = lock;
0125     ddrclk->hw.init = &init;
0126     ddrclk->mux_offset = mux_offset;
0127     ddrclk->mux_shift = mux_shift;
0128     ddrclk->mux_width = mux_width;
0129     ddrclk->div_shift = div_shift;
0130     ddrclk->div_width = div_width;
0131     ddrclk->ddr_flag = ddr_flag;
0132
0133     clk = clk_register(NULL, &ddrclk->hw);
0134     if (IS_ERR(clk))
0135         kfree(ddrclk);
0136
0137     return clk;
0138 }
0139 EXPORT_SYMBOL_GPL(rockchip_clk_register_ddrclk);