clk/renesas/rzg2l-cpg.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * RZ/G2L Clock Pulse Generator
0004  *
0005  * Copyright (C) 2021 Renesas Electronics Corp.
0006  *
0007  */
0008
0009 #ifndef __RENESAS_RZG2L_CPG_H__
0010 #define __RENESAS_RZG2L_CPG_H__
0011
0012 #define CPG_SIPLL5_STBY     (0x140)
0013 #define CPG_SIPLL5_CLK1     (0x144)
0014 #define CPG_SIPLL5_CLK3     (0x14C)
0015 #define CPG_SIPLL5_CLK4     (0x150)
0016 #define CPG_SIPLL5_CLK5     (0x154)
0017 #define CPG_SIPLL5_MON      (0x15C)
0018 #define CPG_PL1_DDIV        (0x200)
0019 #define CPG_PL2_DDIV        (0x204)
0020 #define CPG_PL3A_DDIV       (0x208)
0021 #define CPG_PL6_DDIV        (0x210)
0022 #define CPG_PL2SDHI_DSEL    (0x218)
0023 #define CPG_CLKSTATUS       (0x280)
0024 #define CPG_PL3_SSEL        (0x408)
0025 #define CPG_PL6_SSEL        (0x414)
0026 #define CPG_PL6_ETH_SSEL    (0x418)
0027 #define CPG_PL5_SDIV        (0x420)
0028 #define CPG_RST_MON     (0x680)
0029 #define CPG_OTHERFUNC1_REG  (0xBE8)
0030
0031 #define CPG_SIPLL5_STBY_RESETB      BIT(0)
0032 #define CPG_SIPLL5_STBY_RESETB_WEN  BIT(16)
0033 #define CPG_SIPLL5_STBY_SSCG_EN_WEN BIT(18)
0034 #define CPG_SIPLL5_STBY_DOWNSPREAD_WEN  BIT(20)
0035 #define CPG_SIPLL5_CLK1_POSTDIV1_WEN    BIT(16)
0036 #define CPG_SIPLL5_CLK1_POSTDIV2_WEN    BIT(20)
0037 #define CPG_SIPLL5_CLK1_REFDIV_WEN  BIT(24)
0038 #define CPG_SIPLL5_CLK4_RESV_LSB    (0xFF)
0039 #define CPG_SIPLL5_MON_PLL5_LOCK    BIT(4)
0040
0041 #define CPG_OTHERFUNC1_REG_RES0_ON_WEN  BIT(16)
0042
0043 #define CPG_PL5_SDIV_DIV_DSI_A_WEN  BIT(16)
0044 #define CPG_PL5_SDIV_DIV_DSI_B_WEN  BIT(24)
0045
0046 #define CPG_CLKSTATUS_SELSDHI0_STS  BIT(28)
0047 #define CPG_CLKSTATUS_SELSDHI1_STS  BIT(29)
0048
0049 #define CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US   20000
0050
0051 /* n = 0/1/2 for PLL1/4/6 */
0052 #define CPG_SAMPLL_CLK1(n)  (0x04 + (16 * n))
0053 #define CPG_SAMPLL_CLK2(n)  (0x08 + (16 * n))
0054
0055 #define PLL146_CONF(n)  (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12)
0056
0057 #define DDIV_PACK(offset, bitpos, size) \
0058         (((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
0059 #define DIVPL1A     DDIV_PACK(CPG_PL1_DDIV, 0, 2)
0060 #define DIVPL2A     DDIV_PACK(CPG_PL2_DDIV, 0, 3)
0061 #define DIVDSILPCLK DDIV_PACK(CPG_PL2_DDIV, 12, 2)
0062 #define DIVPL3A     DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
0063 #define DIVPL3B     DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
0064 #define DIVPL3C     DDIV_PACK(CPG_PL3A_DDIV, 8, 3)
0065 #define DIVGPU      DDIV_PACK(CPG_PL6_DDIV, 0, 2)
0066
0067 #define SEL_PLL_PACK(offset, bitpos, size) \
0068         (((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
0069
0070 #define SEL_PLL3_3  SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1)
0071 #define SEL_PLL5_4  SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1)
0072 #define SEL_PLL6_2  SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)
0073 #define SEL_GPU2    SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1)
0074
0075 #define SEL_SDHI0   DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2)
0076 #define SEL_SDHI1   DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2)
0077
0078 #define EXTAL_FREQ_IN_MEGA_HZ   (24)
0079
0080 /**
0081  * Definitions of CPG Core Clocks
0082  *
0083  * These include:
0084  *   - Clock outputs exported to DT
0085  *   - External input clocks
0086  *   - Internal CPG clocks
0087  */
0088 struct cpg_core_clk {
0089     const char *name;
0090     unsigned int id;
0091     unsigned int parent;
0092     unsigned int div;
0093     unsigned int mult;
0094     unsigned int type;
0095     unsigned int conf;
0096     const struct clk_div_table *dtable;
0097     const char * const *parent_names;
0098     int flag;
0099     int mux_flags;
0100     int num_parents;
0101 };
0102
0103 enum clk_types {
0104     /* Generic */
0105     CLK_TYPE_IN,        /* External Clock Input */
0106     CLK_TYPE_FF,        /* Fixed Factor Clock */
0107     CLK_TYPE_SAM_PLL,
0108
0109     /* Clock with divider */
0110     CLK_TYPE_DIV,
0111
0112     /* Clock with clock source selector */
0113     CLK_TYPE_MUX,
0114
0115     /* Clock with SD clock source selector */
0116     CLK_TYPE_SD_MUX,
0117
0118     /* Clock for SIPLL5 */
0119     CLK_TYPE_SIPLL5,
0120
0121     /* Clock for PLL5_4 clock source selector */
0122     CLK_TYPE_PLL5_4_MUX,
0123
0124     /* Clock for DSI divider */
0125     CLK_TYPE_DSI_DIV,
0126
0127 };
0128
0129 #define DEF_TYPE(_name, _id, _type...) \
0130     { .name = _name, .id = _id, .type = _type }
0131 #define DEF_BASE(_name, _id, _type, _parent...) \
0132     DEF_TYPE(_name, _id, _type, .parent = _parent)
0133 #define DEF_SAMPLL(_name, _id, _parent, _conf) \
0134     DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
0135 #define DEF_INPUT(_name, _id) \
0136     DEF_TYPE(_name, _id, CLK_TYPE_IN)
0137 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \
0138     DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
0139 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
0140     DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
0141          .parent = _parent, .dtable = _dtable, \
0142          .flag = CLK_DIVIDER_HIWORD_MASK)
0143 #define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \
0144     DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
0145          .parent = _parent, .dtable = _dtable, \
0146          .flag = CLK_DIVIDER_READ_ONLY)
0147 #define DEF_MUX(_name, _id, _conf, _parent_names) \
0148     DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
0149          .parent_names = _parent_names, \
0150          .num_parents = ARRAY_SIZE(_parent_names), \
0151          .mux_flags = CLK_MUX_HIWORD_MASK)
0152 #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \
0153     DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
0154          .parent_names = _parent_names, \
0155          .num_parents = ARRAY_SIZE(_parent_names), \
0156          .mux_flags = CLK_MUX_READ_ONLY)
0157 #define DEF_SD_MUX(_name, _id, _conf, _parent_names) \
0158     DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \
0159          .parent_names = _parent_names, \
0160          .num_parents = ARRAY_SIZE(_parent_names))
0161 #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \
0162     DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent)
0163 #define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \
0164     DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \
0165          .parent_names = _parent_names, \
0166          .num_parents = ARRAY_SIZE(_parent_names))
0167 #define DEF_DSI_DIV(_name, _id, _parent, _flag) \
0168     DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag)
0169
0170 /**
0171  * struct rzg2l_mod_clk - Module Clocks definitions
0172  *
0173  * @name: handle between common and hardware-specific interfaces
0174  * @id: clock index in array containing all Core and Module Clocks
0175  * @parent: id of parent clock
0176  * @off: register offset
0177  * @bit: ON/MON bit
0178  * @is_coupled: flag to indicate coupled clock
0179  */
0180 struct rzg2l_mod_clk {
0181     const char *name;
0182     unsigned int id;
0183     unsigned int parent;
0184     u16 off;
0185     u8 bit;
0186     bool is_coupled;
0187 };
0188
0189 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled)  \
0190     { \
0191         .name = _name, \
0192         .id = MOD_CLK_BASE + (_id), \
0193         .parent = (_parent), \
0194         .off = (_off), \
0195         .bit = (_bit), \
0196         .is_coupled = (_is_coupled), \
0197     }
0198
0199 #define DEF_MOD(_name, _id, _parent, _off, _bit)    \
0200     DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false)
0201
0202 #define DEF_COUPLED(_name, _id, _parent, _off, _bit)    \
0203     DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true)
0204
0205 /**
0206  * struct rzg2l_reset - Reset definitions
0207  *
0208  * @off: register offset
0209  * @bit: reset bit
0210  * @monbit: monitor bit in CPG_RST_MON register, -1 if none
0211  */
0212 struct rzg2l_reset {
0213     u16 off;
0214     u8 bit;
0215     s8 monbit;
0216 };
0217
0218 #define DEF_RST_MON(_id, _off, _bit, _monbit)   \
0219     [_id] = { \
0220         .off = (_off), \
0221         .bit = (_bit), \
0222         .monbit = (_monbit) \
0223     }
0224 #define DEF_RST(_id, _off, _bit)    \
0225     DEF_RST_MON(_id, _off, _bit, -1)
0226
0227 /**
0228  * struct rzg2l_cpg_info - SoC-specific CPG Description
0229  *
0230  * @core_clks: Array of Core Clock definitions
0231  * @num_core_clks: Number of entries in core_clks[]
0232  * @last_dt_core_clk: ID of the last Core Clock exported to DT
0233  * @num_total_core_clks: Total number of Core Clocks (exported + internal)
0234  *
0235  * @mod_clks: Array of Module Clock definitions
0236  * @num_mod_clks: Number of entries in mod_clks[]
0237  * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
0238  *
0239  * @resets: Array of Module Reset definitions
0240  * @num_resets: Number of entries in resets[]
0241  *
0242  * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
0243  *                 should not be disabled without a knowledgeable driver
0244  * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
0245  * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
0246  */
0247 struct rzg2l_cpg_info {
0248     /* Core Clocks */
0249     const struct cpg_core_clk *core_clks;
0250     unsigned int num_core_clks;
0251     unsigned int last_dt_core_clk;
0252     unsigned int num_total_core_clks;
0253
0254     /* Module Clocks */
0255     const struct rzg2l_mod_clk *mod_clks;
0256     unsigned int num_mod_clks;
0257     unsigned int num_hw_mod_clks;
0258
0259     /* Resets */
0260     const struct rzg2l_reset *resets;
0261     unsigned int num_resets;
0262
0263     /* Critical Module Clocks that should not be disabled */
0264     const unsigned int *crit_mod_clks;
0265     unsigned int num_crit_mod_clks;
0266
0267     bool has_clk_mon_regs;
0268 };
0269
0270 extern const struct rzg2l_cpg_info r9a07g043_cpg_info;
0271 extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
0272 extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
0273 extern const struct rzg2l_cpg_info r9a09g011_cpg_info;
0274
0275 #endif