clk/renesas/renesas-cpg-mssr.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Renesas Clock Pulse Generator / Module Standby and Software Reset
0004  *
0005  * Copyright (C) 2015 Glider bvba
0006  */
0007
0008 #ifndef __CLK_RENESAS_CPG_MSSR_H__
0009 #define __CLK_RENESAS_CPG_MSSR_H__
0010
0011     /*
0012      * Definitions of CPG Core Clocks
0013      *
0014      * These include:
0015      *   - Clock outputs exported to DT
0016      *   - External input clocks
0017      *   - Internal CPG clocks
0018      */
0019
0020 struct cpg_core_clk {
0021     /* Common */
0022     const char *name;
0023     unsigned int id;
0024     unsigned int type;
0025     /* Depending on type */
0026     unsigned int parent;    /* Core Clocks only */
0027     unsigned int div;
0028     unsigned int mult;
0029     unsigned int offset;
0030 };
0031
0032 enum clk_types {
0033     /* Generic */
0034     CLK_TYPE_IN,        /* External Clock Input */
0035     CLK_TYPE_FF,        /* Fixed Factor Clock */
0036     CLK_TYPE_DIV6P1,    /* DIV6 Clock with 1 parent clock */
0037     CLK_TYPE_DIV6_RO,   /* DIV6 Clock read only with extra divisor */
0038     CLK_TYPE_FR,        /* Fixed Rate Clock */
0039
0040     /* Custom definitions start here */
0041     CLK_TYPE_CUSTOM,
0042 };
0043
0044 #define DEF_TYPE(_name, _id, _type...)  \
0045     { .name = _name, .id = _id, .type = _type }
0046 #define DEF_BASE(_name, _id, _type, _parent...) \
0047     DEF_TYPE(_name, _id, _type, .parent = _parent)
0048
0049 #define DEF_INPUT(_name, _id) \
0050     DEF_TYPE(_name, _id, CLK_TYPE_IN)
0051 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \
0052     DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
0053 #define DEF_DIV6P1(_name, _id, _parent, _offset)    \
0054     DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
0055 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
0056     DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
0057 #define DEF_RATE(_name, _id, _rate) \
0058     DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
0059
0060     /*
0061      * Definitions of Module Clocks
0062      */
0063
0064 struct mssr_mod_clk {
0065     const char *name;
0066     unsigned int id;
0067     unsigned int parent;    /* Add MOD_CLK_BASE for Module Clocks */
0068 };
0069
0070 /* Convert from sparse base-100 to packed index space */
0071 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
0072
0073 #define MOD_CLK_ID(x)   (MOD_CLK_BASE + MOD_CLK_PACK(x))
0074
0075 #define DEF_MOD(_name, _mod, _parent...)    \
0076     { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
0077
0078 /* Convert from sparse base-10 to packed index space */
0079 #define MOD_CLK_PACK_10(x)  ((x / 10) * 32 + (x % 10))
0080
0081 #define MOD_CLK_ID_10(x)    (MOD_CLK_BASE + MOD_CLK_PACK_10(x))
0082
0083 #define DEF_MOD_STB(_name, _mod, _parent...)    \
0084     { .name = _name, .id = MOD_CLK_ID_10(_mod), .parent = _parent }
0085
0086 struct device_node;
0087
0088 enum clk_reg_layout {
0089     CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
0090     CLK_REG_LAYOUT_RZ_A,
0091     CLK_REG_LAYOUT_RCAR_GEN4,
0092 };
0093
0094     /**
0095      * SoC-specific CPG/MSSR Description
0096      *
0097      * @early_core_clks: Array of Early Core Clock definitions
0098      * @num_early_core_clks: Number of entries in early_core_clks[]
0099      * @early_mod_clks: Array of Early Module Clock definitions
0100      * @num_early_mod_clks: Number of entries in early_mod_clks[]
0101      *
0102      * @core_clks: Array of Core Clock definitions
0103      * @num_core_clks: Number of entries in core_clks[]
0104      * @last_dt_core_clk: ID of the last Core Clock exported to DT
0105      * @num_total_core_clks: Total number of Core Clocks (exported + internal)
0106      *
0107      * @mod_clks: Array of Module Clock definitions
0108      * @num_mod_clks: Number of entries in mod_clks[]
0109      * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
0110      *
0111      * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
0112      *                 should not be disabled without a knowledgeable driver
0113      * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
0114      * @reg_layout: CPG/MSSR register layout from enum clk_reg_layout
0115      *
0116      * @core_pm_clks: Array with IDs of Core Clocks that are suitable for Power
0117      *                Management, in addition to Module Clocks
0118      * @num_core_pm_clks: Number of entries in core_pm_clks[]
0119      *
0120      * @init: Optional callback to perform SoC-specific initialization
0121      * @cpg_clk_register: Optional callback to handle special Core Clock types
0122      */
0123
0124 struct cpg_mssr_info {
0125     /* Early Clocks */
0126     const struct cpg_core_clk *early_core_clks;
0127     unsigned int num_early_core_clks;
0128     const struct mssr_mod_clk *early_mod_clks;
0129     unsigned int num_early_mod_clks;
0130
0131     /* Core Clocks */
0132     const struct cpg_core_clk *core_clks;
0133     unsigned int num_core_clks;
0134     unsigned int last_dt_core_clk;
0135     unsigned int num_total_core_clks;
0136     enum clk_reg_layout reg_layout;
0137
0138     /* Module Clocks */
0139     const struct mssr_mod_clk *mod_clks;
0140     unsigned int num_mod_clks;
0141     unsigned int num_hw_mod_clks;
0142
0143     /* Critical Module Clocks that should not be disabled */
0144     const unsigned int *crit_mod_clks;
0145     unsigned int num_crit_mod_clks;
0146
0147     /* Core Clocks suitable for PM, in addition to the Module Clocks */
0148     const unsigned int *core_pm_clks;
0149     unsigned int num_core_pm_clks;
0150
0151     /* Callbacks */
0152     int (*init)(struct device *dev);
0153     struct clk *(*cpg_clk_register)(struct device *dev,
0154                     const struct cpg_core_clk *core,
0155                     const struct cpg_mssr_info *info,
0156                     struct clk **clks, void __iomem *base,
0157                     struct raw_notifier_head *notifiers);
0158 };
0159
0160 extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;
0161 extern const struct cpg_mssr_info r8a7742_cpg_mssr_info;
0162 extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
0163 extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
0164 extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
0165 extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info;
0166 extern const struct cpg_mssr_info r8a774b1_cpg_mssr_info;
0167 extern const struct cpg_mssr_info r8a774c0_cpg_mssr_info;
0168 extern const struct cpg_mssr_info r8a774e1_cpg_mssr_info;
0169 extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
0170 extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
0171 extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
0172 extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;
0173 extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
0174 extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
0175 extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
0176 extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
0177 extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
0178 extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
0179 extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
0180 extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;
0181 extern const struct cpg_mssr_info r8a779f0_cpg_mssr_info;
0182 extern const struct cpg_mssr_info r8a779g0_cpg_mssr_info;
0183
0184 void __init cpg_mssr_early_init(struct device_node *np,
0185                 const struct cpg_mssr_info *info);
0186
0187     /*
0188      * Helpers for fixing up clock tables depending on SoC revision
0189      */
0190
0191 struct mssr_mod_reparent {
0192     unsigned int clk, parent;
0193 };
0194
0195
0196 extern void cpg_core_nullify_range(struct cpg_core_clk *core_clks,
0197                    unsigned int num_core_clks,
0198                    unsigned int first_clk,
0199                    unsigned int last_clk);
0200 extern void mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
0201                  unsigned int num_mod_clks,
0202                  const unsigned int *clks, unsigned int n);
0203 extern void mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
0204                   unsigned int num_mod_clks,
0205                   const struct mssr_mod_reparent *clks,
0206                   unsigned int n);
0207 #endif