clk/renesas/rcar-gen4-cpg.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * R-Car Gen4 Clock Pulse Generator
0004  *
0005  * Copyright (C) 2021 Renesas Electronics Corp.
0006  *
0007  */
0008
0009 #ifndef __CLK_RENESAS_RCAR_GEN4_CPG_H__
0010 #define __CLK_RENESAS_RCAR_GEN4_CPG_H__
0011
0012 enum rcar_gen4_clk_types {
0013     CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM,
0014     CLK_TYPE_GEN4_PLL1,
0015     CLK_TYPE_GEN4_PLL2,
0016     CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
0017     CLK_TYPE_GEN4_PLL3,
0018     CLK_TYPE_GEN4_PLL5,
0019     CLK_TYPE_GEN4_PLL4,
0020     CLK_TYPE_GEN4_PLL6,
0021     CLK_TYPE_GEN4_SDSRC,
0022     CLK_TYPE_GEN4_SDH,
0023     CLK_TYPE_GEN4_SD,
0024     CLK_TYPE_GEN4_MDSEL,    /* Select parent/divider using mode pin */
0025     CLK_TYPE_GEN4_Z,
0026     CLK_TYPE_GEN4_OSC,  /* OSC EXTAL predivider and fixed divider */
0027     CLK_TYPE_GEN4_RPCSRC,
0028     CLK_TYPE_GEN4_RPC,
0029     CLK_TYPE_GEN4_RPCD2,
0030
0031     /* SoC specific definitions start here */
0032     CLK_TYPE_GEN4_SOC_BASE,
0033 };
0034
0035 #define DEF_GEN4_SDH(_name, _id, _parent, _offset)  \
0036     DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
0037
0038 #define DEF_GEN4_SD(_name, _id, _parent, _offset)   \
0039     DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
0040
0041 #define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
0042     DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL,   \
0043          (_parent0) << 16 | (_parent1),     \
0044          .div = (_div0) << 16 | (_div1), .offset = _md)
0045
0046 #define DEF_GEN4_OSC(_name, _id, _parent, _div)     \
0047     DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
0048
0049 #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset)   \
0050     DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
0051
0052 struct rcar_gen4_cpg_pll_config {
0053     u8 extal_div;
0054     u8 pll1_mult;
0055     u8 pll1_div;
0056     u8 pll2_mult;
0057     u8 pll2_div;
0058     u8 pll3_mult;
0059     u8 pll3_div;
0060     u8 pll4_mult;
0061     u8 pll4_div;
0062     u8 pll5_mult;
0063     u8 pll5_div;
0064     u8 pll6_mult;
0065     u8 pll6_div;
0066     u8 osc_prediv;
0067 };
0068
0069 #define CPG_RPCCKCR 0x874
0070 #define SD0CKCR1    0x8a4
0071
0072 struct clk *rcar_gen4_cpg_clk_register(struct device *dev,
0073     const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
0074     struct clk **clks, void __iomem *base,
0075     struct raw_notifier_head *notifiers);
0076 int rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
0077                unsigned int clk_extalr, u32 mode);
0078
0079 #endif