clk/renesas/rcar-gen3-cpg.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * R-Car Gen3 Clock Pulse Generator
0004  *
0005  * Copyright (C) 2015-2018 Glider bvba
0006  * Copyright (C) 2018 Renesas Electronics Corp.
0007  *
0008  */
0009
0010 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
0011 #define __CLK_RENESAS_RCAR_GEN3_CPG_H__
0012
0013 enum rcar_gen3_clk_types {
0014     CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
0015     CLK_TYPE_GEN3_PLL0,
0016     CLK_TYPE_GEN3_PLL1,
0017     CLK_TYPE_GEN3_PLL2,
0018     CLK_TYPE_GEN3_PLL3,
0019     CLK_TYPE_GEN3_PLL4,
0020     CLK_TYPE_GEN3_SDH,
0021     CLK_TYPE_GEN3_SD,
0022     CLK_TYPE_GEN3_R,
0023     CLK_TYPE_GEN3_MDSEL,    /* Select parent/divider using mode pin */
0024     CLK_TYPE_GEN3_Z,
0025     CLK_TYPE_GEN3_OSC,  /* OSC EXTAL predivider and fixed divider */
0026     CLK_TYPE_GEN3_RCKSEL,   /* Select parent/divider using RCKCR.CKSEL */
0027     CLK_TYPE_GEN3_RPCSRC,
0028     CLK_TYPE_GEN3_E3_RPCSRC,/* Select parent/divider using RPCCKCR.DIV */
0029     CLK_TYPE_GEN3_RPC,
0030     CLK_TYPE_GEN3_RPCD2,
0031
0032     /* SoC specific definitions start here */
0033     CLK_TYPE_GEN3_SOC_BASE,
0034 };
0035
0036 #define DEF_GEN3_SDH(_name, _id, _parent, _offset)  \
0037     DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
0038
0039 #define DEF_GEN3_SD(_name, _id, _parent, _offset)   \
0040     DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
0041
0042 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
0043     DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL,   \
0044          (_parent0) << 16 | (_parent1),     \
0045          .div = (_div0) << 16 | (_div1), .offset = _md)
0046
0047 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
0048             _div_clean) \
0049     DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
0050                _parent_clean, _div_clean)
0051
0052 #define DEF_GEN3_OSC(_name, _id, _parent, _div)     \
0053     DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
0054
0055 #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
0056     DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL,  \
0057          (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
0058
0059 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset)   \
0060     DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
0061
0062 #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \
0063     DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC,   \
0064          (_parent0) << 16 | (_parent1), .div = 8)
0065 #define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \
0066     DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC,   \
0067          (_parent0) << 16 | (_parent1), .div = 5)
0068
0069 struct rcar_gen3_cpg_pll_config {
0070     u8 extal_div;
0071     u8 pll1_mult;
0072     u8 pll1_div;
0073     u8 pll3_mult;
0074     u8 pll3_div;
0075     u8 osc_prediv;
0076 };
0077
0078 #define CPG_RPCCKCR 0x238
0079 #define CPG_RCKCR   0x240
0080
0081 struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
0082     const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
0083     struct clk **clks, void __iomem *base,
0084     struct raw_notifier_head *notifiers);
0085 int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
0086                unsigned int clk_extalr, u32 mode);
0087
0088 #endif