clk/renesas/rcar-gen3-cpg.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * R-Car Gen3 Clock Pulse Generator
0004  *
0005  * Copyright (C) 2015-2018 Glider bvba
0006  * Copyright (C) 2019 Renesas Electronics Corp.
0007  *
0008  * Based on clk-rcar-gen3.c
0009  *
0010  * Copyright (C) 2015 Renesas Electronics Corp.
0011  */
0012
0013 #include <linux/bug.h>
0014 #include <linux/bitfield.h>
0015 #include <linux/clk.h>
0016 #include <linux/clk-provider.h>
0017 #include <linux/device.h>
0018 #include <linux/err.h>
0019 #include <linux/init.h>
0020 #include <linux/io.h>
0021 #include <linux/pm.h>
0022 #include <linux/slab.h>
0023 #include <linux/sys_soc.h>
0024
0025 #include "renesas-cpg-mssr.h"
0026 #include "rcar-cpg-lib.h"
0027 #include "rcar-gen3-cpg.h"
0028
0029 #define CPG_PLLECR      0x00d0  /* PLL Enable Control Register */
0030
0031 #define CPG_PLLECR_PLLST(n) BIT(8 + (n))    /* PLLn Circuit Status */
0032
0033 #define CPG_PLL0CR      0x00d8  /* PLLn Control Registers */
0034 #define CPG_PLL2CR      0x002c
0035 #define CPG_PLL4CR      0x01f4
0036
0037 #define CPG_PLLnCR_STC_MASK GENMASK(30, 24) /* PLL Circuit Mult. Ratio */
0038
0039 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
0040
0041 /* PLL Clocks */
0042 struct cpg_pll_clk {
0043     struct clk_hw hw;
0044     void __iomem *pllcr_reg;
0045     void __iomem *pllecr_reg;
0046     unsigned int fixed_mult;
0047     u32 pllecr_pllst_mask;
0048 };
0049
0050 #define to_pll_clk(_hw)   container_of(_hw, struct cpg_pll_clk, hw)
0051
0052 static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw,
0053                          unsigned long parent_rate)
0054 {
0055     struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
0056     unsigned int mult;
0057     u32 val;
0058
0059     val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK;
0060     mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1;
0061
0062     return parent_rate * mult * pll_clk->fixed_mult;
0063 }
0064
0065 static int cpg_pll_clk_determine_rate(struct clk_hw *hw,
0066                       struct clk_rate_request *req)
0067 {
0068     struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
0069     unsigned int min_mult, max_mult, mult;
0070     unsigned long prate;
0071
0072     prate = req->best_parent_rate * pll_clk->fixed_mult;
0073     min_mult = max(div64_ul(req->min_rate, prate), 1ULL);
0074     max_mult = min(div64_ul(req->max_rate, prate), 128ULL);
0075     if (max_mult < min_mult)
0076         return -EINVAL;
0077
0078     mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
0079     mult = clamp(mult, min_mult, max_mult);
0080
0081     req->rate = prate * mult;
0082     return 0;
0083 }
0084
0085 static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
0086                 unsigned long parent_rate)
0087 {
0088     struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
0089     unsigned int mult, i;
0090     u32 val;
0091
0092     mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult);
0093     mult = clamp(mult, 1U, 128U);
0094
0095     val = readl(pll_clk->pllcr_reg);
0096     val &= ~CPG_PLLnCR_STC_MASK;
0097     val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK);
0098     writel(val, pll_clk->pllcr_reg);
0099
0100     for (i = 1000; i; i--) {
0101         if (readl(pll_clk->pllecr_reg) & pll_clk->pllecr_pllst_mask)
0102             return 0;
0103
0104         cpu_relax();
0105     }
0106
0107     return -ETIMEDOUT;
0108 }
0109
0110 static const struct clk_ops cpg_pll_clk_ops = {
0111     .recalc_rate = cpg_pll_clk_recalc_rate,
0112     .determine_rate = cpg_pll_clk_determine_rate,
0113     .set_rate = cpg_pll_clk_set_rate,
0114 };
0115
0116 static struct clk * __init cpg_pll_clk_register(const char *name,
0117                         const char *parent_name,
0118                         void __iomem *base,
0119                         unsigned int mult,
0120                         unsigned int offset,
0121                         unsigned int index)
0122
0123 {
0124     struct cpg_pll_clk *pll_clk;
0125     struct clk_init_data init = {};
0126     struct clk *clk;
0127
0128     pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
0129     if (!pll_clk)
0130         return ERR_PTR(-ENOMEM);
0131
0132     init.name = name;
0133     init.ops = &cpg_pll_clk_ops;
0134     init.parent_names = &parent_name;
0135     init.num_parents = 1;
0136
0137     pll_clk->hw.init = &init;
0138     pll_clk->pllcr_reg = base + offset;
0139     pll_clk->pllecr_reg = base + CPG_PLLECR;
0140     pll_clk->fixed_mult = mult; /* PLL refclk x (setting + 1) x mult */
0141     pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);
0142
0143     clk = clk_register(NULL, &pll_clk->hw);
0144     if (IS_ERR(clk))
0145         kfree(pll_clk);
0146
0147     return clk;
0148 }
0149
0150 /*
0151  * Z Clock & Z2 Clock
0152  *
0153  * Traits of this clock:
0154  * prepare - clk_prepare only ensures that parents are prepared
0155  * enable - clk_enable only ensures that parents are enabled
0156  * rate - rate is adjustable.
0157  *        clk->rate = (parent->rate * mult / 32 ) / fixed_div
0158  * parent - fixed parent.  No clk_set_parent support
0159  */
0160 #define CPG_FRQCRB          0x00000004
0161 #define CPG_FRQCRB_KICK         BIT(31)
0162 #define CPG_FRQCRC          0x000000e0
0163
0164 struct cpg_z_clk {
0165     struct clk_hw hw;
0166     void __iomem *reg;
0167     void __iomem *kick_reg;
0168     unsigned long max_rate;     /* Maximum rate for normal mode */
0169     unsigned int fixed_div;
0170     u32 mask;
0171 };
0172
0173 #define to_z_clk(_hw)   container_of(_hw, struct cpg_z_clk, hw)
0174
0175 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
0176                        unsigned long parent_rate)
0177 {
0178     struct cpg_z_clk *zclk = to_z_clk(hw);
0179     unsigned int mult;
0180     u32 val;
0181
0182     val = readl(zclk->reg) & zclk->mask;
0183     mult = 32 - (val >> __ffs(zclk->mask));
0184
0185     return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
0186                      32 * zclk->fixed_div);
0187 }
0188
0189 static int cpg_z_clk_determine_rate(struct clk_hw *hw,
0190                     struct clk_rate_request *req)
0191 {
0192     struct cpg_z_clk *zclk = to_z_clk(hw);
0193     unsigned int min_mult, max_mult, mult;
0194     unsigned long rate, prate;
0195
0196     rate = min(req->rate, req->max_rate);
0197     if (rate <= zclk->max_rate) {
0198         /* Set parent rate to initial value for normal modes */
0199         prate = zclk->max_rate;
0200     } else {
0201         /* Set increased parent rate for boost modes */
0202         prate = rate;
0203     }
0204     req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
0205                           prate * zclk->fixed_div);
0206
0207     prate = req->best_parent_rate / zclk->fixed_div;
0208     min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
0209     max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
0210     if (max_mult < min_mult)
0211         return -EINVAL;
0212
0213     mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
0214     mult = clamp(mult, min_mult, max_mult);
0215
0216     req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
0217     return 0;
0218 }
0219
0220 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
0221                   unsigned long parent_rate)
0222 {
0223     struct cpg_z_clk *zclk = to_z_clk(hw);
0224     unsigned int mult;
0225     unsigned int i;
0226
0227     mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
0228                        parent_rate);
0229     mult = clamp(mult, 1U, 32U);
0230
0231     if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
0232         return -EBUSY;
0233
0234     cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));
0235
0236     /*
0237      * Set KICK bit in FRQCRB to update hardware setting and wait for
0238      * clock change completion.
0239      */
0240     cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
0241
0242     /*
0243      * Note: There is no HW information about the worst case latency.
0244      *
0245      * Using experimental measurements, it seems that no more than
0246      * ~10 iterations are needed, independently of the CPU rate.
0247      * Since this value might be dependent on external xtal rate, pll1
0248      * rate or even the other emulation clocks rate, use 1000 as a
0249      * "super" safe value.
0250      */
0251     for (i = 1000; i; i--) {
0252         if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
0253             return 0;
0254
0255         cpu_relax();
0256     }
0257
0258     return -ETIMEDOUT;
0259 }
0260
0261 static const struct clk_ops cpg_z_clk_ops = {
0262     .recalc_rate = cpg_z_clk_recalc_rate,
0263     .determine_rate = cpg_z_clk_determine_rate,
0264     .set_rate = cpg_z_clk_set_rate,
0265 };
0266
0267 static struct clk * __init cpg_z_clk_register(const char *name,
0268                           const char *parent_name,
0269                           void __iomem *reg,
0270                           unsigned int div,
0271                           unsigned int offset)
0272 {
0273     struct clk_init_data init = {};
0274     struct cpg_z_clk *zclk;
0275     struct clk *clk;
0276
0277     zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
0278     if (!zclk)
0279         return ERR_PTR(-ENOMEM);
0280
0281     init.name = name;
0282     init.ops = &cpg_z_clk_ops;
0283     init.flags = CLK_SET_RATE_PARENT;
0284     init.parent_names = &parent_name;
0285     init.num_parents = 1;
0286
0287     zclk->reg = reg + CPG_FRQCRC;
0288     zclk->kick_reg = reg + CPG_FRQCRB;
0289     zclk->hw.init = &init;
0290     zclk->mask = GENMASK(offset + 4, offset);
0291     zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
0292
0293     clk = clk_register(NULL, &zclk->hw);
0294     if (IS_ERR(clk)) {
0295         kfree(zclk);
0296         return clk;
0297     }
0298
0299     zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
0300              zclk->fixed_div;
0301     return clk;
0302 }
0303
0304 static const struct clk_div_table cpg_rpcsrc_div_table[] = {
0305     { 2, 5 }, { 3, 6 }, { 0, 0 },
0306 };
0307
0308 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
0309 static unsigned int cpg_clk_extalr __initdata;
0310 static u32 cpg_mode __initdata;
0311 static u32 cpg_quirks __initdata;
0312
0313 #define PLL_ERRATA  BIT(0)      /* Missing PLL0/2/4 post-divider */
0314 #define RCKCR_CKSEL BIT(1)      /* Manual RCLK parent selection */
0315
0316
0317 static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
0318     {
0319         .soc_id = "r8a7795", .revision = "ES1.0",
0320         .data = (void *)(PLL_ERRATA | RCKCR_CKSEL),
0321     },
0322     {
0323         .soc_id = "r8a7795", .revision = "ES1.*",
0324         .data = (void *)(RCKCR_CKSEL),
0325     },
0326     {
0327         .soc_id = "r8a7796", .revision = "ES1.0",
0328         .data = (void *)(RCKCR_CKSEL),
0329     },
0330     { /* sentinel */ }
0331 };
0332
0333 struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
0334     const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
0335     struct clk **clks, void __iomem *base,
0336     struct raw_notifier_head *notifiers)
0337 {
0338     const struct clk *parent;
0339     unsigned int mult = 1;
0340     unsigned int div = 1;
0341     u32 value;
0342
0343     parent = clks[core->parent & 0xffff];   /* some types use high bits */
0344     if (IS_ERR(parent))
0345         return ERR_CAST(parent);
0346
0347     switch (core->type) {
0348     case CLK_TYPE_GEN3_MAIN:
0349         div = cpg_pll_config->extal_div;
0350         break;
0351
0352     case CLK_TYPE_GEN3_PLL0:
0353         /*
0354          * PLL0 is implemented as a custom clock, to change the
0355          * multiplier when cpufreq changes between normal and boost
0356          * modes.
0357          */
0358         mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2;
0359         return cpg_pll_clk_register(core->name, __clk_get_name(parent),
0360                         base, mult, CPG_PLL0CR, 0);
0361
0362     case CLK_TYPE_GEN3_PLL1:
0363         mult = cpg_pll_config->pll1_mult;
0364         div = cpg_pll_config->pll1_div;
0365         break;
0366
0367     case CLK_TYPE_GEN3_PLL2:
0368         /*
0369          * PLL2 is implemented as a custom clock, to change the
0370          * multiplier when cpufreq changes between normal and boost
0371          * modes.
0372          */
0373         mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2;
0374         return cpg_pll_clk_register(core->name, __clk_get_name(parent),
0375                         base, mult, CPG_PLL2CR, 2);
0376
0377     case CLK_TYPE_GEN3_PLL3:
0378         mult = cpg_pll_config->pll3_mult;
0379         div = cpg_pll_config->pll3_div;
0380         break;
0381
0382     case CLK_TYPE_GEN3_PLL4:
0383         /*
0384          * PLL4 is a configurable multiplier clock. Register it as a
0385          * fixed factor clock for now as there's no generic multiplier
0386          * clock implementation and we currently have no need to change
0387          * the multiplier value.
0388          */
0389         value = readl(base + CPG_PLL4CR);
0390         mult = (((value >> 24) & 0x7f) + 1) * 2;
0391         if (cpg_quirks & PLL_ERRATA)
0392             mult *= 2;
0393         break;
0394
0395     case CLK_TYPE_GEN3_SDH:
0396         return cpg_sdh_clk_register(core->name, base + core->offset,
0397                        __clk_get_name(parent), notifiers);
0398
0399     case CLK_TYPE_GEN3_SD:
0400         return cpg_sd_clk_register(core->name, base + core->offset,
0401                        __clk_get_name(parent));
0402
0403     case CLK_TYPE_GEN3_R:
0404         if (cpg_quirks & RCKCR_CKSEL) {
0405             struct cpg_simple_notifier *csn;
0406
0407             csn = kzalloc(sizeof(*csn), GFP_KERNEL);
0408             if (!csn)
0409                 return ERR_PTR(-ENOMEM);
0410
0411             csn->reg = base + CPG_RCKCR;
0412
0413             /*
0414              * RINT is default.
0415              * Only if EXTALR is populated, we switch to it.
0416              */
0417             value = readl(csn->reg) & 0x3f;
0418
0419             if (clk_get_rate(clks[cpg_clk_extalr])) {
0420                 parent = clks[cpg_clk_extalr];
0421                 value |= CPG_RCKCR_CKSEL;
0422             }
0423
0424             writel(value, csn->reg);
0425             cpg_simple_notifier_register(notifiers, csn);
0426             break;
0427         }
0428
0429         /* Select parent clock of RCLK by MD28 */
0430         if (cpg_mode & BIT(28))
0431             parent = clks[cpg_clk_extalr];
0432         break;
0433
0434     case CLK_TYPE_GEN3_MDSEL:
0435         /*
0436          * Clock selectable between two parents and two fixed dividers
0437          * using a mode pin
0438          */
0439         if (cpg_mode & BIT(core->offset)) {
0440             div = core->div & 0xffff;
0441         } else {
0442             parent = clks[core->parent >> 16];
0443             if (IS_ERR(parent))
0444                 return ERR_CAST(parent);
0445             div = core->div >> 16;
0446         }
0447         mult = 1;
0448         break;
0449
0450     case CLK_TYPE_GEN3_Z:
0451         return cpg_z_clk_register(core->name, __clk_get_name(parent),
0452                       base, core->div, core->offset);
0453
0454     case CLK_TYPE_GEN3_OSC:
0455         /*
0456          * Clock combining OSC EXTAL predivider and a fixed divider
0457          */
0458         div = cpg_pll_config->osc_prediv * core->div;
0459         break;
0460
0461     case CLK_TYPE_GEN3_RCKSEL:
0462         /*
0463          * Clock selectable between two parents and two fixed dividers
0464          * using RCKCR.CKSEL
0465          */
0466         if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) {
0467             div = core->div & 0xffff;
0468         } else {
0469             parent = clks[core->parent >> 16];
0470             if (IS_ERR(parent))
0471                 return ERR_CAST(parent);
0472             div = core->div >> 16;
0473         }
0474         break;
0475
0476     case CLK_TYPE_GEN3_RPCSRC:
0477         return clk_register_divider_table(NULL, core->name,
0478                           __clk_get_name(parent), 0,
0479                           base + CPG_RPCCKCR, 3, 2, 0,
0480                           cpg_rpcsrc_div_table,
0481                           &cpg_lock);
0482
0483     case CLK_TYPE_GEN3_E3_RPCSRC:
0484         /*
0485          * Register RPCSRC as fixed factor clock based on the
0486          * MD[4:1] pins and CPG_RPCCKCR[4:3] register value for
0487          * which has been set prior to booting the kernel.
0488          */
0489         value = (readl(base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;
0490
0491         switch (value) {
0492         case 0:
0493             div = 5;
0494             break;
0495         case 1:
0496             div = 3;
0497             break;
0498         case 2:
0499             parent = clks[core->parent >> 16];
0500             if (IS_ERR(parent))
0501                 return ERR_CAST(parent);
0502             div = core->div;
0503             break;
0504         case 3:
0505         default:
0506             div = 2;
0507             break;
0508         }
0509         break;
0510
0511     case CLK_TYPE_GEN3_RPC:
0512         return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR,
0513                         __clk_get_name(parent), notifiers);
0514
0515     case CLK_TYPE_GEN3_RPCD2:
0516         return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,
0517                           __clk_get_name(parent));
0518
0519     default:
0520         return ERR_PTR(-EINVAL);
0521     }
0522
0523     return clk_register_fixed_factor(NULL, core->name,
0524                      __clk_get_name(parent), 0, mult, div);
0525 }
0526
0527 int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
0528                   unsigned int clk_extalr, u32 mode)
0529 {
0530     const struct soc_device_attribute *attr;
0531
0532     cpg_pll_config = config;
0533     cpg_clk_extalr = clk_extalr;
0534     cpg_mode = mode;
0535     attr = soc_device_match(cpg_quirks_match);
0536     if (attr)
0537         cpg_quirks = (uintptr_t)attr->data;
0538     pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
0539
0540     spin_lock_init(&cpg_lock);
0541
0542     return 0;
0543 }