clk/renesas/rcar-gen2-cpg.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * R-Car Gen2 Clock Pulse Generator
0004  *
0005  * Copyright (C) 2016 Cogent Embedded Inc.
0006  */
0007
0008 #ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
0009 #define __CLK_RENESAS_RCAR_GEN2_CPG_H__
0010
0011 enum rcar_gen2_clk_types {
0012     CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM,
0013     CLK_TYPE_GEN2_PLL0,
0014     CLK_TYPE_GEN2_PLL1,
0015     CLK_TYPE_GEN2_PLL3,
0016     CLK_TYPE_GEN2_Z,
0017     CLK_TYPE_GEN2_LB,
0018     CLK_TYPE_GEN2_ADSP,
0019     CLK_TYPE_GEN2_SDH,
0020     CLK_TYPE_GEN2_SD0,
0021     CLK_TYPE_GEN2_SD1,
0022     CLK_TYPE_GEN2_QSPI,
0023     CLK_TYPE_GEN2_RCAN,
0024 };
0025
0026 struct rcar_gen2_cpg_pll_config {
0027     u8 extal_div;
0028     u8 pll1_mult;
0029     u8 pll3_mult;
0030     u8 pll0_mult;       /* leave as zero if PLL0CR exists */
0031 };
0032
0033 struct clk *rcar_gen2_cpg_clk_register(struct device *dev,
0034     const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
0035     struct clk **clks, void __iomem *base,
0036     struct raw_notifier_head *notifiers);
0037 int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
0038                unsigned int pll0_div, u32 mode);
0039
0040 #endif