clk/renesas/r9a07g043-cpg.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * RZ/G2UL CPG driver
0004  *
0005  * Copyright (C) 2022 Renesas Electronics Corp.
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/device.h>
0010 #include <linux/init.h>
0011 #include <linux/kernel.h>
0012
0013 #include <dt-bindings/clock/r9a07g043-cpg.h>
0014
0015 #include "rzg2l-cpg.h"
0016
0017 enum clk_ids {
0018     /* Core Clock Outputs exported to DT */
0019     LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2,
0020
0021     /* External Input Clocks */
0022     CLK_EXTAL,
0023
0024     /* Internal Core Clocks */
0025     CLK_OSC_DIV1000,
0026     CLK_PLL1,
0027     CLK_PLL2,
0028     CLK_PLL2_DIV2,
0029     CLK_PLL2_DIV2_8,
0030     CLK_PLL2_DIV2_10,
0031     CLK_PLL3,
0032     CLK_PLL3_400,
0033     CLK_PLL3_533,
0034     CLK_PLL3_DIV2,
0035     CLK_PLL3_DIV2_4,
0036     CLK_PLL3_DIV2_4_2,
0037     CLK_SEL_PLL3_3,
0038     CLK_DIV_PLL3_C,
0039 #ifdef CONFIG_ARM64
0040     CLK_PLL5,
0041     CLK_PLL5_500,
0042     CLK_PLL5_250,
0043 #endif
0044     CLK_PLL6,
0045     CLK_PLL6_250,
0046     CLK_P1_DIV2,
0047     CLK_PLL2_800,
0048     CLK_PLL2_SDHI_533,
0049     CLK_PLL2_SDHI_400,
0050     CLK_PLL2_SDHI_266,
0051     CLK_SD0_DIV4,
0052     CLK_SD1_DIV4,
0053
0054     /* Module Clocks */
0055     MOD_CLK_BASE,
0056 };
0057
0058 /* Divider tables */
0059 static const struct clk_div_table dtable_1_8[] = {
0060     {0, 1},
0061     {1, 2},
0062     {2, 4},
0063     {3, 8},
0064     {0, 0},
0065 };
0066
0067 static const struct clk_div_table dtable_1_32[] = {
0068     {0, 1},
0069     {1, 2},
0070     {2, 4},
0071     {3, 8},
0072     {4, 32},
0073     {0, 0},
0074 };
0075
0076 /* Mux clock tables */
0077 static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
0078 static const char * const sel_pll6_2[]  = { ".pll6_250", ".pll5_250" };
0079 static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
0080
0081 static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
0082     /* External Clock Inputs */
0083     DEF_INPUT("extal", CLK_EXTAL),
0084
0085     /* Internal Core Clocks */
0086     DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1),
0087     DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
0088     DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
0089     DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
0090     DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
0091     DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
0092     DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),
0093     DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
0094     DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
0095     DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
0096     DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
0097     DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
0098     DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
0099     DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
0100     DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
0101     DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
0102     DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
0103     DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),
0104     DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
0105 #ifdef CONFIG_ARM64
0106     DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
0107     DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6),
0108     DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2),
0109 #endif
0110     DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
0111     DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
0112
0113     /* Core output clk */
0114     DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
0115     DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32),
0116     DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2),
0117     DEF_FIXED("TSU", R9A07G043_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
0118     DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32),
0119     DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2),
0120     DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
0121     DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
0122     DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
0123     DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),
0124     DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
0125     DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
0126     DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, sel_shdi),
0127     DEF_SD_MUX("SD1", R9A07G043_CLK_SD1, SEL_SDHI1, sel_shdi),
0128     DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4),
0129     DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4),
0130 };
0131
0132 static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0133 #ifdef CONFIG_ARM64
0134     DEF_MOD("gic",      R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
0135                 0x514, 0),
0136     DEF_MOD("ia55_pclk",    R9A07G043_IA55_PCLK, R9A07G043_CLK_P2,
0137                 0x518, 0),
0138     DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1,
0139                 0x518, 1),
0140 #endif
0141 #ifdef CONFIG_RISCV
0142     DEF_MOD("iax45_pclk",   R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2,
0143                 0x518, 0),
0144     DEF_MOD("iax45_clk",    R9A07G043_IAX45_CLK, R9A07G043_CLK_P1,
0145                 0x518, 1),
0146 #endif
0147     DEF_MOD("dmac_aclk",    R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1,
0148                 0x52c, 0),
0149     DEF_MOD("dmac_pclk",    R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
0150                 0x52c, 1),
0151     DEF_MOD("ostm0_pclk",   R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0,
0152                 0x534, 0),
0153     DEF_MOD("ostm1_pclk",   R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0,
0154                 0x534, 1),
0155     DEF_MOD("ostm2_pclk",   R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
0156                 0x534, 2),
0157     DEF_MOD("wdt0_pclk",    R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0,
0158                 0x548, 0),
0159     DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
0160                 0x548, 1),
0161     DEF_MOD("wdt2_pclk",    R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0,
0162                 0x548, 4),
0163     DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK,
0164                 0x548, 5),
0165     DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,
0166                 0x550, 0),
0167     DEF_MOD("spi_clk",  R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,
0168                 0x550, 1),
0169     DEF_MOD("sdhi0_imclk",  R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4,
0170                 0x554, 0),
0171     DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4,
0172                 0x554, 1),
0173     DEF_MOD("sdhi0_clk_hs", R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0,
0174                 0x554, 2),
0175     DEF_MOD("sdhi0_aclk",   R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1,
0176                 0x554, 3),
0177     DEF_MOD("sdhi1_imclk",  R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4,
0178                 0x554, 4),
0179     DEF_MOD("sdhi1_imclk2", R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4,
0180                 0x554, 5),
0181     DEF_MOD("sdhi1_clk_hs", R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1,
0182                 0x554, 6),
0183     DEF_MOD("sdhi1_aclk",   R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1,
0184                 0x554, 7),
0185     DEF_MOD("ssi0_pclk",    R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0,
0186                 0x570, 0),
0187     DEF_MOD("ssi0_sfr", R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0,
0188                 0x570, 1),
0189     DEF_MOD("ssi1_pclk",    R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0,
0190                 0x570, 2),
0191     DEF_MOD("ssi1_sfr", R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0,
0192                 0x570, 3),
0193     DEF_MOD("ssi2_pclk",    R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0,
0194                 0x570, 4),
0195     DEF_MOD("ssi2_sfr", R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0,
0196                 0x570, 5),
0197     DEF_MOD("ssi3_pclk",    R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0,
0198                 0x570, 6),
0199     DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0,
0200                 0x570, 7),
0201     DEF_MOD("usb0_host",    R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1,
0202                 0x578, 0),
0203     DEF_MOD("usb1_host",    R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1,
0204                 0x578, 1),
0205     DEF_MOD("usb0_func",    R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1,
0206                 0x578, 2),
0207     DEF_MOD("usb_pclk", R9A07G043_USB_PCLK, R9A07G043_CLK_P1,
0208                 0x578, 3),
0209     DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0,
0210                 0x57c, 0),
0211     DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT,
0212                 0x57c, 0),
0213     DEF_COUPLED("eth1_axi", R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0,
0214                 0x57c, 1),
0215     DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT,
0216                 0x57c, 1),
0217     DEF_MOD("i2c0",     R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0,
0218                 0x580, 0),
0219     DEF_MOD("i2c1",     R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0,
0220                 0x580, 1),
0221     DEF_MOD("i2c2",     R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0,
0222                 0x580, 2),
0223     DEF_MOD("i2c3",     R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0,
0224                 0x580, 3),
0225     DEF_MOD("scif0",    R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0,
0226                 0x584, 0),
0227     DEF_MOD("scif1",    R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0,
0228                 0x584, 1),
0229     DEF_MOD("scif2",    R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0,
0230                 0x584, 2),
0231     DEF_MOD("scif3",    R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0,
0232                 0x584, 3),
0233     DEF_MOD("scif4",    R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0,
0234                 0x584, 4),
0235     DEF_MOD("sci0",     R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0,
0236                 0x588, 0),
0237     DEF_MOD("sci1",     R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0,
0238                 0x588, 1),
0239     DEF_MOD("rspi0",    R9A07G043_RSPI0_CLKB, R9A07G043_CLK_P0,
0240                 0x590, 0),
0241     DEF_MOD("rspi1",    R9A07G043_RSPI1_CLKB, R9A07G043_CLK_P0,
0242                 0x590, 1),
0243     DEF_MOD("rspi2",    R9A07G043_RSPI2_CLKB, R9A07G043_CLK_P0,
0244                 0x590, 2),
0245     DEF_MOD("canfd",    R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0,
0246                 0x594, 0),
0247     DEF_MOD("gpio",     R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,
0248                 0x598, 0),
0249     DEF_MOD("adc_adclk",    R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU,
0250                 0x5a8, 0),
0251     DEF_MOD("adc_pclk", R9A07G043_ADC_PCLK, R9A07G043_CLK_P0,
0252                 0x5a8, 1),
0253     DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU,
0254                 0x5ac, 0),
0255 };
0256
0257 static struct rzg2l_reset r9a07g043_resets[] = {
0258 #ifdef CONFIG_ARM64
0259     DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
0260     DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
0261     DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
0262 #endif
0263 #ifdef CONFIG_RISCV
0264     DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0),
0265 #endif
0266     DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
0267     DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
0268     DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
0269     DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
0270     DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
0271     DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
0272     DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2),
0273     DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
0274     DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
0275     DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
0276     DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),
0277     DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1),
0278     DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2),
0279     DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3),
0280     DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0),
0281     DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1),
0282     DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2),
0283     DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3),
0284     DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
0285     DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
0286     DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),
0287     DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1),
0288     DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2),
0289     DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3),
0290     DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0),
0291     DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1),
0292     DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2),
0293     DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3),
0294     DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),
0295     DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),
0296     DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),
0297     DEF_RST(R9A07G043_RSPI0_RST, 0x890, 0),
0298     DEF_RST(R9A07G043_RSPI1_RST, 0x890, 1),
0299     DEF_RST(R9A07G043_RSPI2_RST, 0x890, 2),
0300     DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0),
0301     DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1),
0302     DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),
0303     DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1),
0304     DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2),
0305     DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0),
0306     DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1),
0307     DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),
0308 };
0309
0310 static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
0311 #ifdef CONFIG_ARM64
0312     MOD_CLK_BASE + R9A07G043_GIC600_GICCLK,
0313     MOD_CLK_BASE + R9A07G043_IA55_CLK,
0314 #endif
0315 #ifdef CONFIG_RISCV
0316     MOD_CLK_BASE + R9A07G043_IAX45_CLK,
0317 #endif
0318     MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
0319 };
0320
0321 const struct rzg2l_cpg_info r9a07g043_cpg_info = {
0322     /* Core Clocks */
0323     .core_clks = r9a07g043_core_clks,
0324     .num_core_clks = ARRAY_SIZE(r9a07g043_core_clks),
0325     .last_dt_core_clk = LAST_DT_CORE_CLK,
0326     .num_total_core_clks = MOD_CLK_BASE,
0327
0328     /* Critical Module Clocks */
0329     .crit_mod_clks = r9a07g043_crit_mod_clks,
0330     .num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks),
0331
0332     /* Module Clocks */
0333     .mod_clks = r9a07g043_mod_clks,
0334     .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks),
0335 #ifdef CONFIG_ARM64
0336     .num_hw_mod_clks = R9A07G043_TSU_PCLK + 1,
0337 #endif
0338 #ifdef CONFIG_RISCV
0339     .num_hw_mod_clks = R9A07G043_IAX45_PCLK + 1,
0340 #endif
0341
0342     /* Resets */
0343     .resets = r9a07g043_resets,
0344 #ifdef CONFIG_ARM64
0345     .num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */
0346 #endif
0347 #ifdef CONFIG_RISCV
0348     .num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */
0349 #endif
0350
0351     .has_clk_mon_regs = true,
0352 };