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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * R9A06G032 clock driver
0004  *
0005  * Copyright (C) 2018 Renesas Electronics Europe Limited
0006  *
0007  * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
0008  */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/clk-provider.h>
0012 #include <linux/delay.h>
0013 #include <linux/init.h>
0014 #include <linux/io.h>
0015 #include <linux/kernel.h>
0016 #include <linux/math64.h>
0017 #include <linux/of.h>
0018 #include <linux/of_address.h>
0019 #include <linux/of_platform.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/pm_clock.h>
0022 #include <linux/pm_domain.h>
0023 #include <linux/slab.h>
0024 #include <linux/soc/renesas/r9a06g032-sysctrl.h>
0025 #include <linux/spinlock.h>
0026 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
0027 
0028 #define R9A06G032_SYSCTRL_DMAMUX 0xA0
0029 
0030 struct r9a06g032_gate {
0031     u16 gate, reset, ready, midle,
0032         scon, mirack, mistat;
0033 };
0034 
0035 /* This is used to describe a clock for instantiation */
0036 struct r9a06g032_clkdesc {
0037     const char *name;
0038     uint32_t managed: 1;
0039     uint32_t type: 3;
0040     uint32_t index: 8;
0041     uint32_t source : 8; /* source index + 1 (0 == none) */
0042     /* these are used to populate the bitsel struct */
0043     union {
0044         struct r9a06g032_gate gate;
0045         /* for dividers */
0046         struct {
0047             unsigned int div_min : 10, div_max : 10, reg: 10;
0048             u16 div_table[4];
0049         };
0050         /* For fixed-factor ones */
0051         struct {
0052             u16 div, mul;
0053         };
0054         /* for dual gate */
0055         struct {
0056             uint16_t group : 1;
0057             u16 sel, g1, r1, g2, r2;
0058         } dual;
0059     };
0060 };
0061 
0062 #define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \
0063     { .gate = _clk, .reset = _rst, \
0064         .ready = _rdy, .midle = _midle, \
0065         .scon = _scon, .mirack = _mirack, .mistat = _mistat }
0066 #define D_GATE(_idx, _n, _src, ...) \
0067     { .type = K_GATE, .index = R9A06G032_##_idx, \
0068         .source = 1 + R9A06G032_##_src, .name = _n, \
0069         .gate = I_GATE(__VA_ARGS__) }
0070 #define D_MODULE(_idx, _n, _src, ...) \
0071     { .type = K_GATE, .index = R9A06G032_##_idx, \
0072         .source = 1 + R9A06G032_##_src, .name = _n, \
0073         .managed = 1, .gate = I_GATE(__VA_ARGS__) }
0074 #define D_ROOT(_idx, _n, _mul, _div) \
0075     { .type = K_FFC, .index = R9A06G032_##_idx, .name = _n, \
0076         .div = _div, .mul = _mul }
0077 #define D_FFC(_idx, _n, _src, _div) \
0078     { .type = K_FFC, .index = R9A06G032_##_idx, \
0079         .source = 1 + R9A06G032_##_src, .name = _n, \
0080         .div = _div, .mul = 1}
0081 #define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \
0082     { .type = K_DIV, .index = R9A06G032_##_idx, \
0083         .source = 1 + R9A06G032_##_src, .name = _n, \
0084         .reg = _reg, .div_min = _min, .div_max = _max, \
0085         .div_table = { __VA_ARGS__ } }
0086 #define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \
0087     { .type = K_DUALGATE, .index = R9A06G032_##_idx, \
0088         .source = 1 + R9A06G032_##_src, .name = _n, \
0089         .dual = { .group = _g, \
0090             .g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
0091 
0092 enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
0093 
0094 /* Internal clock IDs */
0095 #define R9A06G032_CLKOUT        0
0096 #define R9A06G032_CLKOUT_D10        2
0097 #define R9A06G032_CLKOUT_D16        3
0098 #define R9A06G032_CLKOUT_D160       4
0099 #define R9A06G032_CLKOUT_D1OR2      5
0100 #define R9A06G032_CLKOUT_D20        6
0101 #define R9A06G032_CLKOUT_D40        7
0102 #define R9A06G032_CLKOUT_D5     8
0103 #define R9A06G032_CLKOUT_D8     9
0104 #define R9A06G032_DIV_ADC       10
0105 #define R9A06G032_DIV_I2C       11
0106 #define R9A06G032_DIV_NAND      12
0107 #define R9A06G032_DIV_P1_PG     13
0108 #define R9A06G032_DIV_P2_PG     14
0109 #define R9A06G032_DIV_P3_PG     15
0110 #define R9A06G032_DIV_P4_PG     16
0111 #define R9A06G032_DIV_P5_PG     17
0112 #define R9A06G032_DIV_P6_PG     18
0113 #define R9A06G032_DIV_QSPI0     19
0114 #define R9A06G032_DIV_QSPI1     20
0115 #define R9A06G032_DIV_REF_SYNC      21
0116 #define R9A06G032_DIV_SDIO0     22
0117 #define R9A06G032_DIV_SDIO1     23
0118 #define R9A06G032_DIV_SWITCH        24
0119 #define R9A06G032_DIV_UART      25
0120 #define R9A06G032_DIV_MOTOR     64
0121 #define R9A06G032_CLK_DDRPHY_PLLCLK_D4  78
0122 #define R9A06G032_CLK_ECAT100_D4    79
0123 #define R9A06G032_CLK_HSR100_D2     80
0124 #define R9A06G032_CLK_REF_SYNC_D4   81
0125 #define R9A06G032_CLK_REF_SYNC_D8   82
0126 #define R9A06G032_CLK_SERCOS100_D2  83
0127 #define R9A06G032_DIV_CA7       84
0128 
0129 #define R9A06G032_UART_GROUP_012    154
0130 #define R9A06G032_UART_GROUP_34567  155
0131 
0132 #define R9A06G032_CLOCK_COUNT       (R9A06G032_UART_GROUP_34567 + 1)
0133 
0134 static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
0135     D_ROOT(CLKOUT, "clkout", 25, 1),
0136     D_ROOT(CLK_PLL_USB, "clk_pll_usb", 12, 10),
0137     D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10),
0138     D_FFC(CLKOUT_D16, "clkout_d16", CLKOUT, 16),
0139     D_FFC(CLKOUT_D160, "clkout_d160", CLKOUT, 160),
0140     D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
0141     D_FFC(CLKOUT_D20, "clkout_d20", CLKOUT, 20),
0142     D_FFC(CLKOUT_D40, "clkout_d40", CLKOUT, 40),
0143     D_FFC(CLKOUT_D5, "clkout_d5", CLKOUT, 5),
0144     D_FFC(CLKOUT_D8, "clkout_d8", CLKOUT, 8),
0145     D_DIV(DIV_ADC, "div_adc", CLKOUT, 77, 50, 250),
0146     D_DIV(DIV_I2C, "div_i2c", CLKOUT, 78, 12, 16),
0147     D_DIV(DIV_NAND, "div_nand", CLKOUT, 82, 12, 32),
0148     D_DIV(DIV_P1_PG, "div_p1_pg", CLKOUT, 68, 12, 200),
0149     D_DIV(DIV_P2_PG, "div_p2_pg", CLKOUT, 62, 12, 128),
0150     D_DIV(DIV_P3_PG, "div_p3_pg", CLKOUT, 64, 8, 128),
0151     D_DIV(DIV_P4_PG, "div_p4_pg", CLKOUT, 66, 8, 128),
0152     D_DIV(DIV_P5_PG, "div_p5_pg", CLKOUT, 71, 10, 40),
0153     D_DIV(DIV_P6_PG, "div_p6_pg", CLKOUT, 18, 12, 64),
0154     D_DIV(DIV_QSPI0, "div_qspi0", CLKOUT, 73, 3, 7),
0155     D_DIV(DIV_QSPI1, "div_qspi1", CLKOUT, 25, 3, 7),
0156     D_DIV(DIV_REF_SYNC, "div_ref_sync", CLKOUT, 56, 2, 16, 2, 4, 8, 16),
0157     D_DIV(DIV_SDIO0, "div_sdio0", CLKOUT, 74, 20, 128),
0158     D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128),
0159     D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40),
0160     D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128),
0161     D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, 0x749, 0x74a, 0x74b, 0, 0xae3, 0, 0),
0162     D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, 0x74c, 0x74d, 0x74e, 0, 0xae4, 0, 0),
0163     D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, 0x74f, 0x750, 0x751, 0, 0xae5, 0, 0),
0164     D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, 0x752, 0x753, 0x754, 0, 0xae6, 0, 0),
0165     D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, 0x755, 0x756, 0x757, 0, 0xae7, 0, 0),
0166     D_GATE(CLK_ADC, "clk_adc", DIV_ADC, 0x1ea, 0x1eb, 0, 0, 0, 0, 0),
0167     D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, 0x405, 0, 0, 0, 0, 0, 0),
0168     D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, 0x483, 0, 0, 0, 0, 0, 0),
0169     D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, 0x1e6, 0x1e7, 0, 0, 0, 0, 0),
0170     D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, 0x1e8, 0x1e9, 0, 0, 0, 0, 0),
0171     D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, 0x342, 0, 0, 0, 0, 0, 0),
0172     D_GATE(CLK_NAND, "clk_nand", DIV_NAND, 0x284, 0x285, 0, 0, 0, 0, 0),
0173     D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, 0x774, 0x775, 0, 0, 0, 0, 0),
0174     D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, 0x862, 0x863, 0, 0, 0, 0, 0),
0175     D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, 0x864, 0x865, 0, 0, 0, 0, 0),
0176     D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, 0x866, 0x867, 0, 0, 0, 0, 0),
0177     D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, 0x824, 0x825, 0, 0, 0, 0, 0),
0178     D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, 0x826, 0x827, 0, 0, 0, 0, 0),
0179     D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, 0x8a0, 0x8a1, 0x8a2, 0, 0xb60, 0, 0),
0180     D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0),
0181     D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0),
0182     D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0),
0183     D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, 0xe6, 0, 0, 0, 0, 0, 0),
0184     D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0),
0185     D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0),
0186     D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0),
0187     D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, 0x341, 0, 0, 0, 0, 0, 0),
0188     D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, 0x64, 0, 0, 0, 0, 0, 0),
0189     D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, 0x644, 0, 0, 0, 0, 0, 0),
0190     D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, 0x425, 0, 0, 0, 0, 0, 0),
0191     D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, 0x860, 0x861, 0, 0, 0, 0, 0),
0192     D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, 0x7e0, 0x7e1, 0, 0, 0, 0, 0),
0193     D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, 0x7e2, 0x7e3, 0, 0, 0, 0, 0),
0194     D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, 0x7e4, 0x7e5, 0, 0, 0, 0, 0),
0195     D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, 0x7e6, 0x7e7, 0, 0, 0, 0, 0),
0196     D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, 0x820, 0x821, 0, 0, 0, 0, 0),
0197     D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, 0x822, 0x823, 0, 0, 0, 0, 0),
0198     D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, 0x982, 0x983, 0, 0, 0, 0, 0),
0199     D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8),
0200     D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, 0x400, 0x401, 0, 0x402, 0, 0x440, 0x441),
0201     D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, 0x740, 0x741, 0x742, 0, 0xae0, 0, 0),
0202     D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, 0x420, 0x422, 0, 0x421, 0, 0x460, 0x461),
0203     D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, 0x8c3, 0x8c4, 0x8c5, 0, 0xb41, 0, 0),
0204     D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, 0x8c6, 0x8c7, 0x8c8, 0, 0xb42, 0, 0),
0205     D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, 0x8c9, 0x8ca, 0x8cb, 0, 0xb43, 0, 0),
0206     D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, 0x743, 0x744, 0x745, 0, 0xae1, 0, 0),
0207     D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, 0x746, 0x747, 0x748, 0, 0xae2, 0, 0),
0208     D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, 0xe3, 0, 0, 0xe4, 0, 0x102, 0x103),
0209     D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, 0xe0, 0xe1, 0, 0xe2, 0, 0x100, 0x101),
0210     D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, 0xe5, 0, 0, 0, 0, 0, 0),
0211     D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, 0x78c, 0x78d, 0, 0x78e, 0, 0xb04, 0xb05),
0212     D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, 0x789, 0x78a, 0x78b, 0, 0xb03, 0, 0),
0213     D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4),
0214     D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4),
0215     D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2),
0216     D_FFC(CLK_REF_SYNC_D4, "clk_ref_sync_d4", CLK_REF_SYNC, 4),
0217     D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8),
0218     D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2),
0219     D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4),
0220     D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, 0x783, 0x784, 0x785, 0, 0xb01, 0, 0),
0221     D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, 0x786, 0x787, 0x788, 0, 0xb02, 0, 0),
0222     D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, 0x1ef, 0x1f0, 0x1f1, 0, 0, 0, 0),
0223     D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, 0x1ec, 0x1ed, 0x1ee, 0, 0, 0, 0),
0224     D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, 0x780, 0x781, 0x782, 0, 0xb00, 0, 0),
0225     D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, 0x1e0, 0x1e1, 0x1e2, 0, 0, 0, 0),
0226     D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, 0x1e3, 0x1e4, 0x1e5, 0, 0, 0, 0),
0227     D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640),
0228     D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, 0xba0, 0xba1, 0, 0xba2, 0, 0xbc0, 0xbc1),
0229     D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, 0x323, 0x324, 0, 0, 0, 0, 0),
0230     D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, 0x403, 0x404, 0, 0, 0, 0, 0),
0231     D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, 0x484, 0x485, 0, 0, 0, 0, 0),
0232     D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, 0xc60, 0xc61, 0, 0, 0, 0, 0),
0233     D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, 0x424, 0x423, 0, 0, 0, 0, 0),
0234     D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, 0x1af, 0x1b0, 0x1b1, 0, 0, 0, 0),
0235     D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, 0xc20, 0xc21, 0xc22, 0, 0, 0, 0),
0236     D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, 0x123, 0x124, 0x125, 0, 0x142, 0, 0),
0237     D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, 0x120, 0x121, 0, 0x122, 0, 0x140, 0x141),
0238     D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, 0x320, 0x322, 0, 0x321, 0, 0x3a0, 0x3a1),
0239     D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, 0x260, 0x261, 0x262, 0x263, 0x2c0, 0x2c1, 0x2c2),
0240     D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, 0x264, 0x265, 0x266, 0x267, 0x2c3, 0x2c4, 0x2c5),
0241     D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, 0x360, 0x361, 0x362, 0x363, 0x3c0, 0x3c1, 0x3c2),
0242     D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, 0x380, 0x381, 0x382, 0x383, 0x3e0, 0x3e1, 0x3e2),
0243     D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, 0x212, 0x213, 0x214, 0, 0, 0, 0),
0244     D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, 0x215, 0x216, 0x217, 0, 0, 0, 0),
0245     D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, 0x229, 0x22a, 0x22b, 0, 0, 0, 0),
0246     D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, 0x480, 0x482, 0, 0x481, 0, 0x4c0, 0x4c1),
0247     D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, 0x1a9, 0x1aa, 0x1ab, 0, 0, 0, 0),
0248     D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, 0x1ac, 0x1ad, 0x1ae, 0, 0, 0, 0),
0249     D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, 0x7a0, 0x7a1, 0x7a2, 0, 0xb20, 0, 0),
0250     D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, 0x164, 0x165, 0x166, 0, 0x183, 0, 0),
0251     D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, 0x160, 0x161, 0x162, 0x163, 0x180, 0x181, 0x182),
0252     D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, 0x280, 0x281, 0x282, 0x283, 0x2e0, 0x2e1, 0x2e2),
0253     D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, 0x7ac, 0x7ad, 0, 0x7ae, 0, 0xb24, 0xb25),
0254     D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, 0x22c, 0x22d, 0x22e, 0, 0, 0, 0),
0255     D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, 0x22f, 0x230, 0x231, 0, 0, 0, 0),
0256     D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, 0x7a6, 0x7a7, 0x7a8, 0, 0xb22, 0, 0),
0257     D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, 0x7a9, 0x7aa, 0x7ab, 0, 0xb23, 0, 0),
0258     D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, 0x2a0, 0x2a1, 0x2a2, 0x2a3, 0x300, 0x301, 0x302),
0259     D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, 0x480, 0x481, 0x482, 0x483, 0x4c0, 0x4c1, 0x4c2),
0260     D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0),
0261     D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0xa03, 0, 0xa02, 0, 0, 0),
0262     D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, 0x60, 0x61, 0x62, 0x63, 0x80, 0x81, 0x82),
0263     D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, 0x640, 0x641, 0x642, 0x643, 0x660, 0x661, 0x662),
0264     D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, 0x7a3, 0x7a4, 0x7a5, 0, 0xb21, 0, 0),
0265     D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, 0x200, 0x201, 0x202, 0, 0, 0, 0),
0266     D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, 0x203, 0x204, 0x205, 0, 0, 0, 0),
0267     D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, 0x206, 0x207, 0x208, 0, 0, 0, 0),
0268     D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, 0x209, 0x20a, 0x20b, 0, 0, 0, 0),
0269     D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, 0x20c, 0x20d, 0x20e, 0, 0, 0, 0),
0270     D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, 0x20f, 0x210, 0x211, 0, 0, 0, 0),
0271     D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, 0x980, 0, 0x981, 0, 0, 0, 0),
0272     D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, 0xc40, 0xc41, 0xc42, 0, 0, 0, 0),
0273     D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, 0x1a0, 0x1a1, 0x1a2, 0, 0, 0, 0),
0274     D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, 0x1a3, 0x1a4, 0x1a5, 0, 0, 0, 0),
0275     D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, 0x1a6, 0x1a7, 0x1a8, 0, 0, 0, 0),
0276     D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, 0x218, 0x219, 0x21a, 0, 0, 0, 0),
0277     D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, 0x21b, 0x21c, 0x21d, 0, 0, 0, 0),
0278     D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, 0x220, 0x221, 0x222, 0, 0, 0, 0),
0279     D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, 0x223, 0x224, 0x225, 0, 0, 0, 0),
0280     D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, 0x226, 0x227, 0x228, 0, 0, 0, 0),
0281     /*
0282      * These are not hardware clocks, but are needed to handle the special
0283      * case where we have a 'selector bit' that doesn't just change the
0284      * parent for a clock, but also the gate it's supposed to use.
0285      */
0286     {
0287         .index = R9A06G032_UART_GROUP_012,
0288         .name = "uart_group_012",
0289         .type = K_BITSEL,
0290         .source = 1 + R9A06G032_DIV_UART,
0291         /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
0292         .dual.sel = ((0x34 / 4) << 5) | 30,
0293         .dual.group = 0,
0294     },
0295     {
0296         .index = R9A06G032_UART_GROUP_34567,
0297         .name = "uart_group_34567",
0298         .type = K_BITSEL,
0299         .source = 1 + R9A06G032_DIV_P2_PG,
0300         /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
0301         .dual.sel = ((0xec / 4) << 5) | 24,
0302         .dual.group = 1,
0303     },
0304     D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
0305     D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
0306     D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
0307     D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0x760, 0x761, 0x762, 0x763),
0308     D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 0x764, 0x765, 0x766, 0x767),
0309     D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 0x768, 0x769, 0x76a, 0x76b),
0310     D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 0x76c, 0x76d, 0x76e, 0x76f),
0311     D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 0x770, 0x771, 0x772, 0x773),
0312 };
0313 
0314 struct r9a06g032_priv {
0315     struct clk_onecell_data data;
0316     spinlock_t lock; /* protects concurrent access to gates */
0317     void __iomem *reg;
0318 };
0319 
0320 static struct r9a06g032_priv *sysctrl_priv;
0321 
0322 /* Exported helper to access the DMAMUX register */
0323 int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val)
0324 {
0325     unsigned long flags;
0326     u32 dmamux;
0327 
0328     if (!sysctrl_priv)
0329         return -EPROBE_DEFER;
0330 
0331     spin_lock_irqsave(&sysctrl_priv->lock, flags);
0332 
0333     dmamux = readl(sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX);
0334     dmamux &= ~mask;
0335     dmamux |= val & mask;
0336     writel(dmamux, sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX);
0337 
0338     spin_unlock_irqrestore(&sysctrl_priv->lock, flags);
0339 
0340     return 0;
0341 }
0342 EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_set_dmamux);
0343 
0344 /* register/bit pairs are encoded as an uint16_t */
0345 static void
0346 clk_rdesc_set(struct r9a06g032_priv *clocks,
0347           u16 one, unsigned int on)
0348 {
0349     u32 __iomem *reg = clocks->reg + (4 * (one >> 5));
0350     u32 val = readl(reg);
0351 
0352     val = (val & ~(1U << (one & 0x1f))) | ((!!on) << (one & 0x1f));
0353     writel(val, reg);
0354 }
0355 
0356 static int
0357 clk_rdesc_get(struct r9a06g032_priv *clocks,
0358           uint16_t one)
0359 {
0360     u32 __iomem *reg = clocks->reg + (4 * (one >> 5));
0361     u32 val = readl(reg);
0362 
0363     return !!(val & (1U << (one & 0x1f)));
0364 }
0365 
0366 /*
0367  * This implements the R9A06G032 clock gate 'driver'. We cannot use the system's
0368  * clock gate framework as the gates on the R9A06G032 have a special enabling
0369  * sequence, therefore we use this little proxy.
0370  */
0371 struct r9a06g032_clk_gate {
0372     struct clk_hw hw;
0373     struct r9a06g032_priv *clocks;
0374     u16 index;
0375 
0376     struct r9a06g032_gate gate;
0377 };
0378 
0379 #define to_r9a06g032_gate(_hw) container_of(_hw, struct r9a06g032_clk_gate, hw)
0380 
0381 static int create_add_module_clock(struct of_phandle_args *clkspec,
0382                    struct device *dev)
0383 {
0384     struct clk *clk;
0385     int error;
0386 
0387     clk = of_clk_get_from_provider(clkspec);
0388     if (IS_ERR(clk))
0389         return PTR_ERR(clk);
0390 
0391     error = pm_clk_create(dev);
0392     if (error) {
0393         clk_put(clk);
0394         return error;
0395     }
0396 
0397     error = pm_clk_add_clk(dev, clk);
0398     if (error) {
0399         pm_clk_destroy(dev);
0400         clk_put(clk);
0401     }
0402 
0403     return error;
0404 }
0405 
0406 static int r9a06g032_attach_dev(struct generic_pm_domain *pd,
0407                 struct device *dev)
0408 {
0409     struct device_node *np = dev->of_node;
0410     struct of_phandle_args clkspec;
0411     int i = 0;
0412     int error;
0413     int index;
0414 
0415     while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
0416                        &clkspec)) {
0417         if (clkspec.np != pd->dev.of_node)
0418             continue;
0419 
0420         index = clkspec.args[0];
0421         if (index < R9A06G032_CLOCK_COUNT &&
0422             r9a06g032_clocks[index].managed) {
0423             error = create_add_module_clock(&clkspec, dev);
0424             of_node_put(clkspec.np);
0425             if (error)
0426                 return error;
0427         }
0428         i++;
0429     }
0430 
0431     return 0;
0432 }
0433 
0434 static void r9a06g032_detach_dev(struct generic_pm_domain *unused, struct device *dev)
0435 {
0436     if (!pm_clk_no_clocks(dev))
0437         pm_clk_destroy(dev);
0438 }
0439 
0440 static int r9a06g032_add_clk_domain(struct device *dev)
0441 {
0442     struct device_node *np = dev->of_node;
0443     struct generic_pm_domain *pd;
0444 
0445     pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
0446     if (!pd)
0447         return -ENOMEM;
0448 
0449     pd->name = np->name;
0450     pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
0451             GENPD_FLAG_ACTIVE_WAKEUP;
0452     pd->attach_dev = r9a06g032_attach_dev;
0453     pd->detach_dev = r9a06g032_detach_dev;
0454     pm_genpd_init(pd, &pm_domain_always_on_gov, false);
0455 
0456     of_genpd_add_provider_simple(np, pd);
0457     return 0;
0458 }
0459 
0460 static void
0461 r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks,
0462                struct r9a06g032_gate *g, int on)
0463 {
0464     unsigned long flags;
0465 
0466     WARN_ON(!g->gate);
0467 
0468     spin_lock_irqsave(&clocks->lock, flags);
0469     clk_rdesc_set(clocks, g->gate, on);
0470     /* De-assert reset */
0471     if (g->reset)
0472         clk_rdesc_set(clocks, g->reset, 1);
0473     spin_unlock_irqrestore(&clocks->lock, flags);
0474 
0475     /* Hardware manual recommends 5us delay after enabling clock & reset */
0476     udelay(5);
0477 
0478     /* If the peripheral is memory mapped (i.e. an AXI slave), there is an
0479      * associated SLVRDY bit in the System Controller that needs to be set
0480      * so that the FlexWAY bus fabric passes on the read/write requests.
0481      */
0482     if (g->ready || g->midle) {
0483         spin_lock_irqsave(&clocks->lock, flags);
0484         if (g->ready)
0485             clk_rdesc_set(clocks, g->ready, on);
0486         /* Clear 'Master Idle Request' bit */
0487         if (g->midle)
0488             clk_rdesc_set(clocks, g->midle, !on);
0489         spin_unlock_irqrestore(&clocks->lock, flags);
0490     }
0491     /* Note: We don't wait for FlexWAY Socket Connection signal */
0492 }
0493 
0494 static int r9a06g032_clk_gate_enable(struct clk_hw *hw)
0495 {
0496     struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
0497 
0498     r9a06g032_clk_gate_set(g->clocks, &g->gate, 1);
0499     return 0;
0500 }
0501 
0502 static void r9a06g032_clk_gate_disable(struct clk_hw *hw)
0503 {
0504     struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
0505 
0506     r9a06g032_clk_gate_set(g->clocks, &g->gate, 0);
0507 }
0508 
0509 static int r9a06g032_clk_gate_is_enabled(struct clk_hw *hw)
0510 {
0511     struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
0512 
0513     /* if clock is in reset, the gate might be on, and still not 'be' on */
0514     if (g->gate.reset && !clk_rdesc_get(g->clocks, g->gate.reset))
0515         return 0;
0516 
0517     return clk_rdesc_get(g->clocks, g->gate.gate);
0518 }
0519 
0520 static const struct clk_ops r9a06g032_clk_gate_ops = {
0521     .enable = r9a06g032_clk_gate_enable,
0522     .disable = r9a06g032_clk_gate_disable,
0523     .is_enabled = r9a06g032_clk_gate_is_enabled,
0524 };
0525 
0526 static struct clk *
0527 r9a06g032_register_gate(struct r9a06g032_priv *clocks,
0528             const char *parent_name,
0529             const struct r9a06g032_clkdesc *desc)
0530 {
0531     struct clk *clk;
0532     struct r9a06g032_clk_gate *g;
0533     struct clk_init_data init = {};
0534 
0535     g = kzalloc(sizeof(*g), GFP_KERNEL);
0536     if (!g)
0537         return NULL;
0538 
0539     init.name = desc->name;
0540     init.ops = &r9a06g032_clk_gate_ops;
0541     init.flags = CLK_SET_RATE_PARENT;
0542     init.parent_names = parent_name ? &parent_name : NULL;
0543     init.num_parents = parent_name ? 1 : 0;
0544 
0545     g->clocks = clocks;
0546     g->index = desc->index;
0547     g->gate = desc->gate;
0548     g->hw.init = &init;
0549 
0550     /*
0551      * important here, some clocks are already in use by the CM3, we
0552      * have to assume they are not Linux's to play with and try to disable
0553      * at the end of the boot!
0554      */
0555     if (r9a06g032_clk_gate_is_enabled(&g->hw)) {
0556         init.flags |= CLK_IS_CRITICAL;
0557         pr_debug("%s was enabled, making read-only\n", desc->name);
0558     }
0559 
0560     clk = clk_register(NULL, &g->hw);
0561     if (IS_ERR(clk)) {
0562         kfree(g);
0563         return NULL;
0564     }
0565     return clk;
0566 }
0567 
0568 struct r9a06g032_clk_div {
0569     struct clk_hw hw;
0570     struct r9a06g032_priv *clocks;
0571     u16 index;
0572     u16 reg;
0573     u16 min, max;
0574     u8 table_size;
0575     u16 table[8];   /* we know there are no more than 8 */
0576 };
0577 
0578 #define to_r9a06g032_div(_hw) \
0579         container_of(_hw, struct r9a06g032_clk_div, hw)
0580 
0581 static unsigned long
0582 r9a06g032_div_recalc_rate(struct clk_hw *hw,
0583               unsigned long parent_rate)
0584 {
0585     struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
0586     u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
0587     u32 div = readl(reg);
0588 
0589     if (div < clk->min)
0590         div = clk->min;
0591     else if (div > clk->max)
0592         div = clk->max;
0593     return DIV_ROUND_UP(parent_rate, div);
0594 }
0595 
0596 /*
0597  * Attempts to find a value that is in range of min,max,
0598  * and if a table of set dividers was specified for this
0599  * register, try to find the fixed divider that is the closest
0600  * to the target frequency
0601  */
0602 static long
0603 r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk,
0604             unsigned long rate, unsigned long prate)
0605 {
0606     /* + 1 to cope with rates that have the remainder dropped */
0607     u32 div = DIV_ROUND_UP(prate, rate + 1);
0608     int i;
0609 
0610     if (div <= clk->min)
0611         return clk->min;
0612     if (div >= clk->max)
0613         return clk->max;
0614 
0615     for (i = 0; clk->table_size && i < clk->table_size - 1; i++) {
0616         if (div >= clk->table[i] && div <= clk->table[i + 1]) {
0617             unsigned long m = rate -
0618                 DIV_ROUND_UP(prate, clk->table[i]);
0619             unsigned long p =
0620                 DIV_ROUND_UP(prate, clk->table[i + 1]) -
0621                 rate;
0622             /*
0623              * select the divider that generates
0624              * the value closest to the ideal frequency
0625              */
0626             div = p >= m ? clk->table[i] : clk->table[i + 1];
0627             return div;
0628         }
0629     }
0630     return div;
0631 }
0632 
0633 static int
0634 r9a06g032_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
0635 {
0636     struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
0637     u32 div = DIV_ROUND_UP(req->best_parent_rate, req->rate);
0638 
0639     pr_devel("%s %pC %ld (prate %ld) (wanted div %u)\n", __func__,
0640          hw->clk, req->rate, req->best_parent_rate, div);
0641     pr_devel("   min %d (%ld) max %d (%ld)\n",
0642          clk->min, DIV_ROUND_UP(req->best_parent_rate, clk->min),
0643          clk->max, DIV_ROUND_UP(req->best_parent_rate, clk->max));
0644 
0645     div = r9a06g032_div_clamp_div(clk, req->rate, req->best_parent_rate);
0646     /*
0647      * this is a hack. Currently the serial driver asks for a clock rate
0648      * that is 16 times the baud rate -- and that is wildly outside the
0649      * range of the UART divider, somehow there is no provision for that
0650      * case of 'let the divider as is if outside range'.
0651      * The serial driver *shouldn't* play with these clocks anyway, there's
0652      * several uarts attached to this divider, and changing this impacts
0653      * everyone.
0654      */
0655     if (clk->index == R9A06G032_DIV_UART ||
0656         clk->index == R9A06G032_DIV_P2_PG) {
0657         pr_devel("%s div uart hack!\n", __func__);
0658         req->rate = clk_get_rate(hw->clk);
0659         return 0;
0660     }
0661     req->rate = DIV_ROUND_UP(req->best_parent_rate, div);
0662     pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk,
0663          req->best_parent_rate, div, req->rate);
0664     return 0;
0665 }
0666 
0667 static int
0668 r9a06g032_div_set_rate(struct clk_hw *hw,
0669                unsigned long rate, unsigned long parent_rate)
0670 {
0671     struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
0672     /* + 1 to cope with rates that have the remainder dropped */
0673     u32 div = DIV_ROUND_UP(parent_rate, rate + 1);
0674     u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
0675 
0676     pr_devel("%s %pC rate %ld parent %ld div %d\n", __func__, hw->clk,
0677          rate, parent_rate, div);
0678 
0679     /*
0680      * Need to write the bit 31 with the divider value to
0681      * latch it. Technically we should wait until it has been
0682      * cleared too.
0683      * TODO: Find whether this callback is sleepable, in case
0684      * the hardware /does/ require some sort of spinloop here.
0685      */
0686     writel(div | BIT(31), reg);
0687 
0688     return 0;
0689 }
0690 
0691 static const struct clk_ops r9a06g032_clk_div_ops = {
0692     .recalc_rate = r9a06g032_div_recalc_rate,
0693     .determine_rate = r9a06g032_div_determine_rate,
0694     .set_rate = r9a06g032_div_set_rate,
0695 };
0696 
0697 static struct clk *
0698 r9a06g032_register_div(struct r9a06g032_priv *clocks,
0699                const char *parent_name,
0700                const struct r9a06g032_clkdesc *desc)
0701 {
0702     struct r9a06g032_clk_div *div;
0703     struct clk *clk;
0704     struct clk_init_data init = {};
0705     unsigned int i;
0706 
0707     div = kzalloc(sizeof(*div), GFP_KERNEL);
0708     if (!div)
0709         return NULL;
0710 
0711     init.name = desc->name;
0712     init.ops = &r9a06g032_clk_div_ops;
0713     init.flags = CLK_SET_RATE_PARENT;
0714     init.parent_names = parent_name ? &parent_name : NULL;
0715     init.num_parents = parent_name ? 1 : 0;
0716 
0717     div->clocks = clocks;
0718     div->index = desc->index;
0719     div->reg = desc->reg;
0720     div->hw.init = &init;
0721     div->min = desc->div_min;
0722     div->max = desc->div_max;
0723     /* populate (optional) divider table fixed values */
0724     for (i = 0; i < ARRAY_SIZE(div->table) &&
0725          i < ARRAY_SIZE(desc->div_table) && desc->div_table[i]; i++) {
0726         div->table[div->table_size++] = desc->div_table[i];
0727     }
0728 
0729     clk = clk_register(NULL, &div->hw);
0730     if (IS_ERR(clk)) {
0731         kfree(div);
0732         return NULL;
0733     }
0734     return clk;
0735 }
0736 
0737 /*
0738  * This clock provider handles the case of the R9A06G032 where you have
0739  * peripherals that have two potential clock source and two gates, one for
0740  * each of the clock source - the used clock source (for all sub clocks)
0741  * is selected by a single bit.
0742  * That single bit affects all sub-clocks, and therefore needs to change the
0743  * active gate (and turn the others off) and force a recalculation of the rates.
0744  *
0745  * This implements two clock providers, one 'bitselect' that
0746  * handles the switch between both parents, and another 'dualgate'
0747  * that knows which gate to poke at, depending on the parent's bit position.
0748  */
0749 struct r9a06g032_clk_bitsel {
0750     struct clk_hw   hw;
0751     struct r9a06g032_priv *clocks;
0752     u16 index;
0753     u16 selector;       /* selector register + bit */
0754 };
0755 
0756 #define to_clk_bitselect(_hw) \
0757         container_of(_hw, struct r9a06g032_clk_bitsel, hw)
0758 
0759 static u8 r9a06g032_clk_mux_get_parent(struct clk_hw *hw)
0760 {
0761     struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw);
0762 
0763     return clk_rdesc_get(set->clocks, set->selector);
0764 }
0765 
0766 static int r9a06g032_clk_mux_set_parent(struct clk_hw *hw, u8 index)
0767 {
0768     struct r9a06g032_clk_bitsel *set = to_clk_bitselect(hw);
0769 
0770     /* a single bit in the register selects one of two parent clocks */
0771     clk_rdesc_set(set->clocks, set->selector, !!index);
0772 
0773     return 0;
0774 }
0775 
0776 static const struct clk_ops clk_bitselect_ops = {
0777     .get_parent = r9a06g032_clk_mux_get_parent,
0778     .set_parent = r9a06g032_clk_mux_set_parent,
0779 };
0780 
0781 static struct clk *
0782 r9a06g032_register_bitsel(struct r9a06g032_priv *clocks,
0783               const char *parent_name,
0784               const struct r9a06g032_clkdesc *desc)
0785 {
0786     struct clk *clk;
0787     struct r9a06g032_clk_bitsel *g;
0788     struct clk_init_data init = {};
0789     const char *names[2];
0790 
0791     /* allocate the gate */
0792     g = kzalloc(sizeof(*g), GFP_KERNEL);
0793     if (!g)
0794         return NULL;
0795 
0796     names[0] = parent_name;
0797     names[1] = "clk_pll_usb";
0798 
0799     init.name = desc->name;
0800     init.ops = &clk_bitselect_ops;
0801     init.flags = CLK_SET_RATE_PARENT;
0802     init.parent_names = names;
0803     init.num_parents = 2;
0804 
0805     g->clocks = clocks;
0806     g->index = desc->index;
0807     g->selector = desc->dual.sel;
0808     g->hw.init = &init;
0809 
0810     clk = clk_register(NULL, &g->hw);
0811     if (IS_ERR(clk)) {
0812         kfree(g);
0813         return NULL;
0814     }
0815     return clk;
0816 }
0817 
0818 struct r9a06g032_clk_dualgate {
0819     struct clk_hw   hw;
0820     struct r9a06g032_priv *clocks;
0821     u16 index;
0822     u16 selector;       /* selector register + bit */
0823     struct r9a06g032_gate gate[2];
0824 };
0825 
0826 #define to_clk_dualgate(_hw) \
0827         container_of(_hw, struct r9a06g032_clk_dualgate, hw)
0828 
0829 static int
0830 r9a06g032_clk_dualgate_setenable(struct r9a06g032_clk_dualgate *g, int enable)
0831 {
0832     u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
0833 
0834     /* we always turn off the 'other' gate, regardless */
0835     r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0);
0836     r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable);
0837 
0838     return 0;
0839 }
0840 
0841 static int r9a06g032_clk_dualgate_enable(struct clk_hw *hw)
0842 {
0843     struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
0844 
0845     r9a06g032_clk_dualgate_setenable(gate, 1);
0846 
0847     return 0;
0848 }
0849 
0850 static void r9a06g032_clk_dualgate_disable(struct clk_hw *hw)
0851 {
0852     struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
0853 
0854     r9a06g032_clk_dualgate_setenable(gate, 0);
0855 }
0856 
0857 static int r9a06g032_clk_dualgate_is_enabled(struct clk_hw *hw)
0858 {
0859     struct r9a06g032_clk_dualgate *g = to_clk_dualgate(hw);
0860     u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
0861 
0862     return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate);
0863 }
0864 
0865 static const struct clk_ops r9a06g032_clk_dualgate_ops = {
0866     .enable = r9a06g032_clk_dualgate_enable,
0867     .disable = r9a06g032_clk_dualgate_disable,
0868     .is_enabled = r9a06g032_clk_dualgate_is_enabled,
0869 };
0870 
0871 static struct clk *
0872 r9a06g032_register_dualgate(struct r9a06g032_priv *clocks,
0873                 const char *parent_name,
0874                 const struct r9a06g032_clkdesc *desc,
0875                 uint16_t sel)
0876 {
0877     struct r9a06g032_clk_dualgate *g;
0878     struct clk *clk;
0879     struct clk_init_data init = {};
0880 
0881     /* allocate the gate */
0882     g = kzalloc(sizeof(*g), GFP_KERNEL);
0883     if (!g)
0884         return NULL;
0885     g->clocks = clocks;
0886     g->index = desc->index;
0887     g->selector = sel;
0888     g->gate[0].gate = desc->dual.g1;
0889     g->gate[0].reset = desc->dual.r1;
0890     g->gate[1].gate = desc->dual.g2;
0891     g->gate[1].reset = desc->dual.r2;
0892 
0893     init.name = desc->name;
0894     init.ops = &r9a06g032_clk_dualgate_ops;
0895     init.flags = CLK_SET_RATE_PARENT;
0896     init.parent_names = &parent_name;
0897     init.num_parents = 1;
0898     g->hw.init = &init;
0899     /*
0900      * important here, some clocks are already in use by the CM3, we
0901      * have to assume they are not Linux's to play with and try to disable
0902      * at the end of the boot!
0903      */
0904     if (r9a06g032_clk_dualgate_is_enabled(&g->hw)) {
0905         init.flags |= CLK_IS_CRITICAL;
0906         pr_debug("%s was enabled, making read-only\n", desc->name);
0907     }
0908 
0909     clk = clk_register(NULL, &g->hw);
0910     if (IS_ERR(clk)) {
0911         kfree(g);
0912         return NULL;
0913     }
0914     return clk;
0915 }
0916 
0917 static void r9a06g032_clocks_del_clk_provider(void *data)
0918 {
0919     of_clk_del_provider(data);
0920 }
0921 
0922 static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
0923 {
0924     struct device *dev = &pdev->dev;
0925     struct device_node *np = dev->of_node;
0926     struct r9a06g032_priv *clocks;
0927     struct clk **clks;
0928     struct clk *mclk;
0929     unsigned int i;
0930     u16 uart_group_sel[2];
0931     int error;
0932 
0933     clocks = devm_kzalloc(dev, sizeof(*clocks), GFP_KERNEL);
0934     clks = devm_kcalloc(dev, R9A06G032_CLOCK_COUNT, sizeof(struct clk *),
0935                 GFP_KERNEL);
0936     if (!clocks || !clks)
0937         return -ENOMEM;
0938 
0939     spin_lock_init(&clocks->lock);
0940 
0941     clocks->data.clks = clks;
0942     clocks->data.clk_num = R9A06G032_CLOCK_COUNT;
0943 
0944     mclk = devm_clk_get(dev, "mclk");
0945     if (IS_ERR(mclk))
0946         return PTR_ERR(mclk);
0947 
0948     clocks->reg = of_iomap(np, 0);
0949     if (WARN_ON(!clocks->reg))
0950         return -ENOMEM;
0951     for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) {
0952         const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i];
0953         const char *parent_name = d->source ?
0954             __clk_get_name(clocks->data.clks[d->source - 1]) :
0955             __clk_get_name(mclk);
0956         struct clk *clk = NULL;
0957 
0958         switch (d->type) {
0959         case K_FFC:
0960             clk = clk_register_fixed_factor(NULL, d->name,
0961                             parent_name, 0,
0962                             d->mul, d->div);
0963             break;
0964         case K_GATE:
0965             clk = r9a06g032_register_gate(clocks, parent_name, d);
0966             break;
0967         case K_DIV:
0968             clk = r9a06g032_register_div(clocks, parent_name, d);
0969             break;
0970         case K_BITSEL:
0971             /* keep that selector register around */
0972             uart_group_sel[d->dual.group] = d->dual.sel;
0973             clk = r9a06g032_register_bitsel(clocks, parent_name, d);
0974             break;
0975         case K_DUALGATE:
0976             clk = r9a06g032_register_dualgate(clocks, parent_name,
0977                               d,
0978                               uart_group_sel[d->dual.group]);
0979             break;
0980         }
0981         clocks->data.clks[d->index] = clk;
0982     }
0983     error = of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data);
0984     if (error)
0985         return error;
0986 
0987     error = devm_add_action_or_reset(dev,
0988                     r9a06g032_clocks_del_clk_provider, np);
0989     if (error)
0990         return error;
0991 
0992     error = r9a06g032_add_clk_domain(dev);
0993     if (error)
0994         return error;
0995 
0996     sysctrl_priv = clocks;
0997 
0998     error = of_platform_populate(np, NULL, NULL, dev);
0999     if (error)
1000         dev_err(dev, "Failed to populate children (%d)\n", error);
1001 
1002     return 0;
1003 }
1004 
1005 static const struct of_device_id r9a06g032_match[] = {
1006     { .compatible = "renesas,r9a06g032-sysctrl" },
1007     { }
1008 };
1009 
1010 static struct platform_driver r9a06g032_clock_driver = {
1011     .driver     = {
1012         .name   = "renesas,r9a06g032-sysctrl",
1013         .of_match_table = r9a06g032_match,
1014     },
1015 };
1016 
1017 static int __init r9a06g032_clocks_init(void)
1018 {
1019     return platform_driver_probe(&r9a06g032_clock_driver,
1020             r9a06g032_clocks_probe);
1021 }
1022 
1023 subsys_initcall(r9a06g032_clocks_init);
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