clk/renesas/r8a779a0-cpg-mssr.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset
0004  *
0005  * Copyright (C) 2020 Renesas Electronics Corp.
0006  *
0007  * Based on r8a7795-cpg-mssr.c
0008  *
0009  * Copyright (C) 2015 Glider bvba
0010  * Copyright (C) 2015 Renesas Electronics Corp.
0011  */
0012
0013 #include <linux/bitfield.h>
0014 #include <linux/clk.h>
0015 #include <linux/clk-provider.h>
0016 #include <linux/device.h>
0017 #include <linux/err.h>
0018 #include <linux/init.h>
0019 #include <linux/kernel.h>
0020 #include <linux/soc/renesas/rcar-rst.h>
0021
0022 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
0023
0024 #include "renesas-cpg-mssr.h"
0025 #include "rcar-gen4-cpg.h"
0026
0027 enum clk_ids {
0028     /* Core Clock Outputs exported to DT */
0029     LAST_DT_CORE_CLK = R8A779A0_CLK_OSC,
0030
0031     /* External Input Clocks */
0032     CLK_EXTAL,
0033     CLK_EXTALR,
0034
0035     /* Internal Core Clocks */
0036     CLK_MAIN,
0037     CLK_PLL1,
0038     CLK_PLL20,
0039     CLK_PLL21,
0040     CLK_PLL30,
0041     CLK_PLL31,
0042     CLK_PLL5,
0043     CLK_PLL1_DIV2,
0044     CLK_PLL20_DIV2,
0045     CLK_PLL21_DIV2,
0046     CLK_PLL30_DIV2,
0047     CLK_PLL31_DIV2,
0048     CLK_PLL5_DIV2,
0049     CLK_PLL5_DIV4,
0050     CLK_S1,
0051     CLK_S3,
0052     CLK_SDSRC,
0053     CLK_RPCSRC,
0054     CLK_OCO,
0055
0056     /* Module Clocks */
0057     MOD_CLK_BASE
0058 };
0059
0060 #define DEF_PLL(_name, _id, _offset)    \
0061     DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
0062          .offset = _offset)
0063
0064 static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
0065     /* External Clock Inputs */
0066     DEF_INPUT("extal",  CLK_EXTAL),
0067     DEF_INPUT("extalr", CLK_EXTALR),
0068
0069     /* Internal Core Clocks */
0070     DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
0071     DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
0072     DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
0073     DEF_PLL(".pll20", CLK_PLL20,    0x0834),
0074     DEF_PLL(".pll21", CLK_PLL21,    0x0838),
0075     DEF_PLL(".pll30", CLK_PLL30,    0x083c),
0076     DEF_PLL(".pll31", CLK_PLL31,    0x0840),
0077
0078     DEF_FIXED(".pll1_div2",     CLK_PLL1_DIV2,  CLK_PLL1,   2, 1),
0079     DEF_FIXED(".pll20_div2",    CLK_PLL20_DIV2, CLK_PLL20,  2, 1),
0080     DEF_FIXED(".pll21_div2",    CLK_PLL21_DIV2, CLK_PLL21,  2, 1),
0081     DEF_FIXED(".pll30_div2",    CLK_PLL30_DIV2, CLK_PLL30,  2, 1),
0082     DEF_FIXED(".pll31_div2",    CLK_PLL31_DIV2, CLK_PLL31,  2, 1),
0083     DEF_FIXED(".pll5_div2",     CLK_PLL5_DIV2,  CLK_PLL5,   2, 1),
0084     DEF_FIXED(".pll5_div4",     CLK_PLL5_DIV4,  CLK_PLL5_DIV2,  2, 1),
0085     DEF_FIXED(".s1",        CLK_S1,     CLK_PLL1_DIV2,  2, 1),
0086     DEF_FIXED(".s3",        CLK_S3,     CLK_PLL1_DIV2,  4, 1),
0087     DEF_FIXED(".sdsrc",     CLK_SDSRC,  CLK_PLL5_DIV4,  1, 1),
0088
0089     DEF_RATE(".oco",        CLK_OCO,    32768),
0090
0091     DEF_BASE(".rpcsrc",     CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
0092
0093     /* Core Clock Outputs */
0094     DEF_GEN4_Z("z0",    R8A779A0_CLK_Z0,    CLK_TYPE_GEN4_Z,    CLK_PLL20,  2, 0),
0095     DEF_GEN4_Z("z1",    R8A779A0_CLK_Z1,    CLK_TYPE_GEN4_Z,    CLK_PLL21,  2, 8),
0096     DEF_FIXED("zx",     R8A779A0_CLK_ZX,    CLK_PLL20_DIV2, 2, 1),
0097     DEF_FIXED("s1d1",   R8A779A0_CLK_S1D1,  CLK_S1,     1, 1),
0098     DEF_FIXED("s1d2",   R8A779A0_CLK_S1D2,  CLK_S1,     2, 1),
0099     DEF_FIXED("s1d4",   R8A779A0_CLK_S1D4,  CLK_S1,     4, 1),
0100     DEF_FIXED("s1d8",   R8A779A0_CLK_S1D8,  CLK_S1,     8, 1),
0101     DEF_FIXED("s1d12",  R8A779A0_CLK_S1D12, CLK_S1,     12, 1),
0102     DEF_FIXED("s3d1",   R8A779A0_CLK_S3D1,  CLK_S3,     1, 1),
0103     DEF_FIXED("s3d2",   R8A779A0_CLK_S3D2,  CLK_S3,     2, 1),
0104     DEF_FIXED("s3d4",   R8A779A0_CLK_S3D4,  CLK_S3,     4, 1),
0105     DEF_FIXED("zs",     R8A779A0_CLK_ZS,    CLK_PLL1_DIV2,  4, 1),
0106     DEF_FIXED("zt",     R8A779A0_CLK_ZT,    CLK_PLL1_DIV2,  2, 1),
0107     DEF_FIXED("ztr",    R8A779A0_CLK_ZTR,   CLK_PLL1_DIV2,  2, 1),
0108     DEF_FIXED("zr",     R8A779A0_CLK_ZR,    CLK_PLL1_DIV2,  1, 1),
0109     DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP,    CLK_PLL5_DIV4,  1, 1),
0110     DEF_FIXED("vip",    R8A779A0_CLK_VIP,   CLK_PLL5,   5, 1),
0111     DEF_FIXED("adgh",   R8A779A0_CLK_ADGH,  CLK_PLL5_DIV4,  1, 1),
0112     DEF_FIXED("icu",    R8A779A0_CLK_ICU,   CLK_PLL5_DIV4,  2, 1),
0113     DEF_FIXED("icud2",  R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4,  4, 1),
0114     DEF_FIXED("vcbus",  R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4,  1, 1),
0115     DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA,    CLK_EXTAL,  2, 1),
0116     DEF_FIXED("cp",     R8A779A0_CLK_CP,    CLK_EXTAL,  2, 1),
0117     DEF_FIXED("cl16mck",    R8A779A0_CLK_CL16MCK,   CLK_PLL1_DIV2,  64, 1),
0118
0119     DEF_GEN4_SDH("sdh0",    R8A779A0_CLK_SD0H,  CLK_SDSRC,     0x870),
0120     DEF_GEN4_SD("sd0",  R8A779A0_CLK_SD0,   R8A779A0_CLK_SD0H, 0x870),
0121
0122     DEF_BASE("rpc",     R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
0123     DEF_BASE("rpcd2",   R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
0124          R8A779A0_CLK_RPC),
0125
0126     DEF_DIV6P1("mso",   R8A779A0_CLK_MSO,   CLK_PLL5_DIV4,  0x87c),
0127     DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4,  0x878),
0128     DEF_DIV6P1("csi0",  R8A779A0_CLK_CSI0,  CLK_PLL5_DIV4,  0x880),
0129     DEF_DIV6P1("dsi",   R8A779A0_CLK_DSI,   CLK_PLL5_DIV4,  0x884),
0130
0131     DEF_GEN4_OSC("osc", R8A779A0_CLK_OSC,   CLK_EXTAL,  8),
0132     DEF_GEN4_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
0133 };
0134
0135 static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
0136     DEF_MOD("avb0",     211,    R8A779A0_CLK_S3D2),
0137     DEF_MOD("avb1",     212,    R8A779A0_CLK_S3D2),
0138     DEF_MOD("avb2",     213,    R8A779A0_CLK_S3D2),
0139     DEF_MOD("avb3",     214,    R8A779A0_CLK_S3D2),
0140     DEF_MOD("avb4",     215,    R8A779A0_CLK_S3D2),
0141     DEF_MOD("avb5",     216,    R8A779A0_CLK_S3D2),
0142     DEF_MOD("canfd0",   328,    R8A779A0_CLK_CANFD),
0143     DEF_MOD("csi40",    331,    R8A779A0_CLK_CSI0),
0144     DEF_MOD("csi41",    400,    R8A779A0_CLK_CSI0),
0145     DEF_MOD("csi42",    401,    R8A779A0_CLK_CSI0),
0146     DEF_MOD("csi43",    402,    R8A779A0_CLK_CSI0),
0147     DEF_MOD("du",       411,    R8A779A0_CLK_S3D1),
0148     DEF_MOD("dsi0",     415,    R8A779A0_CLK_DSI),
0149     DEF_MOD("dsi1",     416,    R8A779A0_CLK_DSI),
0150     DEF_MOD("fcpvd0",   508,    R8A779A0_CLK_S3D1),
0151     DEF_MOD("fcpvd1",   509,    R8A779A0_CLK_S3D1),
0152     DEF_MOD("hscif0",   514,    R8A779A0_CLK_S1D2),
0153     DEF_MOD("hscif1",   515,    R8A779A0_CLK_S1D2),
0154     DEF_MOD("hscif2",   516,    R8A779A0_CLK_S1D2),
0155     DEF_MOD("hscif3",   517,    R8A779A0_CLK_S1D2),
0156     DEF_MOD("i2c0",     518,    R8A779A0_CLK_S1D4),
0157     DEF_MOD("i2c1",     519,    R8A779A0_CLK_S1D4),
0158     DEF_MOD("i2c2",     520,    R8A779A0_CLK_S1D4),
0159     DEF_MOD("i2c3",     521,    R8A779A0_CLK_S1D4),
0160     DEF_MOD("i2c4",     522,    R8A779A0_CLK_S1D4),
0161     DEF_MOD("i2c5",     523,    R8A779A0_CLK_S1D4),
0162     DEF_MOD("i2c6",     524,    R8A779A0_CLK_S1D4),
0163     DEF_MOD("ispcs0",   612,    R8A779A0_CLK_S1D1),
0164     DEF_MOD("ispcs1",   613,    R8A779A0_CLK_S1D1),
0165     DEF_MOD("ispcs2",   614,    R8A779A0_CLK_S1D1),
0166     DEF_MOD("ispcs3",   615,    R8A779A0_CLK_S1D1),
0167     DEF_MOD("msi0",     618,    R8A779A0_CLK_MSO),
0168     DEF_MOD("msi1",     619,    R8A779A0_CLK_MSO),
0169     DEF_MOD("msi2",     620,    R8A779A0_CLK_MSO),
0170     DEF_MOD("msi3",     621,    R8A779A0_CLK_MSO),
0171     DEF_MOD("msi4",     622,    R8A779A0_CLK_MSO),
0172     DEF_MOD("msi5",     623,    R8A779A0_CLK_MSO),
0173     DEF_MOD("rpc-if",   629,    R8A779A0_CLK_RPCD2),
0174     DEF_MOD("scif0",    702,    R8A779A0_CLK_S1D8),
0175     DEF_MOD("scif1",    703,    R8A779A0_CLK_S1D8),
0176     DEF_MOD("scif3",    704,    R8A779A0_CLK_S1D8),
0177     DEF_MOD("scif4",    705,    R8A779A0_CLK_S1D8),
0178     DEF_MOD("sdhi0",    706,    R8A779A0_CLK_SD0),
0179     DEF_MOD("sydm1",    709,    R8A779A0_CLK_S1D2),
0180     DEF_MOD("sydm2",    710,    R8A779A0_CLK_S1D2),
0181     DEF_MOD("tmu0",     713,    R8A779A0_CLK_CL16MCK),
0182     DEF_MOD("tmu1",     714,    R8A779A0_CLK_S1D4),
0183     DEF_MOD("tmu2",     715,    R8A779A0_CLK_S1D4),
0184     DEF_MOD("tmu3",     716,    R8A779A0_CLK_S1D4),
0185     DEF_MOD("tmu4",     717,    R8A779A0_CLK_S1D4),
0186     DEF_MOD("tpu0",     718,    R8A779A0_CLK_S1D8),
0187     DEF_MOD("vin00",    730,    R8A779A0_CLK_S1D1),
0188     DEF_MOD("vin01",    731,    R8A779A0_CLK_S1D1),
0189     DEF_MOD("vin02",    800,    R8A779A0_CLK_S1D1),
0190     DEF_MOD("vin03",    801,    R8A779A0_CLK_S1D1),
0191     DEF_MOD("vin04",    802,    R8A779A0_CLK_S1D1),
0192     DEF_MOD("vin05",    803,    R8A779A0_CLK_S1D1),
0193     DEF_MOD("vin06",    804,    R8A779A0_CLK_S1D1),
0194     DEF_MOD("vin07",    805,    R8A779A0_CLK_S1D1),
0195     DEF_MOD("vin10",    806,    R8A779A0_CLK_S1D1),
0196     DEF_MOD("vin11",    807,    R8A779A0_CLK_S1D1),
0197     DEF_MOD("vin12",    808,    R8A779A0_CLK_S1D1),
0198     DEF_MOD("vin13",    809,    R8A779A0_CLK_S1D1),
0199     DEF_MOD("vin14",    810,    R8A779A0_CLK_S1D1),
0200     DEF_MOD("vin15",    811,    R8A779A0_CLK_S1D1),
0201     DEF_MOD("vin16",    812,    R8A779A0_CLK_S1D1),
0202     DEF_MOD("vin17",    813,    R8A779A0_CLK_S1D1),
0203     DEF_MOD("vin20",    814,    R8A779A0_CLK_S1D1),
0204     DEF_MOD("vin21",    815,    R8A779A0_CLK_S1D1),
0205     DEF_MOD("vin22",    816,    R8A779A0_CLK_S1D1),
0206     DEF_MOD("vin23",    817,    R8A779A0_CLK_S1D1),
0207     DEF_MOD("vin24",    818,    R8A779A0_CLK_S1D1),
0208     DEF_MOD("vin25",    819,    R8A779A0_CLK_S1D1),
0209     DEF_MOD("vin26",    820,    R8A779A0_CLK_S1D1),
0210     DEF_MOD("vin27",    821,    R8A779A0_CLK_S1D1),
0211     DEF_MOD("vin30",    822,    R8A779A0_CLK_S1D1),
0212     DEF_MOD("vin31",    823,    R8A779A0_CLK_S1D1),
0213     DEF_MOD("vin32",    824,    R8A779A0_CLK_S1D1),
0214     DEF_MOD("vin33",    825,    R8A779A0_CLK_S1D1),
0215     DEF_MOD("vin34",    826,    R8A779A0_CLK_S1D1),
0216     DEF_MOD("vin35",    827,    R8A779A0_CLK_S1D1),
0217     DEF_MOD("vin36",    828,    R8A779A0_CLK_S1D1),
0218     DEF_MOD("vin37",    829,    R8A779A0_CLK_S1D1),
0219     DEF_MOD("vspd0",    830,    R8A779A0_CLK_S3D1),
0220     DEF_MOD("vspd1",    831,    R8A779A0_CLK_S3D1),
0221     DEF_MOD("rwdt",     907,    R8A779A0_CLK_R),
0222     DEF_MOD("cmt0",     910,    R8A779A0_CLK_R),
0223     DEF_MOD("cmt1",     911,    R8A779A0_CLK_R),
0224     DEF_MOD("cmt2",     912,    R8A779A0_CLK_R),
0225     DEF_MOD("cmt3",     913,    R8A779A0_CLK_R),
0226     DEF_MOD("pfc0",     915,    R8A779A0_CLK_CP),
0227     DEF_MOD("pfc1",     916,    R8A779A0_CLK_CP),
0228     DEF_MOD("pfc2",     917,    R8A779A0_CLK_CP),
0229     DEF_MOD("pfc3",     918,    R8A779A0_CLK_CP),
0230     DEF_MOD("tsc",      919,    R8A779A0_CLK_CL16MCK),
0231     DEF_MOD("vspx0",    1028,   R8A779A0_CLK_S1D1),
0232     DEF_MOD("vspx1",    1029,   R8A779A0_CLK_S1D1),
0233     DEF_MOD("vspx2",    1030,   R8A779A0_CLK_S1D1),
0234     DEF_MOD("vspx3",    1031,   R8A779A0_CLK_S1D1),
0235 };
0236
0237 static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
0238     MOD_CLK_ID(907),    /* RWDT */
0239 };
0240
0241 /*
0242  * CPG Clock Data
0243  */
0244 /*
0245  *   MD  EXTAL      PLL1    PLL20   PLL30   PLL4    PLL5    OSC
0246  * 14 13 (MHz)             21      31
0247  * ----------------------------------------------------------------
0248  * 0  0  16.66 x 1  x128    x216    x128    x144    x192    /16
0249  * 0  1  20    x 1  x106    x180    x106    x120    x160    /19
0250  * 1  0  Prohibited setting
0251  * 1  1  33.33 / 2  x128    x216    x128    x144    x192    /32
0252  */
0253 #define CPG_PLL_CONFIG_INDEX(md)    ((((md) & BIT(14)) >> 13) | \
0254                      (((md) & BIT(13)) >> 13))
0255 static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
0256     /* EXTAL div    PLL1 mult/div   PLL2 mult/div   PLL3 mult/div   PLL4 mult/div   PLL5 mult/div   PLL6 mult/div   OSC prediv */
0257     { 1,        128,    1,  0,  0,  0,  0,  144,    1,  192,    1,  0,  0,  16, },
0258     { 1,        106,    1,  0,  0,  0,  0,  120,    1,  160,    1,  0,  0,  19, },
0259     { 0,        0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  },
0260     { 2,        128,    1,  0,  0,  0,  0,  144,    1,  192,    1,  0,  0,  32, },
0261 };
0262
0263
0264 static int __init r8a779a0_cpg_mssr_init(struct device *dev)
0265 {
0266     const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
0267     u32 cpg_mode;
0268     int error;
0269
0270     error = rcar_rst_read_mode_pins(&cpg_mode);
0271     if (error)
0272         return error;
0273
0274     cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
0275
0276     return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
0277 }
0278
0279 const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
0280     /* Core Clocks */
0281     .core_clks = r8a779a0_core_clks,
0282     .num_core_clks = ARRAY_SIZE(r8a779a0_core_clks),
0283     .last_dt_core_clk = LAST_DT_CORE_CLK,
0284     .num_total_core_clks = MOD_CLK_BASE,
0285
0286     /* Module Clocks */
0287     .mod_clks = r8a779a0_mod_clks,
0288     .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks),
0289     .num_hw_mod_clks = 15 * 32,
0290
0291     /* Critical Module Clocks */
0292     .crit_mod_clks      = r8a779a0_crit_mod_clks,
0293     .num_crit_mod_clks  = ARRAY_SIZE(r8a779a0_crit_mod_clks),
0294
0295     /* Callbacks */
0296     .init = r8a779a0_cpg_mssr_init,
0297     .cpg_clk_register = rcar_gen4_cpg_clk_register,
0298
0299     .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
0300 };