clk/renesas/r8a77995-cpg-mssr.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * r8a77995 Clock Pulse Generator / Module Standby and Software Reset
0004  *
0005  * Copyright (C) 2017 Glider bvba
0006  *
0007  * Based on r8a7795-cpg-mssr.c
0008  *
0009  * Copyright (C) 2015 Glider bvba
0010  * Copyright (C) 2015 Renesas Electronics Corp.
0011  */
0012
0013 #include <linux/device.h>
0014 #include <linux/init.h>
0015 #include <linux/kernel.h>
0016 #include <linux/soc/renesas/rcar-rst.h>
0017
0018 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
0019
0020 #include "renesas-cpg-mssr.h"
0021 #include "rcar-gen3-cpg.h"
0022
0023 enum clk_ids {
0024     /* Core Clock Outputs exported to DT */
0025     LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,
0026
0027     /* External Input Clocks */
0028     CLK_EXTAL,
0029
0030     /* Internal Core Clocks */
0031     CLK_MAIN,
0032     CLK_PLL0,
0033     CLK_PLL1,
0034     CLK_PLL3,
0035     CLK_PLL0D2,
0036     CLK_PLL0D3,
0037     CLK_PLL0D5,
0038     CLK_PLL1D2,
0039     CLK_PE,
0040     CLK_S0,
0041     CLK_S1,
0042     CLK_S2,
0043     CLK_S3,
0044     CLK_SDSRC,
0045     CLK_RPCSRC,
0046     CLK_RINT,
0047     CLK_OCO,
0048
0049     /* Module Clocks */
0050     MOD_CLK_BASE
0051 };
0052
0053 static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
0054     /* External Clock Inputs */
0055     DEF_INPUT("extal",     CLK_EXTAL),
0056
0057     /* Internal Core Clocks */
0058     DEF_BASE(".main",      CLK_MAIN, CLK_TYPE_GEN3_MAIN,       CLK_EXTAL),
0059     DEF_BASE(".pll1",      CLK_PLL1, CLK_TYPE_GEN3_PLL1,       CLK_MAIN),
0060     DEF_BASE(".pll3",      CLK_PLL3, CLK_TYPE_GEN3_PLL3,       CLK_MAIN),
0061
0062     DEF_FIXED(".pll0",     CLK_PLL0,           CLK_MAIN,       4, 250),
0063     DEF_FIXED(".pll0d2",   CLK_PLL0D2,         CLK_PLL0,       2, 1),
0064     DEF_FIXED(".pll0d3",   CLK_PLL0D3,         CLK_PLL0,       3, 1),
0065     DEF_FIXED(".pll0d5",   CLK_PLL0D5,         CLK_PLL0,       5, 1),
0066     DEF_FIXED(".pll1d2",   CLK_PLL1D2,         CLK_PLL1,       2, 1),
0067     DEF_FIXED(".pe",       CLK_PE,             CLK_PLL0D3,     4, 1),
0068     DEF_FIXED(".s0",       CLK_S0,             CLK_PLL1,       2, 1),
0069     DEF_FIXED(".s1",       CLK_S1,             CLK_PLL1,       3, 1),
0070     DEF_FIXED(".s2",       CLK_S2,             CLK_PLL1,       4, 1),
0071     DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),
0072     DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),
0073
0074     DEF_FIXED_RPCSRC_D3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
0075
0076     DEF_DIV6_RO(".r",      CLK_RINT,           CLK_EXTAL, CPG_RCKCR, 32),
0077
0078     DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),
0079
0080     /* Core Clock Outputs */
0081     DEF_FIXED("za2",       R8A77995_CLK_ZA2,   CLK_PLL0D3,     2, 1),
0082     DEF_FIXED("z2",        R8A77995_CLK_Z2,    CLK_PLL0D3,     1, 1),
0083     DEF_FIXED("ztr",       R8A77995_CLK_ZTR,   CLK_PLL1,       6, 1),
0084     DEF_FIXED("zt",        R8A77995_CLK_ZT,    CLK_PLL1,       4, 1),
0085     DEF_FIXED("zx",        R8A77995_CLK_ZX,    CLK_PLL1,       3, 1),
0086     DEF_FIXED("s0d1",      R8A77995_CLK_S0D1,  CLK_S0,         1, 1),
0087     DEF_FIXED("s1d1",      R8A77995_CLK_S1D1,  CLK_S1,         1, 1),
0088     DEF_FIXED("s1d2",      R8A77995_CLK_S1D2,  CLK_S1,         2, 1),
0089     DEF_FIXED("s1d4",      R8A77995_CLK_S1D4,  CLK_S1,         4, 1),
0090     DEF_FIXED("s2d1",      R8A77995_CLK_S2D1,  CLK_S2,         1, 1),
0091     DEF_FIXED("s2d2",      R8A77995_CLK_S2D2,  CLK_S2,         2, 1),
0092     DEF_FIXED("s2d4",      R8A77995_CLK_S2D4,  CLK_S2,         4, 1),
0093     DEF_FIXED("s3d1",      R8A77995_CLK_S3D1,  CLK_S3,         1, 1),
0094     DEF_FIXED("s3d2",      R8A77995_CLK_S3D2,  CLK_S3,         2, 1),
0095     DEF_FIXED("s3d4",      R8A77995_CLK_S3D4,  CLK_S3,         4, 1),
0096
0097     DEF_FIXED("cl",        R8A77995_CLK_CL,    CLK_PLL1,      48, 1),
0098     DEF_FIXED("cr",        R8A77995_CLK_CR,    CLK_PLL1D2,     2, 1),
0099     DEF_FIXED("cp",        R8A77995_CLK_CP,    CLK_EXTAL,      2, 1),
0100     DEF_FIXED("cpex",      R8A77995_CLK_CPEX,  CLK_EXTAL,      4, 1),
0101
0102     DEF_DIV6_RO("osc",     R8A77995_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),
0103
0104     DEF_GEN3_PE("s1d4c",   R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
0105     DEF_GEN3_PE("s3d1c",   R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
0106     DEF_GEN3_PE("s3d2c",   R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
0107     DEF_GEN3_PE("s3d4c",   R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
0108
0109     DEF_GEN3_SDH("sd0h",   R8A77995_CLK_SD0H,  CLK_SDSRC,         0x268),
0110     DEF_GEN3_SD("sd0",     R8A77995_CLK_SD0,   R8A77995_CLK_SD0H, 0x268),
0111
0112     DEF_BASE("rpc",        R8A77995_CLK_RPC,   CLK_TYPE_GEN3_RPC,   CLK_RPCSRC),
0113     DEF_BASE("rpcd2",      R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77995_CLK_RPC),
0114
0115     DEF_DIV6P1("canfd",    R8A77995_CLK_CANFD, CLK_PLL0D3,    0x244),
0116     DEF_DIV6P1("mso",      R8A77995_CLK_MSO,   CLK_PLL1D2,    0x014),
0117
0118     DEF_GEN3_RCKSEL("r",   R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
0119 };
0120
0121 static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
0122     DEF_MOD("tmu4",          121,   R8A77995_CLK_S1D4C),
0123     DEF_MOD("tmu3",          122,   R8A77995_CLK_S3D2C),
0124     DEF_MOD("tmu2",          123,   R8A77995_CLK_S3D2C),
0125     DEF_MOD("tmu1",          124,   R8A77995_CLK_S3D2C),
0126     DEF_MOD("tmu0",          125,   R8A77995_CLK_CP),
0127     DEF_MOD("scif5",         202,   R8A77995_CLK_S3D4C),
0128     DEF_MOD("scif4",         203,   R8A77995_CLK_S3D4C),
0129     DEF_MOD("scif3",         204,   R8A77995_CLK_S3D4C),
0130     DEF_MOD("scif1",         206,   R8A77995_CLK_S3D4C),
0131     DEF_MOD("scif0",         207,   R8A77995_CLK_S3D4C),
0132     DEF_MOD("msiof3",        208,   R8A77995_CLK_MSO),
0133     DEF_MOD("msiof2",        209,   R8A77995_CLK_MSO),
0134     DEF_MOD("msiof1",        210,   R8A77995_CLK_MSO),
0135     DEF_MOD("msiof0",        211,   R8A77995_CLK_MSO),
0136     DEF_MOD("sys-dmac2",         217,   R8A77995_CLK_S3D1),
0137     DEF_MOD("sys-dmac1",         218,   R8A77995_CLK_S3D1),
0138     DEF_MOD("sys-dmac0",         219,   R8A77995_CLK_S3D1),
0139     DEF_MOD("sceg-pub",      229,   R8A77995_CLK_CR),
0140     DEF_MOD("cmt3",          300,   R8A77995_CLK_R),
0141     DEF_MOD("cmt2",          301,   R8A77995_CLK_R),
0142     DEF_MOD("cmt1",          302,   R8A77995_CLK_R),
0143     DEF_MOD("cmt0",          303,   R8A77995_CLK_R),
0144     DEF_MOD("scif2",         310,   R8A77995_CLK_S3D4C),
0145     DEF_MOD("emmc0",         312,   R8A77995_CLK_SD0),
0146     DEF_MOD("usb-dmac0",         330,   R8A77995_CLK_S3D1),
0147     DEF_MOD("usb-dmac1",         331,   R8A77995_CLK_S3D1),
0148     DEF_MOD("rwdt",          402,   R8A77995_CLK_R),
0149     DEF_MOD("intc-ex",       407,   R8A77995_CLK_CP),
0150     DEF_MOD("intc-ap",       408,   R8A77995_CLK_S1D2),
0151     DEF_MOD("audmac0",       502,   R8A77995_CLK_S1D2),
0152     DEF_MOD("hscif3",        517,   R8A77995_CLK_S3D1C),
0153     DEF_MOD("hscif0",        520,   R8A77995_CLK_S3D1C),
0154     DEF_MOD("thermal",       522,   R8A77995_CLK_CP),
0155     DEF_MOD("pwm",           523,   R8A77995_CLK_S3D4C),
0156     DEF_MOD("fcpvd1",        602,   R8A77995_CLK_S1D2),
0157     DEF_MOD("fcpvd0",        603,   R8A77995_CLK_S1D2),
0158     DEF_MOD("fcpvbs",        607,   R8A77995_CLK_S0D1),
0159     DEF_MOD("vspd1",         622,   R8A77995_CLK_S1D2),
0160     DEF_MOD("vspd0",         623,   R8A77995_CLK_S1D2),
0161     DEF_MOD("vspbs",         627,   R8A77995_CLK_S0D1),
0162     DEF_MOD("ehci0",         703,   R8A77995_CLK_S3D2),
0163     DEF_MOD("hsusb",         704,   R8A77995_CLK_S3D2),
0164     DEF_MOD("cmm1",          710,   R8A77995_CLK_S1D1),
0165     DEF_MOD("cmm0",          711,   R8A77995_CLK_S1D1),
0166     DEF_MOD("du1",           723,   R8A77995_CLK_S1D1),
0167     DEF_MOD("du0",           724,   R8A77995_CLK_S1D1),
0168     DEF_MOD("lvds",          727,   R8A77995_CLK_S2D1),
0169     DEF_MOD("mlp",           802,   R8A77995_CLK_S2D1),
0170     DEF_MOD("vin4",          807,   R8A77995_CLK_S1D2),
0171     DEF_MOD("etheravb",      812,   R8A77995_CLK_S3D2),
0172     DEF_MOD("imr0",          823,   R8A77995_CLK_S1D2),
0173     DEF_MOD("gpio6",         906,   R8A77995_CLK_S3D4),
0174     DEF_MOD("gpio5",         907,   R8A77995_CLK_S3D4),
0175     DEF_MOD("gpio4",         908,   R8A77995_CLK_S3D4),
0176     DEF_MOD("gpio3",         909,   R8A77995_CLK_S3D4),
0177     DEF_MOD("gpio2",         910,   R8A77995_CLK_S3D4),
0178     DEF_MOD("gpio1",         911,   R8A77995_CLK_S3D4),
0179     DEF_MOD("gpio0",         912,   R8A77995_CLK_S3D4),
0180     DEF_MOD("can-fd",        914,   R8A77995_CLK_S3D2),
0181     DEF_MOD("can-if1",       915,   R8A77995_CLK_S3D4),
0182     DEF_MOD("can-if0",       916,   R8A77995_CLK_S3D4),
0183     DEF_MOD("rpc-if",        917,   R8A77995_CLK_RPCD2),
0184     DEF_MOD("i2c3",          928,   R8A77995_CLK_S3D2),
0185     DEF_MOD("i2c2",          929,   R8A77995_CLK_S3D2),
0186     DEF_MOD("i2c1",          930,   R8A77995_CLK_S3D2),
0187     DEF_MOD("i2c0",          931,   R8A77995_CLK_S3D2),
0188     DEF_MOD("ssi-all",      1005,   R8A77995_CLK_S3D4),
0189     DEF_MOD("ssi4",         1011,   MOD_CLK_ID(1005)),
0190     DEF_MOD("ssi3",         1012,   MOD_CLK_ID(1005)),
0191     DEF_MOD("scu-all",      1017,   R8A77995_CLK_S3D4),
0192     DEF_MOD("scu-dvc1",     1018,   MOD_CLK_ID(1017)),
0193     DEF_MOD("scu-dvc0",     1019,   MOD_CLK_ID(1017)),
0194     DEF_MOD("scu-ctu1-mix1",    1020,   MOD_CLK_ID(1017)),
0195     DEF_MOD("scu-ctu0-mix0",    1021,   MOD_CLK_ID(1017)),
0196     DEF_MOD("scu-src6",     1025,   MOD_CLK_ID(1017)),
0197     DEF_MOD("scu-src5",     1026,   MOD_CLK_ID(1017)),
0198 };
0199
0200 static const unsigned int r8a77995_crit_mod_clks[] __initconst = {
0201     MOD_CLK_ID(402),    /* RWDT */
0202     MOD_CLK_ID(408),    /* INTC-AP (GIC) */
0203 };
0204
0205 /*
0206  * CPG Clock Data
0207  */
0208
0209 /*
0210  * MD19     EXTAL (MHz) PLL0        PLL1        PLL3
0211  *--------------------------------------------------------------------
0212  * 0        48 x 1      x250/4      x100/3      x100/3
0213  * 1        48 x 1      x250/4      x100/3      x58/3
0214  */
0215 #define CPG_PLL_CONFIG_INDEX(md)    (((md) & BIT(19)) >> 19)
0216
0217 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
0218     /* EXTAL div    PLL1 mult/div   PLL3 mult/div */
0219     { 1,        100,    3,  100,    3,  },
0220     { 1,        100,    3,  58, 3,  },
0221 };
0222
0223 static int __init r8a77995_cpg_mssr_init(struct device *dev)
0224 {
0225     const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
0226     u32 cpg_mode;
0227     int error;
0228
0229     error = rcar_rst_read_mode_pins(&cpg_mode);
0230     if (error)
0231         return error;
0232
0233     cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
0234
0235     return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
0236 }
0237
0238 const struct cpg_mssr_info r8a77995_cpg_mssr_info __initconst = {
0239     /* Core Clocks */
0240     .core_clks = r8a77995_core_clks,
0241     .num_core_clks = ARRAY_SIZE(r8a77995_core_clks),
0242     .last_dt_core_clk = LAST_DT_CORE_CLK,
0243     .num_total_core_clks = MOD_CLK_BASE,
0244
0245     /* Module Clocks */
0246     .mod_clks = r8a77995_mod_clks,
0247     .num_mod_clks = ARRAY_SIZE(r8a77995_mod_clks),
0248     .num_hw_mod_clks = 12 * 32,
0249
0250     /* Critical Module Clocks */
0251     .crit_mod_clks = r8a77995_crit_mod_clks,
0252     .num_crit_mod_clks = ARRAY_SIZE(r8a77995_crit_mod_clks),
0253
0254     /* Callbacks */
0255     .init = r8a77995_cpg_mssr_init,
0256     .cpg_clk_register = rcar_gen3_cpg_clk_register,
0257 };