clk/renesas/r8a77990-cpg-mssr.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * r8a77990 Clock Pulse Generator / Module Standby and Software Reset
0004  *
0005  * Copyright (C) 2018-2019 Renesas Electronics Corp.
0006  *
0007  * Based on r8a7795-cpg-mssr.c
0008  *
0009  * Copyright (C) 2015 Glider bvba
0010  * Copyright (C) 2015 Renesas Electronics Corp.
0011  */
0012
0013 #include <linux/device.h>
0014 #include <linux/init.h>
0015 #include <linux/kernel.h>
0016 #include <linux/soc/renesas/rcar-rst.h>
0017
0018 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
0019
0020 #include "renesas-cpg-mssr.h"
0021 #include "rcar-gen3-cpg.h"
0022
0023 enum clk_ids {
0024     /* Core Clock Outputs exported to DT */
0025     LAST_DT_CORE_CLK = R8A77990_CLK_CPEX,
0026
0027     /* External Input Clocks */
0028     CLK_EXTAL,
0029
0030     /* Internal Core Clocks */
0031     CLK_MAIN,
0032     CLK_PLL0,
0033     CLK_PLL1,
0034     CLK_PLL3,
0035     CLK_PLL0D4,
0036     CLK_PLL0D6,
0037     CLK_PLL0D8,
0038     CLK_PLL0D20,
0039     CLK_PLL0D24,
0040     CLK_PLL1D2,
0041     CLK_PE,
0042     CLK_S0,
0043     CLK_S1,
0044     CLK_S2,
0045     CLK_S3,
0046     CLK_SDSRC,
0047     CLK_RPCSRC,
0048     CLK_RINT,
0049     CLK_OCO,
0050
0051     /* Module Clocks */
0052     MOD_CLK_BASE
0053 };
0054
0055 static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
0056     /* External Clock Inputs */
0057     DEF_INPUT("extal",     CLK_EXTAL),
0058
0059     /* Internal Core Clocks */
0060     DEF_BASE(".main",      CLK_MAIN, CLK_TYPE_GEN3_MAIN,       CLK_EXTAL),
0061     DEF_BASE(".pll1",      CLK_PLL1, CLK_TYPE_GEN3_PLL1,       CLK_MAIN),
0062     DEF_BASE(".pll3",      CLK_PLL3, CLK_TYPE_GEN3_PLL3,       CLK_MAIN),
0063
0064     DEF_FIXED(".pll0",     CLK_PLL0,           CLK_MAIN,       1, 100),
0065     DEF_FIXED(".pll0d4",   CLK_PLL0D4,         CLK_PLL0,       4, 1),
0066     DEF_FIXED(".pll0d6",   CLK_PLL0D6,         CLK_PLL0,       6, 1),
0067     DEF_FIXED(".pll0d8",   CLK_PLL0D8,         CLK_PLL0,       8, 1),
0068     DEF_FIXED(".pll0d20",  CLK_PLL0D20,        CLK_PLL0,      20, 1),
0069     DEF_FIXED(".pll0d24",  CLK_PLL0D24,        CLK_PLL0,      24, 1),
0070     DEF_FIXED(".pll1d2",   CLK_PLL1D2,         CLK_PLL1,       2, 1),
0071     DEF_FIXED(".pe",       CLK_PE,             CLK_PLL0D20,    1, 1),
0072     DEF_FIXED(".s0",       CLK_S0,             CLK_PLL1,       2, 1),
0073     DEF_FIXED(".s1",       CLK_S1,             CLK_PLL1,       3, 1),
0074     DEF_FIXED(".s2",       CLK_S2,             CLK_PLL1,       4, 1),
0075     DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),
0076     DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),
0077
0078     DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
0079
0080     DEF_DIV6_RO(".r",      CLK_RINT,           CLK_EXTAL, CPG_RCKCR, 32),
0081
0082     DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),
0083
0084     /* Core Clock Outputs */
0085     DEF_FIXED("za2",       R8A77990_CLK_ZA2,   CLK_PLL0D24,    1, 1),
0086     DEF_FIXED("za8",       R8A77990_CLK_ZA8,   CLK_PLL0D8,     1, 1),
0087     DEF_GEN3_Z("z2",       R8A77990_CLK_Z2,    CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8),
0088     DEF_FIXED("ztr",       R8A77990_CLK_ZTR,   CLK_PLL1,       6, 1),
0089     DEF_FIXED("zt",        R8A77990_CLK_ZT,    CLK_PLL1,       4, 1),
0090     DEF_FIXED("zx",        R8A77990_CLK_ZX,    CLK_PLL1,       3, 1),
0091     DEF_FIXED("s0d1",      R8A77990_CLK_S0D1,  CLK_S0,         1, 1),
0092     DEF_FIXED("s0d3",      R8A77990_CLK_S0D3,  CLK_S0,         3, 1),
0093     DEF_FIXED("s0d6",      R8A77990_CLK_S0D6,  CLK_S0,         6, 1),
0094     DEF_FIXED("s0d12",     R8A77990_CLK_S0D12, CLK_S0,        12, 1),
0095     DEF_FIXED("s0d24",     R8A77990_CLK_S0D24, CLK_S0,        24, 1),
0096     DEF_FIXED("s1d1",      R8A77990_CLK_S1D1,  CLK_S1,         1, 1),
0097     DEF_FIXED("s1d2",      R8A77990_CLK_S1D2,  CLK_S1,         2, 1),
0098     DEF_FIXED("s1d4",      R8A77990_CLK_S1D4,  CLK_S1,         4, 1),
0099     DEF_FIXED("s2d1",      R8A77990_CLK_S2D1,  CLK_S2,         1, 1),
0100     DEF_FIXED("s2d2",      R8A77990_CLK_S2D2,  CLK_S2,         2, 1),
0101     DEF_FIXED("s2d4",      R8A77990_CLK_S2D4,  CLK_S2,         4, 1),
0102     DEF_FIXED("s3d1",      R8A77990_CLK_S3D1,  CLK_S3,         1, 1),
0103     DEF_FIXED("s3d2",      R8A77990_CLK_S3D2,  CLK_S3,         2, 1),
0104     DEF_FIXED("s3d4",      R8A77990_CLK_S3D4,  CLK_S3,         4, 1),
0105
0106     DEF_GEN3_SDH("sd0h",   R8A77990_CLK_SD0H,  CLK_SDSRC,         0x0074),
0107     DEF_GEN3_SDH("sd1h",   R8A77990_CLK_SD1H,  CLK_SDSRC,         0x0078),
0108     DEF_GEN3_SDH("sd3h",   R8A77990_CLK_SD3H,  CLK_SDSRC,         0x026c),
0109     DEF_GEN3_SD("sd0",     R8A77990_CLK_SD0,   R8A77990_CLK_SD0H, 0x0074),
0110     DEF_GEN3_SD("sd1",     R8A77990_CLK_SD1,   R8A77990_CLK_SD1H, 0x0078),
0111     DEF_GEN3_SD("sd3",     R8A77990_CLK_SD3,   R8A77990_CLK_SD3H, 0x026c),
0112
0113     DEF_BASE("rpc",        R8A77990_CLK_RPC,   CLK_TYPE_GEN3_RPC,   CLK_RPCSRC),
0114     DEF_BASE("rpcd2",      R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77990_CLK_RPC),
0115
0116     DEF_FIXED("cl",        R8A77990_CLK_CL,    CLK_PLL1,      48, 1),
0117     DEF_FIXED("cr",        R8A77990_CLK_CR,    CLK_PLL1D2,     2, 1),
0118     DEF_FIXED("cp",        R8A77990_CLK_CP,    CLK_EXTAL,      2, 1),
0119     DEF_FIXED("cpex",      R8A77990_CLK_CPEX,  CLK_EXTAL,      4, 1),
0120
0121     DEF_DIV6_RO("osc",     R8A77990_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),
0122
0123     DEF_GEN3_PE("s0d6c",   R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
0124     DEF_GEN3_PE("s3d1c",   R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
0125     DEF_GEN3_PE("s3d2c",   R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
0126     DEF_GEN3_PE("s3d4c",   R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
0127
0128     DEF_DIV6P1("canfd",    R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
0129     DEF_DIV6P1("csi0",     R8A77990_CLK_CSI0,  CLK_PLL1D2, 0x00c),
0130     DEF_DIV6P1("mso",      R8A77990_CLK_MSO,   CLK_PLL1D2, 0x014),
0131
0132     DEF_GEN3_RCKSEL("r",   R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
0133 };
0134
0135 static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
0136     DEF_MOD("tmu4",          121,   R8A77990_CLK_S0D6C),
0137     DEF_MOD("tmu3",          122,   R8A77990_CLK_S3D2C),
0138     DEF_MOD("tmu2",          123,   R8A77990_CLK_S3D2C),
0139     DEF_MOD("tmu1",          124,   R8A77990_CLK_S3D2C),
0140     DEF_MOD("tmu0",          125,   R8A77990_CLK_CP),
0141     DEF_MOD("scif5",         202,   R8A77990_CLK_S3D4C),
0142     DEF_MOD("scif4",         203,   R8A77990_CLK_S3D4C),
0143     DEF_MOD("scif3",         204,   R8A77990_CLK_S3D4C),
0144     DEF_MOD("scif1",         206,   R8A77990_CLK_S3D4C),
0145     DEF_MOD("scif0",         207,   R8A77990_CLK_S3D4C),
0146     DEF_MOD("msiof3",        208,   R8A77990_CLK_MSO),
0147     DEF_MOD("msiof2",        209,   R8A77990_CLK_MSO),
0148     DEF_MOD("msiof1",        210,   R8A77990_CLK_MSO),
0149     DEF_MOD("msiof0",        211,   R8A77990_CLK_MSO),
0150     DEF_MOD("sys-dmac2",         217,   R8A77990_CLK_S3D1),
0151     DEF_MOD("sys-dmac1",         218,   R8A77990_CLK_S3D1),
0152     DEF_MOD("sys-dmac0",         219,   R8A77990_CLK_S3D1),
0153     DEF_MOD("sceg-pub",      229,   R8A77990_CLK_CR),
0154
0155     DEF_MOD("cmt3",          300,   R8A77990_CLK_R),
0156     DEF_MOD("cmt2",          301,   R8A77990_CLK_R),
0157     DEF_MOD("cmt1",          302,   R8A77990_CLK_R),
0158     DEF_MOD("cmt0",          303,   R8A77990_CLK_R),
0159     DEF_MOD("scif2",         310,   R8A77990_CLK_S3D4C),
0160     DEF_MOD("sdif3",         311,   R8A77990_CLK_SD3),
0161     DEF_MOD("sdif1",         313,   R8A77990_CLK_SD1),
0162     DEF_MOD("sdif0",         314,   R8A77990_CLK_SD0),
0163     DEF_MOD("pcie0",         319,   R8A77990_CLK_S3D1),
0164     DEF_MOD("usb3-if0",      328,   R8A77990_CLK_S3D1),
0165     DEF_MOD("usb-dmac0",         330,   R8A77990_CLK_S3D1),
0166     DEF_MOD("usb-dmac1",         331,   R8A77990_CLK_S3D1),
0167
0168     DEF_MOD("rwdt",          402,   R8A77990_CLK_R),
0169     DEF_MOD("intc-ex",       407,   R8A77990_CLK_CP),
0170     DEF_MOD("intc-ap",       408,   R8A77990_CLK_S0D3),
0171
0172     DEF_MOD("audmac0",       502,   R8A77990_CLK_S1D2),
0173     DEF_MOD("drif31",        508,   R8A77990_CLK_S3D2),
0174     DEF_MOD("drif30",        509,   R8A77990_CLK_S3D2),
0175     DEF_MOD("drif21",        510,   R8A77990_CLK_S3D2),
0176     DEF_MOD("drif20",        511,   R8A77990_CLK_S3D2),
0177     DEF_MOD("drif11",        512,   R8A77990_CLK_S3D2),
0178     DEF_MOD("drif10",        513,   R8A77990_CLK_S3D2),
0179     DEF_MOD("drif01",        514,   R8A77990_CLK_S3D2),
0180     DEF_MOD("drif00",        515,   R8A77990_CLK_S3D2),
0181     DEF_MOD("hscif4",        516,   R8A77990_CLK_S3D1C),
0182     DEF_MOD("hscif3",        517,   R8A77990_CLK_S3D1C),
0183     DEF_MOD("hscif2",        518,   R8A77990_CLK_S3D1C),
0184     DEF_MOD("hscif1",        519,   R8A77990_CLK_S3D1C),
0185     DEF_MOD("hscif0",        520,   R8A77990_CLK_S3D1C),
0186     DEF_MOD("thermal",       522,   R8A77990_CLK_CP),
0187     DEF_MOD("pwm",           523,   R8A77990_CLK_S3D4C),
0188
0189     DEF_MOD("fcpvd1",        602,   R8A77990_CLK_S1D2),
0190     DEF_MOD("fcpvd0",        603,   R8A77990_CLK_S1D2),
0191     DEF_MOD("fcpvb0",        607,   R8A77990_CLK_S0D1),
0192     DEF_MOD("fcpvi0",        611,   R8A77990_CLK_S0D1),
0193     DEF_MOD("fcpf0",         615,   R8A77990_CLK_S0D1),
0194     DEF_MOD("fcpcs",         619,   R8A77990_CLK_S0D1),
0195     DEF_MOD("vspd1",         622,   R8A77990_CLK_S1D2),
0196     DEF_MOD("vspd0",         623,   R8A77990_CLK_S1D2),
0197     DEF_MOD("vspb",          626,   R8A77990_CLK_S0D1),
0198     DEF_MOD("vspi0",         631,   R8A77990_CLK_S0D1),
0199
0200     DEF_MOD("ehci0",         703,   R8A77990_CLK_S3D2),
0201     DEF_MOD("hsusb",         704,   R8A77990_CLK_S3D2),
0202     DEF_MOD("cmm1",          710,   R8A77990_CLK_S1D1),
0203     DEF_MOD("cmm0",          711,   R8A77990_CLK_S1D1),
0204     DEF_MOD("csi40",         716,   R8A77990_CLK_CSI0),
0205     DEF_MOD("du1",           723,   R8A77990_CLK_S1D1),
0206     DEF_MOD("du0",           724,   R8A77990_CLK_S1D1),
0207     DEF_MOD("lvds",          727,   R8A77990_CLK_S2D1),
0208
0209     DEF_MOD("mlp",           802,   R8A77990_CLK_S2D1),
0210     DEF_MOD("vin5",          806,   R8A77990_CLK_S1D2),
0211     DEF_MOD("vin4",          807,   R8A77990_CLK_S1D2),
0212     DEF_MOD("etheravb",      812,   R8A77990_CLK_S3D2),
0213
0214     DEF_MOD("gpio6",         906,   R8A77990_CLK_S3D4),
0215     DEF_MOD("gpio5",         907,   R8A77990_CLK_S3D4),
0216     DEF_MOD("gpio4",         908,   R8A77990_CLK_S3D4),
0217     DEF_MOD("gpio3",         909,   R8A77990_CLK_S3D4),
0218     DEF_MOD("gpio2",         910,   R8A77990_CLK_S3D4),
0219     DEF_MOD("gpio1",         911,   R8A77990_CLK_S3D4),
0220     DEF_MOD("gpio0",         912,   R8A77990_CLK_S3D4),
0221     DEF_MOD("can-fd",        914,   R8A77990_CLK_S3D2),
0222     DEF_MOD("can-if1",       915,   R8A77990_CLK_S3D4),
0223     DEF_MOD("can-if0",       916,   R8A77990_CLK_S3D4),
0224     DEF_MOD("rpc-if",        917,   R8A77990_CLK_RPCD2),
0225     DEF_MOD("i2c6",          918,   R8A77990_CLK_S3D2),
0226     DEF_MOD("i2c5",          919,   R8A77990_CLK_S3D2),
0227     DEF_MOD("i2c-dvfs",      926,   R8A77990_CLK_CP),
0228     DEF_MOD("i2c4",          927,   R8A77990_CLK_S3D2),
0229     DEF_MOD("i2c3",          928,   R8A77990_CLK_S3D2),
0230     DEF_MOD("i2c2",          929,   R8A77990_CLK_S3D2),
0231     DEF_MOD("i2c1",          930,   R8A77990_CLK_S3D2),
0232     DEF_MOD("i2c0",          931,   R8A77990_CLK_S3D2),
0233
0234     DEF_MOD("i2c7",         1003,   R8A77990_CLK_S3D2),
0235     DEF_MOD("ssi-all",      1005,   R8A77990_CLK_S3D4),
0236     DEF_MOD("ssi9",         1006,   MOD_CLK_ID(1005)),
0237     DEF_MOD("ssi8",         1007,   MOD_CLK_ID(1005)),
0238     DEF_MOD("ssi7",         1008,   MOD_CLK_ID(1005)),
0239     DEF_MOD("ssi6",         1009,   MOD_CLK_ID(1005)),
0240     DEF_MOD("ssi5",         1010,   MOD_CLK_ID(1005)),
0241     DEF_MOD("ssi4",         1011,   MOD_CLK_ID(1005)),
0242     DEF_MOD("ssi3",         1012,   MOD_CLK_ID(1005)),
0243     DEF_MOD("ssi2",         1013,   MOD_CLK_ID(1005)),
0244     DEF_MOD("ssi1",         1014,   MOD_CLK_ID(1005)),
0245     DEF_MOD("ssi0",         1015,   MOD_CLK_ID(1005)),
0246     DEF_MOD("dab",          1016,   R8A77990_CLK_S3D1),
0247     DEF_MOD("scu-all",      1017,   R8A77990_CLK_S3D4),
0248     DEF_MOD("scu-dvc1",     1018,   MOD_CLK_ID(1017)),
0249     DEF_MOD("scu-dvc0",     1019,   MOD_CLK_ID(1017)),
0250     DEF_MOD("scu-ctu1-mix1",    1020,   MOD_CLK_ID(1017)),
0251     DEF_MOD("scu-ctu0-mix0",    1021,   MOD_CLK_ID(1017)),
0252     DEF_MOD("scu-src9",     1022,   MOD_CLK_ID(1017)),
0253     DEF_MOD("scu-src8",     1023,   MOD_CLK_ID(1017)),
0254     DEF_MOD("scu-src7",     1024,   MOD_CLK_ID(1017)),
0255     DEF_MOD("scu-src6",     1025,   MOD_CLK_ID(1017)),
0256     DEF_MOD("scu-src5",     1026,   MOD_CLK_ID(1017)),
0257     DEF_MOD("scu-src4",     1027,   MOD_CLK_ID(1017)),
0258     DEF_MOD("scu-src3",     1028,   MOD_CLK_ID(1017)),
0259     DEF_MOD("scu-src2",     1029,   MOD_CLK_ID(1017)),
0260     DEF_MOD("scu-src1",     1030,   MOD_CLK_ID(1017)),
0261     DEF_MOD("scu-src0",     1031,   MOD_CLK_ID(1017)),
0262 };
0263
0264 static const unsigned int r8a77990_crit_mod_clks[] __initconst = {
0265     MOD_CLK_ID(402),    /* RWDT */
0266     MOD_CLK_ID(408),    /* INTC-AP (GIC) */
0267 };
0268
0269 /*
0270  * CPG Clock Data
0271  */
0272
0273 /*
0274  * MD19     EXTAL (MHz) PLL0        PLL1        PLL3
0275  *--------------------------------------------------------------------
0276  * 0        48 x 1      x100/1      x100/3      x100/3
0277  * 1        48 x 1      x100/1      x100/3       x58/3
0278  */
0279 #define CPG_PLL_CONFIG_INDEX(md)    (((md) & BIT(19)) >> 19)
0280
0281 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
0282     /* EXTAL div    PLL1 mult/div   PLL3 mult/div */
0283     { 1,        100,    3,  100,    3,  },
0284     { 1,        100,    3,   58,    3,  },
0285 };
0286
0287 static int __init r8a77990_cpg_mssr_init(struct device *dev)
0288 {
0289     const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
0290     u32 cpg_mode;
0291     int error;
0292
0293     error = rcar_rst_read_mode_pins(&cpg_mode);
0294     if (error)
0295         return error;
0296
0297     cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
0298
0299     return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
0300 }
0301
0302 const struct cpg_mssr_info r8a77990_cpg_mssr_info __initconst = {
0303     /* Core Clocks */
0304     .core_clks = r8a77990_core_clks,
0305     .num_core_clks = ARRAY_SIZE(r8a77990_core_clks),
0306     .last_dt_core_clk = LAST_DT_CORE_CLK,
0307     .num_total_core_clks = MOD_CLK_BASE,
0308
0309     /* Module Clocks */
0310     .mod_clks = r8a77990_mod_clks,
0311     .num_mod_clks = ARRAY_SIZE(r8a77990_mod_clks),
0312     .num_hw_mod_clks = 12 * 32,
0313
0314     /* Critical Module Clocks */
0315     .crit_mod_clks = r8a77990_crit_mod_clks,
0316     .num_crit_mod_clks = ARRAY_SIZE(r8a77990_crit_mod_clks),
0317
0318     /* Callbacks */
0319     .init = r8a77990_cpg_mssr_init,
0320     .cpg_clk_register = rcar_gen3_cpg_clk_register,
0321 };