Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * r8a7794 Clock Pulse Generator / Module Standby and Software Reset
0004  *
0005  * Copyright (C) 2017 Glider bvba
0006  *
0007  * Based on clk-rcar-gen2.c
0008  *
0009  * Copyright (C) 2013 Ideas On Board SPRL
0010  */
0011 
0012 #include <linux/device.h>
0013 #include <linux/init.h>
0014 #include <linux/kernel.h>
0015 #include <linux/soc/renesas/rcar-rst.h>
0016 
0017 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
0018 
0019 #include "renesas-cpg-mssr.h"
0020 #include "rcar-gen2-cpg.h"
0021 
0022 enum clk_ids {
0023     /* Core Clock Outputs exported to DT */
0024     LAST_DT_CORE_CLK = R8A7794_CLK_OSC,
0025 
0026     /* External Input Clocks */
0027     CLK_EXTAL,
0028     CLK_USB_EXTAL,
0029 
0030     /* Internal Core Clocks */
0031     CLK_MAIN,
0032     CLK_PLL0,
0033     CLK_PLL1,
0034     CLK_PLL3,
0035     CLK_PLL1_DIV2,
0036 
0037     /* Module Clocks */
0038     MOD_CLK_BASE
0039 };
0040 
0041 static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
0042     /* External Clock Inputs */
0043     DEF_INPUT("extal",     CLK_EXTAL),
0044     DEF_INPUT("usb_extal", CLK_USB_EXTAL),
0045 
0046     /* Internal Core Clocks */
0047     DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
0048     DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
0049     DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
0050     DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
0051 
0052     DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
0053 
0054     /* Core Clock Outputs */
0055     DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
0056     DEF_BASE("sdh",  R8A7794_CLK_SDH,  CLK_TYPE_GEN2_SDH,  CLK_PLL1),
0057     DEF_BASE("sd0",  R8A7794_CLK_SD0,  CLK_TYPE_GEN2_SD0,  CLK_PLL1),
0058     DEF_BASE("qspi", R8A7794_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
0059     DEF_BASE("rcan", R8A7794_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
0060 
0061     DEF_FIXED("z2",     R8A7794_CLK_Z2,    CLK_PLL0,          1, 1),
0062     DEF_FIXED("zg",     R8A7794_CLK_ZG,    CLK_PLL1,          6, 1),
0063     DEF_FIXED("zx",     R8A7794_CLK_ZX,    CLK_PLL1,          3, 1),
0064     DEF_FIXED("zs",     R8A7794_CLK_ZS,    CLK_PLL1,          6, 1),
0065     DEF_FIXED("hp",     R8A7794_CLK_HP,    CLK_PLL1,         12, 1),
0066     DEF_FIXED("i",      R8A7794_CLK_I,     CLK_PLL1,          2, 1),
0067     DEF_FIXED("b",      R8A7794_CLK_B,     CLK_PLL1,         12, 1),
0068     DEF_FIXED("lb",     R8A7794_CLK_LB,    CLK_PLL1,         24, 1),
0069     DEF_FIXED("p",      R8A7794_CLK_P,     CLK_PLL1,         24, 1),
0070     DEF_FIXED("cl",     R8A7794_CLK_CL,    CLK_PLL1,         48, 1),
0071     DEF_FIXED("cp",     R8A7794_CLK_CP,    CLK_PLL1,         48, 1),
0072     DEF_FIXED("m2",     R8A7794_CLK_M2,    CLK_PLL1,          8, 1),
0073     DEF_FIXED("zb3",    R8A7794_CLK_ZB3,   CLK_PLL3,          4, 1),
0074     DEF_FIXED("zb3d2",  R8A7794_CLK_ZB3D2, CLK_PLL3,          8, 1),
0075     DEF_FIXED("ddr",    R8A7794_CLK_DDR,   CLK_PLL3,          8, 1),
0076     DEF_FIXED("mp",     R8A7794_CLK_MP,    CLK_PLL1_DIV2,    15, 1),
0077     DEF_FIXED("cpex",   R8A7794_CLK_CPEX,  CLK_EXTAL,         2, 1),
0078     DEF_FIXED("r",      R8A7794_CLK_R,     CLK_PLL1,      49152, 1),
0079     DEF_FIXED("osc",    R8A7794_CLK_OSC,   CLK_PLL1,      12288, 1),
0080 
0081     DEF_DIV6P1("sd2",   R8A7794_CLK_SD2,   CLK_PLL1_DIV2, 0x078),
0082     DEF_DIV6P1("sd3",   R8A7794_CLK_SD3,   CLK_PLL1_DIV2, 0x26c),
0083     DEF_DIV6P1("mmc0",  R8A7794_CLK_MMC0,  CLK_PLL1_DIV2, 0x240),
0084 };
0085 
0086 static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
0087     DEF_MOD("msiof0",          0,   R8A7794_CLK_MP),
0088     DEF_MOD("vcp0",          101,   R8A7794_CLK_ZS),
0089     DEF_MOD("vpc0",          103,   R8A7794_CLK_ZS),
0090     DEF_MOD("jpu",           106,   R8A7794_CLK_M2),
0091     DEF_MOD("tmu1",          111,   R8A7794_CLK_P),
0092     DEF_MOD("3dg",           112,   R8A7794_CLK_ZG),
0093     DEF_MOD("2d-dmac",       115,   R8A7794_CLK_ZS),
0094     DEF_MOD("fdp1-0",        119,   R8A7794_CLK_ZS),
0095     DEF_MOD("tmu3",          121,   R8A7794_CLK_P),
0096     DEF_MOD("tmu2",          122,   R8A7794_CLK_P),
0097     DEF_MOD("cmt0",          124,   R8A7794_CLK_R),
0098     DEF_MOD("tmu0",          125,   R8A7794_CLK_CP),
0099     DEF_MOD("vsp1du0",       128,   R8A7794_CLK_ZS),
0100     DEF_MOD("vsps",          131,   R8A7794_CLK_ZS),
0101     DEF_MOD("scifa2",        202,   R8A7794_CLK_MP),
0102     DEF_MOD("scifa1",        203,   R8A7794_CLK_MP),
0103     DEF_MOD("scifa0",        204,   R8A7794_CLK_MP),
0104     DEF_MOD("msiof2",        205,   R8A7794_CLK_MP),
0105     DEF_MOD("scifb0",        206,   R8A7794_CLK_MP),
0106     DEF_MOD("scifb1",        207,   R8A7794_CLK_MP),
0107     DEF_MOD("msiof1",        208,   R8A7794_CLK_MP),
0108     DEF_MOD("scifb2",        216,   R8A7794_CLK_MP),
0109     DEF_MOD("sys-dmac1",         218,   R8A7794_CLK_ZS),
0110     DEF_MOD("sys-dmac0",         219,   R8A7794_CLK_ZS),
0111     DEF_MOD("tpu0",          304,   R8A7794_CLK_CP),
0112     DEF_MOD("sdhi3",         311,   R8A7794_CLK_SD3),
0113     DEF_MOD("sdhi2",         312,   R8A7794_CLK_SD2),
0114     DEF_MOD("sdhi0",         314,   R8A7794_CLK_SD0),
0115     DEF_MOD("mmcif0",        315,   R8A7794_CLK_MMC0),
0116     DEF_MOD("iic0",          318,   R8A7794_CLK_HP),
0117     DEF_MOD("iic1",          323,   R8A7794_CLK_HP),
0118     DEF_MOD("cmt1",          329,   R8A7794_CLK_R),
0119     DEF_MOD("usbhs-dmac0",       330,   R8A7794_CLK_HP),
0120     DEF_MOD("usbhs-dmac1",       331,   R8A7794_CLK_HP),
0121     DEF_MOD("rwdt",          402,   R8A7794_CLK_R),
0122     DEF_MOD("irqc",          407,   R8A7794_CLK_CP),
0123     DEF_MOD("intc-sys",      408,   R8A7794_CLK_ZS),
0124     DEF_MOD("audio-dmac0",       502,   R8A7794_CLK_HP),
0125     DEF_MOD("adsp_mod",      506,   R8A7794_CLK_ADSP),
0126     DEF_MOD("pwm",           523,   R8A7794_CLK_P),
0127     DEF_MOD("usb-ehci",      703,   R8A7794_CLK_MP),
0128     DEF_MOD("usbhs",         704,   R8A7794_CLK_HP),
0129     DEF_MOD("hscif2",        713,   R8A7794_CLK_ZS),
0130     DEF_MOD("scif5",         714,   R8A7794_CLK_P),
0131     DEF_MOD("scif4",         715,   R8A7794_CLK_P),
0132     DEF_MOD("hscif1",        716,   R8A7794_CLK_ZS),
0133     DEF_MOD("hscif0",        717,   R8A7794_CLK_ZS),
0134     DEF_MOD("scif3",         718,   R8A7794_CLK_P),
0135     DEF_MOD("scif2",         719,   R8A7794_CLK_P),
0136     DEF_MOD("scif1",         720,   R8A7794_CLK_P),
0137     DEF_MOD("scif0",         721,   R8A7794_CLK_P),
0138     DEF_MOD("du1",           723,   R8A7794_CLK_ZX),
0139     DEF_MOD("du0",           724,   R8A7794_CLK_ZX),
0140     DEF_MOD("ipmmu-sgx",         800,   R8A7794_CLK_ZX),
0141     DEF_MOD("mlb",           802,   R8A7794_CLK_HP),
0142     DEF_MOD("vin1",          810,   R8A7794_CLK_ZG),
0143     DEF_MOD("vin0",          811,   R8A7794_CLK_ZG),
0144     DEF_MOD("etheravb",      812,   R8A7794_CLK_HP),
0145     DEF_MOD("ether",         813,   R8A7794_CLK_P),
0146     DEF_MOD("gyro-adc",      901,   R8A7794_CLK_P),
0147     DEF_MOD("gpio6",         905,   R8A7794_CLK_CP),
0148     DEF_MOD("gpio5",         907,   R8A7794_CLK_CP),
0149     DEF_MOD("gpio4",         908,   R8A7794_CLK_CP),
0150     DEF_MOD("gpio3",         909,   R8A7794_CLK_CP),
0151     DEF_MOD("gpio2",         910,   R8A7794_CLK_CP),
0152     DEF_MOD("gpio1",         911,   R8A7794_CLK_CP),
0153     DEF_MOD("gpio0",         912,   R8A7794_CLK_CP),
0154     DEF_MOD("can1",          915,   R8A7794_CLK_P),
0155     DEF_MOD("can0",          916,   R8A7794_CLK_P),
0156     DEF_MOD("qspi_mod",      917,   R8A7794_CLK_QSPI),
0157     DEF_MOD("i2c5",          925,   R8A7794_CLK_HP),
0158     DEF_MOD("i2c4",          927,   R8A7794_CLK_HP),
0159     DEF_MOD("i2c3",          928,   R8A7794_CLK_HP),
0160     DEF_MOD("i2c2",          929,   R8A7794_CLK_HP),
0161     DEF_MOD("i2c1",          930,   R8A7794_CLK_HP),
0162     DEF_MOD("i2c0",          931,   R8A7794_CLK_HP),
0163     DEF_MOD("ssi-all",      1005,   R8A7794_CLK_P),
0164     DEF_MOD("ssi9",         1006,   MOD_CLK_ID(1005)),
0165     DEF_MOD("ssi8",         1007,   MOD_CLK_ID(1005)),
0166     DEF_MOD("ssi7",         1008,   MOD_CLK_ID(1005)),
0167     DEF_MOD("ssi6",         1009,   MOD_CLK_ID(1005)),
0168     DEF_MOD("ssi5",         1010,   MOD_CLK_ID(1005)),
0169     DEF_MOD("ssi4",         1011,   MOD_CLK_ID(1005)),
0170     DEF_MOD("ssi3",         1012,   MOD_CLK_ID(1005)),
0171     DEF_MOD("ssi2",         1013,   MOD_CLK_ID(1005)),
0172     DEF_MOD("ssi1",         1014,   MOD_CLK_ID(1005)),
0173     DEF_MOD("ssi0",         1015,   MOD_CLK_ID(1005)),
0174     DEF_MOD("scu-all",      1017,   R8A7794_CLK_P),
0175     DEF_MOD("scu-dvc1",     1018,   MOD_CLK_ID(1017)),
0176     DEF_MOD("scu-dvc0",     1019,   MOD_CLK_ID(1017)),
0177     DEF_MOD("scu-ctu1-mix1",    1020,   MOD_CLK_ID(1017)),
0178     DEF_MOD("scu-ctu0-mix0",    1021,   MOD_CLK_ID(1017)),
0179     DEF_MOD("scu-src6",     1025,   MOD_CLK_ID(1017)),
0180     DEF_MOD("scu-src5",     1026,   MOD_CLK_ID(1017)),
0181     DEF_MOD("scu-src4",     1027,   MOD_CLK_ID(1017)),
0182     DEF_MOD("scu-src3",     1028,   MOD_CLK_ID(1017)),
0183     DEF_MOD("scu-src2",     1029,   MOD_CLK_ID(1017)),
0184     DEF_MOD("scu-src1",     1030,   MOD_CLK_ID(1017)),
0185     DEF_MOD("scifa3",       1106,   R8A7794_CLK_MP),
0186     DEF_MOD("scifa4",       1107,   R8A7794_CLK_MP),
0187     DEF_MOD("scifa5",       1108,   R8A7794_CLK_MP),
0188 };
0189 
0190 static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
0191     MOD_CLK_ID(402),    /* RWDT */
0192     MOD_CLK_ID(408),    /* INTC-SYS (GIC) */
0193 };
0194 
0195 /*
0196  * CPG Clock Data
0197  */
0198 
0199 /*
0200  *   MD     EXTAL       PLL0    PLL1    PLL3
0201  * 14 13 19 (MHz)       *1  *2
0202  *---------------------------------------------------
0203  * 0  0  1  15      x200/3  x208/2  x88
0204  * 0  1  1  20      x150/3  x156/2  x66
0205  * 1  0  1  26 / 2      x230/3  x240/2  x102
0206  * 1  1  1  30 / 2      x200/3  x208/2  x88
0207  *
0208  * *1 : Table 7.5c indicates VCO output (PLL0 = VCO/3)
0209  * *2 : Table 7.5c indicates VCO output (PLL1 = VCO/2)
0210  */
0211 #define CPG_PLL_CONFIG_INDEX(md)    ((((md) & BIT(14)) >> 13) | \
0212                      (((md) & BIT(13)) >> 13))
0213 static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
0214     { 1, 208,  88, 200 },
0215     { 1, 156,  66, 150 },
0216     { 2, 240, 102, 230 },
0217     { 2, 208,  88, 200 },
0218 };
0219 
0220 static int __init r8a7794_cpg_mssr_init(struct device *dev)
0221 {
0222     const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
0223     u32 cpg_mode;
0224     int error;
0225 
0226     error = rcar_rst_read_mode_pins(&cpg_mode);
0227     if (error)
0228         return error;
0229 
0230     cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
0231 
0232     return rcar_gen2_cpg_init(cpg_pll_config, 3, cpg_mode);
0233 }
0234 
0235 const struct cpg_mssr_info r8a7794_cpg_mssr_info __initconst = {
0236     /* Core Clocks */
0237     .core_clks = r8a7794_core_clks,
0238     .num_core_clks = ARRAY_SIZE(r8a7794_core_clks),
0239     .last_dt_core_clk = LAST_DT_CORE_CLK,
0240     .num_total_core_clks = MOD_CLK_BASE,
0241 
0242     /* Module Clocks */
0243     .mod_clks = r8a7794_mod_clks,
0244     .num_mod_clks = ARRAY_SIZE(r8a7794_mod_clks),
0245     .num_hw_mod_clks = 12 * 32,
0246 
0247     /* Critical Module Clocks */
0248     .crit_mod_clks = r8a7794_crit_mod_clks,
0249     .num_crit_mod_clks = ARRAY_SIZE(r8a7794_crit_mod_clks),
0250 
0251     /* Callbacks */
0252     .init = r8a7794_cpg_mssr_init,
0253     .cpg_clk_register = rcar_gen2_cpg_clk_register,
0254 };
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!