clk/renesas/r8a7792-cpg-mssr.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * r8a7792 Clock Pulse Generator / Module Standby and Software Reset
0004  *
0005  * Copyright (C) 2017 Glider bvba
0006  *
0007  * Based on clk-rcar-gen2.c
0008  *
0009  * Copyright (C) 2013 Ideas On Board SPRL
0010  */
0011
0012 #include <linux/device.h>
0013 #include <linux/init.h>
0014 #include <linux/kernel.h>
0015 #include <linux/soc/renesas/rcar-rst.h>
0016
0017 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
0018
0019 #include "renesas-cpg-mssr.h"
0020 #include "rcar-gen2-cpg.h"
0021
0022 enum clk_ids {
0023     /* Core Clock Outputs exported to DT */
0024     LAST_DT_CORE_CLK = R8A7792_CLK_OSC,
0025
0026     /* External Input Clocks */
0027     CLK_EXTAL,
0028
0029     /* Internal Core Clocks */
0030     CLK_MAIN,
0031     CLK_PLL0,
0032     CLK_PLL1,
0033     CLK_PLL3,
0034     CLK_PLL1_DIV2,
0035
0036     /* Module Clocks */
0037     MOD_CLK_BASE
0038 };
0039
0040 static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
0041     /* External Clock Inputs */
0042     DEF_INPUT("extal",     CLK_EXTAL),
0043
0044     /* Internal Core Clocks */
0045     DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
0046     DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
0047     DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
0048     DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
0049
0050     DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
0051
0052     /* Core Clock Outputs */
0053     DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
0054
0055     DEF_FIXED("z",      R8A7792_CLK_Z,     CLK_PLL0,          1, 1),
0056     DEF_FIXED("zg",     R8A7792_CLK_ZG,    CLK_PLL1,          5, 1),
0057     DEF_FIXED("zx",     R8A7792_CLK_ZX,    CLK_PLL1,          3, 1),
0058     DEF_FIXED("zs",     R8A7792_CLK_ZS,    CLK_PLL1,          6, 1),
0059     DEF_FIXED("hp",     R8A7792_CLK_HP,    CLK_PLL1,         12, 1),
0060     DEF_FIXED("i",      R8A7792_CLK_I,     CLK_PLL1,          3, 1),
0061     DEF_FIXED("b",      R8A7792_CLK_B,     CLK_PLL1,         12, 1),
0062     DEF_FIXED("lb",     R8A7792_CLK_LB,    CLK_PLL1,         24, 1),
0063     DEF_FIXED("p",      R8A7792_CLK_P,     CLK_PLL1,         24, 1),
0064     DEF_FIXED("cl",     R8A7792_CLK_CL,    CLK_PLL1,         48, 1),
0065     DEF_FIXED("m2",     R8A7792_CLK_M2,    CLK_PLL1,          8, 1),
0066     DEF_FIXED("imp",    R8A7792_CLK_IMP,   CLK_PLL1,          4, 1),
0067     DEF_FIXED("zb3",    R8A7792_CLK_ZB3,   CLK_PLL3,          4, 1),
0068     DEF_FIXED("zb3d2",  R8A7792_CLK_ZB3D2, CLK_PLL3,          8, 1),
0069     DEF_FIXED("ddr",    R8A7792_CLK_DDR,   CLK_PLL3,          8, 1),
0070     DEF_FIXED("sd",     R8A7792_CLK_SD,    CLK_PLL1_DIV2,     8, 1),
0071     DEF_FIXED("mp",     R8A7792_CLK_MP,    CLK_PLL1_DIV2,    15, 1),
0072     DEF_FIXED("cp",     R8A7792_CLK_CP,    CLK_PLL1,         48, 1),
0073     DEF_FIXED("cpex",   R8A7792_CLK_CPEX,  CLK_EXTAL,         2, 1),
0074     DEF_FIXED("rcan",   R8A7792_CLK_RCAN,  CLK_PLL1_DIV2,    49, 1),
0075     DEF_FIXED("r",      R8A7792_CLK_R,     CLK_PLL1,      49152, 1),
0076     DEF_FIXED("osc",    R8A7792_CLK_OSC,   CLK_PLL1,      12288, 1),
0077 };
0078
0079 static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
0080     DEF_MOD("msiof0",          0,   R8A7792_CLK_MP),
0081     DEF_MOD("jpu",           106,   R8A7792_CLK_M2),
0082     DEF_MOD("tmu1",          111,   R8A7792_CLK_P),
0083     DEF_MOD("3dg",           112,   R8A7792_CLK_ZG),
0084     DEF_MOD("2d-dmac",       115,   R8A7792_CLK_ZS),
0085     DEF_MOD("tmu3",          121,   R8A7792_CLK_P),
0086     DEF_MOD("tmu2",          122,   R8A7792_CLK_P),
0087     DEF_MOD("cmt0",          124,   R8A7792_CLK_R),
0088     DEF_MOD("tmu0",          125,   R8A7792_CLK_CP),
0089     DEF_MOD("vsp1du1",       127,   R8A7792_CLK_ZS),
0090     DEF_MOD("vsp1du0",       128,   R8A7792_CLK_ZS),
0091     DEF_MOD("vsps",          131,   R8A7792_CLK_ZS),
0092     DEF_MOD("msiof1",        208,   R8A7792_CLK_MP),
0093     DEF_MOD("sys-dmac1",         218,   R8A7792_CLK_ZS),
0094     DEF_MOD("sys-dmac0",         219,   R8A7792_CLK_ZS),
0095     DEF_MOD("tpu0",          304,   R8A7792_CLK_CP),
0096     DEF_MOD("sdhi0",         314,   R8A7792_CLK_SD),
0097     DEF_MOD("cmt1",          329,   R8A7792_CLK_R),
0098     DEF_MOD("rwdt",          402,   R8A7792_CLK_R),
0099     DEF_MOD("irqc",          407,   R8A7792_CLK_CP),
0100     DEF_MOD("intc-sys",      408,   R8A7792_CLK_ZS),
0101     DEF_MOD("audio-dmac0",       502,   R8A7792_CLK_HP),
0102     DEF_MOD("thermal",       522,   CLK_EXTAL),
0103     DEF_MOD("pwm",           523,   R8A7792_CLK_P),
0104     DEF_MOD("hscif1",        716,   R8A7792_CLK_ZS),
0105     DEF_MOD("hscif0",        717,   R8A7792_CLK_ZS),
0106     DEF_MOD("scif3",         718,   R8A7792_CLK_P),
0107     DEF_MOD("scif2",         719,   R8A7792_CLK_P),
0108     DEF_MOD("scif1",         720,   R8A7792_CLK_P),
0109     DEF_MOD("scif0",         721,   R8A7792_CLK_P),
0110     DEF_MOD("du1",           723,   R8A7792_CLK_ZX),
0111     DEF_MOD("du0",           724,   R8A7792_CLK_ZX),
0112     DEF_MOD("vin5",          804,   R8A7792_CLK_ZG),
0113     DEF_MOD("vin4",          805,   R8A7792_CLK_ZG),
0114     DEF_MOD("vin3",          808,   R8A7792_CLK_ZG),
0115     DEF_MOD("vin2",          809,   R8A7792_CLK_ZG),
0116     DEF_MOD("vin1",          810,   R8A7792_CLK_ZG),
0117     DEF_MOD("vin0",          811,   R8A7792_CLK_ZG),
0118     DEF_MOD("etheravb",      812,   R8A7792_CLK_HP),
0119     DEF_MOD("imr-lx3",       821,   R8A7792_CLK_ZG),
0120     DEF_MOD("imr-lsx3-1",        822,   R8A7792_CLK_ZG),
0121     DEF_MOD("imr-lsx3-0",        823,   R8A7792_CLK_ZG),
0122     DEF_MOD("imr-lsx3-5",        825,   R8A7792_CLK_ZG),
0123     DEF_MOD("imr-lsx3-4",        826,   R8A7792_CLK_ZG),
0124     DEF_MOD("imr-lsx3-3",        827,   R8A7792_CLK_ZG),
0125     DEF_MOD("imr-lsx3-2",        828,   R8A7792_CLK_ZG),
0126     DEF_MOD("gyro-adc",      901,   R8A7792_CLK_P),
0127     DEF_MOD("gpio7",         904,   R8A7792_CLK_CP),
0128     DEF_MOD("gpio6",         905,   R8A7792_CLK_CP),
0129     DEF_MOD("gpio5",         907,   R8A7792_CLK_CP),
0130     DEF_MOD("gpio4",         908,   R8A7792_CLK_CP),
0131     DEF_MOD("gpio3",         909,   R8A7792_CLK_CP),
0132     DEF_MOD("gpio2",         910,   R8A7792_CLK_CP),
0133     DEF_MOD("gpio1",         911,   R8A7792_CLK_CP),
0134     DEF_MOD("gpio0",         912,   R8A7792_CLK_CP),
0135     DEF_MOD("gpio11",        913,   R8A7792_CLK_CP),
0136     DEF_MOD("gpio10",        914,   R8A7792_CLK_CP),
0137     DEF_MOD("can1",          915,   R8A7792_CLK_P),
0138     DEF_MOD("can0",          916,   R8A7792_CLK_P),
0139     DEF_MOD("qspi_mod",      917,   R8A7792_CLK_QSPI),
0140     DEF_MOD("gpio9",         919,   R8A7792_CLK_CP),
0141     DEF_MOD("gpio8",         921,   R8A7792_CLK_CP),
0142     DEF_MOD("i2c5",          925,   R8A7792_CLK_HP),
0143     DEF_MOD("iicdvfs",       926,   R8A7792_CLK_CP),
0144     DEF_MOD("i2c4",          927,   R8A7792_CLK_HP),
0145     DEF_MOD("i2c3",          928,   R8A7792_CLK_HP),
0146     DEF_MOD("i2c2",          929,   R8A7792_CLK_HP),
0147     DEF_MOD("i2c1",          930,   R8A7792_CLK_HP),
0148     DEF_MOD("i2c0",          931,   R8A7792_CLK_HP),
0149     DEF_MOD("ssi-all",      1005,   R8A7792_CLK_P),
0150     DEF_MOD("ssi4",         1011,   MOD_CLK_ID(1005)),
0151     DEF_MOD("ssi3",         1012,   MOD_CLK_ID(1005)),
0152 };
0153
0154 static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
0155     MOD_CLK_ID(402),    /* RWDT */
0156     MOD_CLK_ID(408),    /* INTC-SYS (GIC) */
0157 };
0158
0159 /*
0160  * CPG Clock Data
0161  */
0162
0163 /*
0164  *   MD     EXTAL       PLL0    PLL1    PLL3
0165  * 14 13 19 (MHz)       *1  *2
0166  *---------------------------------------------------
0167  * 0  0  0  15      x200/3  x208/2  x106
0168  * 0  0  1  15      x200/3  x208/2  x88
0169  * 0  1  0  20      x150/3  x156/2  x80
0170  * 0  1  1  20      x150/3  x156/2  x66
0171  * 1  0  0  26 / 2      x230/3  x240/2  x122
0172  * 1  0  1  26 / 2      x230/3  x240/2  x102
0173  * 1  1  0  30 / 2      x200/3  x208/2  x106
0174  * 1  1  1  30 / 2      x200/3  x208/2  x88
0175  *
0176  * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
0177  * *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
0178  */
0179 #define CPG_PLL_CONFIG_INDEX(md)    ((((md) & BIT(14)) >> 12) | \
0180                      (((md) & BIT(13)) >> 12) | \
0181                      (((md) & BIT(19)) >> 19))
0182 static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
0183     { 1, 208, 106, 200 },
0184     { 1, 208,  88, 200 },
0185     { 1, 156,  80, 150 },
0186     { 1, 156,  66, 150 },
0187     { 2, 240, 122, 230 },
0188     { 2, 240, 102, 230 },
0189     { 2, 208, 106, 200 },
0190     { 2, 208,  88, 200 },
0191 };
0192
0193 static int __init r8a7792_cpg_mssr_init(struct device *dev)
0194 {
0195     const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
0196     u32 cpg_mode;
0197     int error;
0198
0199     error = rcar_rst_read_mode_pins(&cpg_mode);
0200     if (error)
0201         return error;
0202
0203     cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
0204
0205     return rcar_gen2_cpg_init(cpg_pll_config, 3, cpg_mode);
0206 }
0207
0208 const struct cpg_mssr_info r8a7792_cpg_mssr_info __initconst = {
0209     /* Core Clocks */
0210     .core_clks = r8a7792_core_clks,
0211     .num_core_clks = ARRAY_SIZE(r8a7792_core_clks),
0212     .last_dt_core_clk = LAST_DT_CORE_CLK,
0213     .num_total_core_clks = MOD_CLK_BASE,
0214
0215     /* Module Clocks */
0216     .mod_clks = r8a7792_mod_clks,
0217     .num_mod_clks = ARRAY_SIZE(r8a7792_mod_clks),
0218     .num_hw_mod_clks = 12 * 32,
0219
0220     /* Critical Module Clocks */
0221     .crit_mod_clks = r8a7792_crit_mod_clks,
0222     .num_crit_mod_clks = ARRAY_SIZE(r8a7792_crit_mod_clks),
0223
0224     /* Callbacks */
0225     .init = r8a7792_cpg_mssr_init,
0226     .cpg_clk_register = rcar_gen2_cpg_clk_register,
0227 };