clk/renesas/r8a774b1-cpg-mssr.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * r8a774b1 Clock Pulse Generator / Module Standby and Software Reset
0004  *
0005  * Copyright (C) 2019 Renesas Electronics Corp.
0006  *
0007  * Based on r8a7796-cpg-mssr.c
0008  *
0009  * Copyright (C) 2016 Glider bvba
0010  */
0011
0012 #include <linux/device.h>
0013 #include <linux/init.h>
0014 #include <linux/kernel.h>
0015 #include <linux/soc/renesas/rcar-rst.h>
0016
0017 #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
0018
0019 #include "renesas-cpg-mssr.h"
0020 #include "rcar-gen3-cpg.h"
0021
0022 enum clk_ids {
0023     /* Core Clock Outputs exported to DT */
0024     LAST_DT_CORE_CLK = R8A774B1_CLK_CANFD,
0025
0026     /* External Input Clocks */
0027     CLK_EXTAL,
0028     CLK_EXTALR,
0029
0030     /* Internal Core Clocks */
0031     CLK_MAIN,
0032     CLK_PLL0,
0033     CLK_PLL1,
0034     CLK_PLL3,
0035     CLK_PLL4,
0036     CLK_PLL1_DIV2,
0037     CLK_PLL1_DIV4,
0038     CLK_S0,
0039     CLK_S1,
0040     CLK_S2,
0041     CLK_S3,
0042     CLK_SDSRC,
0043     CLK_RPCSRC,
0044     CLK_RINT,
0045
0046     /* Module Clocks */
0047     MOD_CLK_BASE
0048 };
0049
0050 static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
0051     /* External Clock Inputs */
0052     DEF_INPUT("extal",      CLK_EXTAL),
0053     DEF_INPUT("extalr",     CLK_EXTALR),
0054
0055     /* Internal Core Clocks */
0056     DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
0057     DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
0058     DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
0059     DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
0060     DEF_BASE(".pll4",       CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
0061
0062     DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
0063     DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
0064     DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
0065     DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
0066     DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
0067     DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
0068     DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
0069
0070     DEF_BASE(".rpcsrc",     CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
0071
0072     DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
0073
0074     /* Core Clock Outputs */
0075     DEF_GEN3_Z("z",         R8A774B1_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),
0076     DEF_FIXED("ztr",        R8A774B1_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
0077     DEF_FIXED("ztrd2",      R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
0078     DEF_FIXED("zt",         R8A774B1_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
0079     DEF_FIXED("zx",         R8A774B1_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
0080     DEF_FIXED("s0d1",       R8A774B1_CLK_S0D1,  CLK_S0,         1, 1),
0081     DEF_FIXED("s0d2",       R8A774B1_CLK_S0D2,  CLK_S0,         2, 1),
0082     DEF_FIXED("s0d3",       R8A774B1_CLK_S0D3,  CLK_S0,         3, 1),
0083     DEF_FIXED("s0d4",       R8A774B1_CLK_S0D4,  CLK_S0,         4, 1),
0084     DEF_FIXED("s0d6",       R8A774B1_CLK_S0D6,  CLK_S0,         6, 1),
0085     DEF_FIXED("s0d8",       R8A774B1_CLK_S0D8,  CLK_S0,         8, 1),
0086     DEF_FIXED("s0d12",      R8A774B1_CLK_S0D12, CLK_S0,        12, 1),
0087     DEF_FIXED("s1d2",       R8A774B1_CLK_S1D2,  CLK_S1,         2, 1),
0088     DEF_FIXED("s1d4",       R8A774B1_CLK_S1D4,  CLK_S1,         4, 1),
0089     DEF_FIXED("s2d1",       R8A774B1_CLK_S2D1,  CLK_S2,         1, 1),
0090     DEF_FIXED("s2d2",       R8A774B1_CLK_S2D2,  CLK_S2,         2, 1),
0091     DEF_FIXED("s2d4",       R8A774B1_CLK_S2D4,  CLK_S2,         4, 1),
0092     DEF_FIXED("s3d1",       R8A774B1_CLK_S3D1,  CLK_S3,         1, 1),
0093     DEF_FIXED("s3d2",       R8A774B1_CLK_S3D2,  CLK_S3,         2, 1),
0094     DEF_FIXED("s3d4",       R8A774B1_CLK_S3D4,  CLK_S3,         4, 1),
0095
0096     DEF_GEN3_SDH("sd0h",    R8A774B1_CLK_SD0H,  CLK_SDSRC,         0x074),
0097     DEF_GEN3_SDH("sd1h",    R8A774B1_CLK_SD1H,  CLK_SDSRC,         0x078),
0098     DEF_GEN3_SDH("sd2h",    R8A774B1_CLK_SD2H,  CLK_SDSRC,         0x268),
0099     DEF_GEN3_SDH("sd3h",    R8A774B1_CLK_SD3H,  CLK_SDSRC,         0x26c),
0100     DEF_GEN3_SD("sd0",      R8A774B1_CLK_SD0,   R8A774B1_CLK_SD0H, 0x074),
0101     DEF_GEN3_SD("sd1",      R8A774B1_CLK_SD1,   R8A774B1_CLK_SD1H, 0x078),
0102     DEF_GEN3_SD("sd2",      R8A774B1_CLK_SD2,   R8A774B1_CLK_SD2H, 0x268),
0103     DEF_GEN3_SD("sd3",      R8A774B1_CLK_SD3,   R8A774B1_CLK_SD3H, 0x26c),
0104
0105     DEF_BASE("rpc",         R8A774B1_CLK_RPC,   CLK_TYPE_GEN3_RPC,   CLK_RPCSRC),
0106     DEF_BASE("rpcd2",       R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774B1_CLK_RPC),
0107
0108     DEF_FIXED("cl",         R8A774B1_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
0109     DEF_FIXED("cp",         R8A774B1_CLK_CP,    CLK_EXTAL,      2, 1),
0110     DEF_FIXED("cpex",       R8A774B1_CLK_CPEX,  CLK_EXTAL,      2, 1),
0111
0112     DEF_DIV6P1("canfd",     R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
0113     DEF_DIV6P1("csi0",      R8A774B1_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
0114     DEF_DIV6P1("mso",       R8A774B1_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
0115     DEF_DIV6P1("hdmi",      R8A774B1_CLK_HDMI,  CLK_PLL1_DIV4, 0x250),
0116
0117     DEF_GEN3_OSC("osc",     R8A774B1_CLK_OSC,   CLK_EXTAL,     8),
0118
0119     DEF_BASE("r",           R8A774B1_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
0120 };
0121
0122 static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
0123     DEF_MOD("tmu4",          121,   R8A774B1_CLK_S0D6),
0124     DEF_MOD("tmu3",          122,   R8A774B1_CLK_S3D2),
0125     DEF_MOD("tmu2",          123,   R8A774B1_CLK_S3D2),
0126     DEF_MOD("tmu1",          124,   R8A774B1_CLK_S3D2),
0127     DEF_MOD("tmu0",          125,   R8A774B1_CLK_CP),
0128     DEF_MOD("fdp1-0",        119,   R8A774B1_CLK_S0D1),
0129     DEF_MOD("scif5",         202,   R8A774B1_CLK_S3D4),
0130     DEF_MOD("scif4",         203,   R8A774B1_CLK_S3D4),
0131     DEF_MOD("scif3",         204,   R8A774B1_CLK_S3D4),
0132     DEF_MOD("scif1",         206,   R8A774B1_CLK_S3D4),
0133     DEF_MOD("scif0",         207,   R8A774B1_CLK_S3D4),
0134     DEF_MOD("msiof3",        208,   R8A774B1_CLK_MSO),
0135     DEF_MOD("msiof2",        209,   R8A774B1_CLK_MSO),
0136     DEF_MOD("msiof1",        210,   R8A774B1_CLK_MSO),
0137     DEF_MOD("msiof0",        211,   R8A774B1_CLK_MSO),
0138     DEF_MOD("sys-dmac2",         217,   R8A774B1_CLK_S3D1),
0139     DEF_MOD("sys-dmac1",         218,   R8A774B1_CLK_S3D1),
0140     DEF_MOD("sys-dmac0",         219,   R8A774B1_CLK_S0D3),
0141     DEF_MOD("cmt3",          300,   R8A774B1_CLK_R),
0142     DEF_MOD("cmt2",          301,   R8A774B1_CLK_R),
0143     DEF_MOD("cmt1",          302,   R8A774B1_CLK_R),
0144     DEF_MOD("cmt0",          303,   R8A774B1_CLK_R),
0145     DEF_MOD("tpu0",          304,   R8A774B1_CLK_S3D4),
0146     DEF_MOD("scif2",         310,   R8A774B1_CLK_S3D4),
0147     DEF_MOD("sdif3",         311,   R8A774B1_CLK_SD3),
0148     DEF_MOD("sdif2",         312,   R8A774B1_CLK_SD2),
0149     DEF_MOD("sdif1",         313,   R8A774B1_CLK_SD1),
0150     DEF_MOD("sdif0",         314,   R8A774B1_CLK_SD0),
0151     DEF_MOD("pcie1",         318,   R8A774B1_CLK_S3D1),
0152     DEF_MOD("pcie0",         319,   R8A774B1_CLK_S3D1),
0153     DEF_MOD("usb3-if0",      328,   R8A774B1_CLK_S3D1),
0154     DEF_MOD("usb-dmac0",         330,   R8A774B1_CLK_S3D1),
0155     DEF_MOD("usb-dmac1",         331,   R8A774B1_CLK_S3D1),
0156     DEF_MOD("rwdt",          402,   R8A774B1_CLK_R),
0157     DEF_MOD("intc-ex",       407,   R8A774B1_CLK_CP),
0158     DEF_MOD("intc-ap",       408,   R8A774B1_CLK_S0D3),
0159     DEF_MOD("audmac1",       501,   R8A774B1_CLK_S1D2),
0160     DEF_MOD("audmac0",       502,   R8A774B1_CLK_S1D2),
0161     DEF_MOD("hscif4",        516,   R8A774B1_CLK_S3D1),
0162     DEF_MOD("hscif3",        517,   R8A774B1_CLK_S3D1),
0163     DEF_MOD("hscif2",        518,   R8A774B1_CLK_S3D1),
0164     DEF_MOD("hscif1",        519,   R8A774B1_CLK_S3D1),
0165     DEF_MOD("hscif0",        520,   R8A774B1_CLK_S3D1),
0166     DEF_MOD("thermal",       522,   R8A774B1_CLK_CP),
0167     DEF_MOD("pwm",           523,   R8A774B1_CLK_S0D12),
0168     DEF_MOD("fcpvd1",        602,   R8A774B1_CLK_S0D2),
0169     DEF_MOD("fcpvd0",        603,   R8A774B1_CLK_S0D2),
0170     DEF_MOD("fcpvb0",        607,   R8A774B1_CLK_S0D1),
0171     DEF_MOD("fcpvi0",        611,   R8A774B1_CLK_S0D1),
0172     DEF_MOD("fcpf0",         615,   R8A774B1_CLK_S0D1),
0173     DEF_MOD("fcpcs",         619,   R8A774B1_CLK_S0D2),
0174     DEF_MOD("vspd1",         622,   R8A774B1_CLK_S0D2),
0175     DEF_MOD("vspd0",         623,   R8A774B1_CLK_S0D2),
0176     DEF_MOD("vspb",          626,   R8A774B1_CLK_S0D1),
0177     DEF_MOD("vspi0",         631,   R8A774B1_CLK_S0D1),
0178     DEF_MOD("ehci1",         702,   R8A774B1_CLK_S3D2),
0179     DEF_MOD("ehci0",         703,   R8A774B1_CLK_S3D2),
0180     DEF_MOD("hsusb",         704,   R8A774B1_CLK_S3D2),
0181     DEF_MOD("csi20",         714,   R8A774B1_CLK_CSI0),
0182     DEF_MOD("csi40",         716,   R8A774B1_CLK_CSI0),
0183     DEF_MOD("du3",           721,   R8A774B1_CLK_S2D1),
0184     DEF_MOD("du1",           723,   R8A774B1_CLK_S2D1),
0185     DEF_MOD("du0",           724,   R8A774B1_CLK_S2D1),
0186     DEF_MOD("lvds",          727,   R8A774B1_CLK_S2D1),
0187     DEF_MOD("hdmi0",         729,   R8A774B1_CLK_HDMI),
0188     DEF_MOD("vin7",          804,   R8A774B1_CLK_S0D2),
0189     DEF_MOD("vin6",          805,   R8A774B1_CLK_S0D2),
0190     DEF_MOD("vin5",          806,   R8A774B1_CLK_S0D2),
0191     DEF_MOD("vin4",          807,   R8A774B1_CLK_S0D2),
0192     DEF_MOD("vin3",          808,   R8A774B1_CLK_S0D2),
0193     DEF_MOD("vin2",          809,   R8A774B1_CLK_S0D2),
0194     DEF_MOD("vin1",          810,   R8A774B1_CLK_S0D2),
0195     DEF_MOD("vin0",          811,   R8A774B1_CLK_S0D2),
0196     DEF_MOD("etheravb",      812,   R8A774B1_CLK_S0D6),
0197     DEF_MOD("sata0",         815,   R8A774B1_CLK_S3D2),
0198     DEF_MOD("gpio7",         905,   R8A774B1_CLK_S3D4),
0199     DEF_MOD("gpio6",         906,   R8A774B1_CLK_S3D4),
0200     DEF_MOD("gpio5",         907,   R8A774B1_CLK_S3D4),
0201     DEF_MOD("gpio4",         908,   R8A774B1_CLK_S3D4),
0202     DEF_MOD("gpio3",         909,   R8A774B1_CLK_S3D4),
0203     DEF_MOD("gpio2",         910,   R8A774B1_CLK_S3D4),
0204     DEF_MOD("gpio1",         911,   R8A774B1_CLK_S3D4),
0205     DEF_MOD("gpio0",         912,   R8A774B1_CLK_S3D4),
0206     DEF_MOD("can-fd",        914,   R8A774B1_CLK_S3D2),
0207     DEF_MOD("can-if1",       915,   R8A774B1_CLK_S3D4),
0208     DEF_MOD("can-if0",       916,   R8A774B1_CLK_S3D4),
0209     DEF_MOD("rpc-if",        917,   R8A774B1_CLK_RPCD2),
0210     DEF_MOD("i2c6",          918,   R8A774B1_CLK_S0D6),
0211     DEF_MOD("i2c5",          919,   R8A774B1_CLK_S0D6),
0212     DEF_MOD("iic-pmic",      926,   R8A774B1_CLK_CP),
0213     DEF_MOD("i2c4",          927,   R8A774B1_CLK_S0D6),
0214     DEF_MOD("i2c3",          928,   R8A774B1_CLK_S0D6),
0215     DEF_MOD("i2c2",          929,   R8A774B1_CLK_S3D2),
0216     DEF_MOD("i2c1",          930,   R8A774B1_CLK_S3D2),
0217     DEF_MOD("i2c0",          931,   R8A774B1_CLK_S3D2),
0218     DEF_MOD("ssi-all",      1005,   R8A774B1_CLK_S3D4),
0219     DEF_MOD("ssi9",         1006,   MOD_CLK_ID(1005)),
0220     DEF_MOD("ssi8",         1007,   MOD_CLK_ID(1005)),
0221     DEF_MOD("ssi7",         1008,   MOD_CLK_ID(1005)),
0222     DEF_MOD("ssi6",         1009,   MOD_CLK_ID(1005)),
0223     DEF_MOD("ssi5",         1010,   MOD_CLK_ID(1005)),
0224     DEF_MOD("ssi4",         1011,   MOD_CLK_ID(1005)),
0225     DEF_MOD("ssi3",         1012,   MOD_CLK_ID(1005)),
0226     DEF_MOD("ssi2",         1013,   MOD_CLK_ID(1005)),
0227     DEF_MOD("ssi1",         1014,   MOD_CLK_ID(1005)),
0228     DEF_MOD("ssi0",         1015,   MOD_CLK_ID(1005)),
0229     DEF_MOD("scu-all",      1017,   R8A774B1_CLK_S3D4),
0230     DEF_MOD("scu-dvc1",     1018,   MOD_CLK_ID(1017)),
0231     DEF_MOD("scu-dvc0",     1019,   MOD_CLK_ID(1017)),
0232     DEF_MOD("scu-ctu1-mix1",    1020,   MOD_CLK_ID(1017)),
0233     DEF_MOD("scu-ctu0-mix0",    1021,   MOD_CLK_ID(1017)),
0234     DEF_MOD("scu-src9",     1022,   MOD_CLK_ID(1017)),
0235     DEF_MOD("scu-src8",     1023,   MOD_CLK_ID(1017)),
0236     DEF_MOD("scu-src7",     1024,   MOD_CLK_ID(1017)),
0237     DEF_MOD("scu-src6",     1025,   MOD_CLK_ID(1017)),
0238     DEF_MOD("scu-src5",     1026,   MOD_CLK_ID(1017)),
0239     DEF_MOD("scu-src4",     1027,   MOD_CLK_ID(1017)),
0240     DEF_MOD("scu-src3",     1028,   MOD_CLK_ID(1017)),
0241     DEF_MOD("scu-src2",     1029,   MOD_CLK_ID(1017)),
0242     DEF_MOD("scu-src1",     1030,   MOD_CLK_ID(1017)),
0243     DEF_MOD("scu-src0",     1031,   MOD_CLK_ID(1017)),
0244 };
0245
0246 static const unsigned int r8a774b1_crit_mod_clks[] __initconst = {
0247     MOD_CLK_ID(402),    /* RWDT */
0248     MOD_CLK_ID(408),    /* INTC-AP (GIC) */
0249 };
0250
0251 /*
0252  * CPG Clock Data
0253  */
0254
0255 /*
0256  *   MD     EXTAL       PLL0    PLL1    PLL3    PLL4    OSC
0257  * 14 13 19 17  (MHz)
0258  *-----------------------------------------------------------------
0259  * 0  0  0  0   16.66 x 1   x180    x192    x192    x144    /16
0260  * 0  0  0  1   16.66 x 1   x180    x192    x128    x144    /16
0261  * 0  0  1  0   Prohibited setting
0262  * 0  0  1  1   16.66 x 1   x180    x192    x192    x144    /16
0263  * 0  1  0  0   20    x 1   x150    x160    x160    x120    /19
0264  * 0  1  0  1   20    x 1   x150    x160    x106    x120    /19
0265  * 0  1  1  0   Prohibited setting
0266  * 0  1  1  1   20    x 1   x150    x160    x160    x120    /19
0267  * 1  0  0  0   25    x 1   x120    x128    x128    x96 /24
0268  * 1  0  0  1   25    x 1   x120    x128    x84 x96 /24
0269  * 1  0  1  0   Prohibited setting
0270  * 1  0  1  1   25    x 1   x120    x128    x128    x96 /24
0271  * 1  1  0  0   33.33 / 2   x180    x192    x192    x144    /32
0272  * 1  1  0  1   33.33 / 2   x180    x192    x128    x144    /32
0273  * 1  1  1  0   Prohibited setting
0274  * 1  1  1  1   33.33 / 2   x180    x192    x192    x144    /32
0275  */
0276 #define CPG_PLL_CONFIG_INDEX(md)    ((((md) & BIT(14)) >> 11) | \
0277                      (((md) & BIT(13)) >> 11) | \
0278                      (((md) & BIT(19)) >> 18) | \
0279                      (((md) & BIT(17)) >> 17))
0280
0281 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
0282     /* EXTAL div    PLL1 mult/div   PLL3 mult/div   OSC prediv */
0283     { 1,        192,    1,  192,    1,  16, },
0284     { 1,        192,    1,  128,    1,  16, },
0285     { 0, /* Prohibited setting */               },
0286     { 1,        192,    1,  192,    1,  16, },
0287     { 1,        160,    1,  160,    1,  19, },
0288     { 1,        160,    1,  106,    1,  19, },
0289     { 0, /* Prohibited setting */               },
0290     { 1,        160,    1,  160,    1,  19, },
0291     { 1,        128,    1,  128,    1,  24, },
0292     { 1,        128,    1,  84, 1,  24, },
0293     { 0, /* Prohibited setting */               },
0294     { 1,        128,    1,  128,    1,  24, },
0295     { 2,        192,    1,  192,    1,  32, },
0296     { 2,        192,    1,  128,    1,  32, },
0297     { 0, /* Prohibited setting */               },
0298     { 2,        192,    1,  192,    1,  32, },
0299 };
0300
0301 static int __init r8a774b1_cpg_mssr_init(struct device *dev)
0302 {
0303     const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
0304     u32 cpg_mode;
0305     int error;
0306
0307     error = rcar_rst_read_mode_pins(&cpg_mode);
0308     if (error)
0309         return error;
0310
0311     cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
0312     if (!cpg_pll_config->extal_div) {
0313         dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
0314         return -EINVAL;
0315     }
0316
0317     return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
0318 }
0319
0320 const struct cpg_mssr_info r8a774b1_cpg_mssr_info __initconst = {
0321     /* Core Clocks */
0322     .core_clks = r8a774b1_core_clks,
0323     .num_core_clks = ARRAY_SIZE(r8a774b1_core_clks),
0324     .last_dt_core_clk = LAST_DT_CORE_CLK,
0325     .num_total_core_clks = MOD_CLK_BASE,
0326
0327     /* Module Clocks */
0328     .mod_clks = r8a774b1_mod_clks,
0329     .num_mod_clks = ARRAY_SIZE(r8a774b1_mod_clks),
0330     .num_hw_mod_clks = 12 * 32,
0331
0332     /* Critical Module Clocks */
0333     .crit_mod_clks = r8a774b1_crit_mod_clks,
0334     .num_crit_mod_clks = ARRAY_SIZE(r8a774b1_crit_mod_clks),
0335
0336     /* Callbacks */
0337     .init = r8a774b1_cpg_mssr_init,
0338     .cpg_clk_register = rcar_gen3_cpg_clk_register,
0339 };