clk/renesas/r8a7742-cpg-mssr.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * r8a7742 Clock Pulse Generator / Module Standby and Software Reset
0004  *
0005  * Copyright (C) 2020 Renesas Electronics Corp.
0006  */
0007
0008 #include <linux/device.h>
0009 #include <linux/init.h>
0010 #include <linux/kernel.h>
0011 #include <linux/soc/renesas/rcar-rst.h>
0012
0013 #include <dt-bindings/clock/r8a7742-cpg-mssr.h>
0014
0015 #include "renesas-cpg-mssr.h"
0016 #include "rcar-gen2-cpg.h"
0017
0018 enum clk_ids {
0019     /* Core Clock Outputs exported to DT */
0020     LAST_DT_CORE_CLK = R8A7742_CLK_OSC,
0021
0022     /* External Input Clocks */
0023     CLK_EXTAL,
0024     CLK_USB_EXTAL,
0025
0026     /* Internal Core Clocks */
0027     CLK_MAIN,
0028     CLK_PLL0,
0029     CLK_PLL1,
0030     CLK_PLL3,
0031     CLK_PLL1_DIV2,
0032
0033     /* Module Clocks */
0034     MOD_CLK_BASE
0035 };
0036
0037 static const struct cpg_core_clk r8a7742_core_clks[] __initconst = {
0038     /* External Clock Inputs */
0039     DEF_INPUT("extal",  CLK_EXTAL),
0040     DEF_INPUT("usb_extal",  CLK_USB_EXTAL),
0041
0042     /* Internal Core Clocks */
0043     DEF_BASE(".main",   CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
0044     DEF_BASE(".pll0",   CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
0045     DEF_BASE(".pll1",   CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
0046     DEF_BASE(".pll3",   CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
0047
0048     DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
0049
0050     /* Core Clock Outputs */
0051     DEF_BASE("z",    R8A7742_CLK_Z,    CLK_TYPE_GEN2_Z, CLK_PLL0),
0052     DEF_BASE("lb",   R8A7742_CLK_LB,   CLK_TYPE_GEN2_LB,    CLK_PLL1),
0053     DEF_BASE("sdh",  R8A7742_CLK_SDH,  CLK_TYPE_GEN2_SDH,   CLK_PLL1),
0054     DEF_BASE("sd0",  R8A7742_CLK_SD0,  CLK_TYPE_GEN2_SD0,   CLK_PLL1),
0055     DEF_BASE("sd1",  R8A7742_CLK_SD1,  CLK_TYPE_GEN2_SD1,   CLK_PLL1),
0056     DEF_BASE("qspi", R8A7742_CLK_QSPI, CLK_TYPE_GEN2_QSPI,  CLK_PLL1_DIV2),
0057     DEF_BASE("rcan", R8A7742_CLK_RCAN, CLK_TYPE_GEN2_RCAN,  CLK_USB_EXTAL),
0058
0059     DEF_FIXED("z2",    R8A7742_CLK_Z2,  CLK_PLL1,       2, 1),
0060     DEF_FIXED("zg",    R8A7742_CLK_ZG,  CLK_PLL1,       3, 1),
0061     DEF_FIXED("zx",    R8A7742_CLK_ZX,  CLK_PLL1,       3, 1),
0062     DEF_FIXED("zs",    R8A7742_CLK_ZS,  CLK_PLL1,       6, 1),
0063     DEF_FIXED("hp",    R8A7742_CLK_HP,  CLK_PLL1,      12, 1),
0064     DEF_FIXED("b",     R8A7742_CLK_B,   CLK_PLL1,      12, 1),
0065     DEF_FIXED("p",     R8A7742_CLK_P,   CLK_PLL1,      24, 1),
0066     DEF_FIXED("cl",    R8A7742_CLK_CL,  CLK_PLL1,      48, 1),
0067     DEF_FIXED("m2",    R8A7742_CLK_M2,  CLK_PLL1,       8, 1),
0068     DEF_FIXED("zb3",   R8A7742_CLK_ZB3, CLK_PLL3,       4, 1),
0069     DEF_FIXED("zb3d2", R8A7742_CLK_ZB3D2,   CLK_PLL3,       8, 1),
0070     DEF_FIXED("ddr",   R8A7742_CLK_DDR, CLK_PLL3,       8, 1),
0071     DEF_FIXED("mp",    R8A7742_CLK_MP,  CLK_PLL1_DIV2,     15, 1),
0072     DEF_FIXED("cp",    R8A7742_CLK_CP,  CLK_EXTAL,      2, 1),
0073     DEF_FIXED("r",     R8A7742_CLK_R,   CLK_PLL1,   49152, 1),
0074     DEF_FIXED("osc",   R8A7742_CLK_OSC, CLK_PLL1,   12288, 1),
0075
0076     DEF_DIV6P1("sd2",  R8A7742_CLK_SD2, CLK_PLL1_DIV2,  0x078),
0077     DEF_DIV6P1("sd3",  R8A7742_CLK_SD3, CLK_PLL1_DIV2,  0x26c),
0078     DEF_DIV6P1("mmc0", R8A7742_CLK_MMC0,    CLK_PLL1_DIV2,  0x240),
0079     DEF_DIV6P1("mmc1", R8A7742_CLK_MMC1,    CLK_PLL1_DIV2,  0x244),
0080 };
0081
0082 static const struct mssr_mod_clk r8a7742_mod_clks[] __initconst = {
0083     DEF_MOD("msiof0",          0,   R8A7742_CLK_MP),
0084     DEF_MOD("vcp1",          100,   R8A7742_CLK_ZS),
0085     DEF_MOD("vcp0",          101,   R8A7742_CLK_ZS),
0086     DEF_MOD("vpc1",          102,   R8A7742_CLK_ZS),
0087     DEF_MOD("vpc0",          103,   R8A7742_CLK_ZS),
0088     DEF_MOD("tmu1",          111,   R8A7742_CLK_P),
0089     DEF_MOD("3dg",           112,   R8A7742_CLK_ZG),
0090     DEF_MOD("2d-dmac",       115,   R8A7742_CLK_ZS),
0091     DEF_MOD("fdp1-2",        117,   R8A7742_CLK_ZS),
0092     DEF_MOD("fdp1-1",        118,   R8A7742_CLK_ZS),
0093     DEF_MOD("fdp1-0",        119,   R8A7742_CLK_ZS),
0094     DEF_MOD("tmu3",          121,   R8A7742_CLK_P),
0095     DEF_MOD("tmu2",          122,   R8A7742_CLK_P),
0096     DEF_MOD("cmt0",          124,   R8A7742_CLK_R),
0097     DEF_MOD("tmu0",          125,   R8A7742_CLK_CP),
0098     DEF_MOD("vsp1du1",       127,   R8A7742_CLK_ZS),
0099     DEF_MOD("vsp1du0",       128,   R8A7742_CLK_ZS),
0100     DEF_MOD("vspr",          130,   R8A7742_CLK_ZS),
0101     DEF_MOD("vsps",          131,   R8A7742_CLK_ZS),
0102     DEF_MOD("scifa2",        202,   R8A7742_CLK_MP),
0103     DEF_MOD("scifa1",        203,   R8A7742_CLK_MP),
0104     DEF_MOD("scifa0",        204,   R8A7742_CLK_MP),
0105     DEF_MOD("msiof2",        205,   R8A7742_CLK_MP),
0106     DEF_MOD("scifb0",        206,   R8A7742_CLK_MP),
0107     DEF_MOD("scifb1",        207,   R8A7742_CLK_MP),
0108     DEF_MOD("msiof1",        208,   R8A7742_CLK_MP),
0109     DEF_MOD("msiof3",        215,   R8A7742_CLK_MP),
0110     DEF_MOD("scifb2",        216,   R8A7742_CLK_MP),
0111     DEF_MOD("sys-dmac1",         218,   R8A7742_CLK_ZS),
0112     DEF_MOD("sys-dmac0",         219,   R8A7742_CLK_ZS),
0113     DEF_MOD("iic2",          300,   R8A7742_CLK_HP),
0114     DEF_MOD("tpu0",          304,   R8A7742_CLK_CP),
0115     DEF_MOD("mmcif1",        305,   R8A7742_CLK_MMC1),
0116     DEF_MOD("scif2",         310,   R8A7742_CLK_P),
0117     DEF_MOD("sdhi3",         311,   R8A7742_CLK_SD3),
0118     DEF_MOD("sdhi2",         312,   R8A7742_CLK_SD2),
0119     DEF_MOD("sdhi1",         313,   R8A7742_CLK_SD1),
0120     DEF_MOD("sdhi0",         314,   R8A7742_CLK_SD0),
0121     DEF_MOD("mmcif0",        315,   R8A7742_CLK_MMC0),
0122     DEF_MOD("iic0",          318,   R8A7742_CLK_HP),
0123     DEF_MOD("pciec",         319,   R8A7742_CLK_MP),
0124     DEF_MOD("iic1",          323,   R8A7742_CLK_HP),
0125     DEF_MOD("usb3.0",        328,   R8A7742_CLK_MP),
0126     DEF_MOD("cmt1",          329,   R8A7742_CLK_R),
0127     DEF_MOD("usbhs-dmac0",       330,   R8A7742_CLK_HP),
0128     DEF_MOD("usbhs-dmac1",       331,   R8A7742_CLK_HP),
0129     DEF_MOD("rwdt",          402,   R8A7742_CLK_R),
0130     DEF_MOD("irqc",          407,   R8A7742_CLK_CP),
0131     DEF_MOD("intc-sys",      408,   R8A7742_CLK_ZS),
0132     DEF_MOD("audio-dmac1",       501,   R8A7742_CLK_HP),
0133     DEF_MOD("audio-dmac0",       502,   R8A7742_CLK_HP),
0134     DEF_MOD("thermal",       522,   CLK_EXTAL),
0135     DEF_MOD("pwm",           523,   R8A7742_CLK_P),
0136     DEF_MOD("usb-ehci",      703,   R8A7742_CLK_MP),
0137     DEF_MOD("usbhs",         704,   R8A7742_CLK_HP),
0138     DEF_MOD("hscif1",        716,   R8A7742_CLK_ZS),
0139     DEF_MOD("hscif0",        717,   R8A7742_CLK_ZS),
0140     DEF_MOD("scif1",         720,   R8A7742_CLK_P),
0141     DEF_MOD("scif0",         721,   R8A7742_CLK_P),
0142     DEF_MOD("du2",           722,   R8A7742_CLK_ZX),
0143     DEF_MOD("du1",           723,   R8A7742_CLK_ZX),
0144     DEF_MOD("du0",           724,   R8A7742_CLK_ZX),
0145     DEF_MOD("lvds1",         725,   R8A7742_CLK_ZX),
0146     DEF_MOD("lvds0",         726,   R8A7742_CLK_ZX),
0147     DEF_MOD("r-gp2d",        807,   R8A7742_CLK_ZX),
0148     DEF_MOD("vin3",          808,   R8A7742_CLK_ZG),
0149     DEF_MOD("vin2",          809,   R8A7742_CLK_ZG),
0150     DEF_MOD("vin1",          810,   R8A7742_CLK_ZG),
0151     DEF_MOD("vin0",          811,   R8A7742_CLK_ZG),
0152     DEF_MOD("etheravb",      812,   R8A7742_CLK_HP),
0153     DEF_MOD("ether",         813,   R8A7742_CLK_P),
0154     DEF_MOD("sata1",         814,   R8A7742_CLK_ZS),
0155     DEF_MOD("sata0",         815,   R8A7742_CLK_ZS),
0156     DEF_MOD("imr-x2-1",      820,   R8A7742_CLK_ZG),
0157     DEF_MOD("imr-x2-0",      821,   R8A7742_CLK_HP),
0158     DEF_MOD("imr-lsx2-1",        822,   R8A7742_CLK_P),
0159     DEF_MOD("imr-lsx2-0",        823,   R8A7742_CLK_ZS),
0160     DEF_MOD("gpio5",         907,   R8A7742_CLK_CP),
0161     DEF_MOD("gpio4",         908,   R8A7742_CLK_CP),
0162     DEF_MOD("gpio3",         909,   R8A7742_CLK_CP),
0163     DEF_MOD("gpio2",         910,   R8A7742_CLK_CP),
0164     DEF_MOD("gpio1",         911,   R8A7742_CLK_CP),
0165     DEF_MOD("gpio0",         912,   R8A7742_CLK_CP),
0166     DEF_MOD("can1",          915,   R8A7742_CLK_P),
0167     DEF_MOD("can0",          916,   R8A7742_CLK_P),
0168     DEF_MOD("qspi_mod",      917,   R8A7742_CLK_QSPI),
0169     DEF_MOD("iicdvfs",       926,   R8A7742_CLK_CP),
0170     DEF_MOD("i2c3",          928,   R8A7742_CLK_HP),
0171     DEF_MOD("i2c2",          929,   R8A7742_CLK_HP),
0172     DEF_MOD("i2c1",          930,   R8A7742_CLK_HP),
0173     DEF_MOD("i2c0",          931,   R8A7742_CLK_HP),
0174     DEF_MOD("ssi-all",      1005,   R8A7742_CLK_P),
0175     DEF_MOD("ssi9",         1006,   MOD_CLK_ID(1005)),
0176     DEF_MOD("ssi8",         1007,   MOD_CLK_ID(1005)),
0177     DEF_MOD("ssi7",         1008,   MOD_CLK_ID(1005)),
0178     DEF_MOD("ssi6",         1009,   MOD_CLK_ID(1005)),
0179     DEF_MOD("ssi5",         1010,   MOD_CLK_ID(1005)),
0180     DEF_MOD("ssi4",         1011,   MOD_CLK_ID(1005)),
0181     DEF_MOD("ssi3",         1012,   MOD_CLK_ID(1005)),
0182     DEF_MOD("ssi2",         1013,   MOD_CLK_ID(1005)),
0183     DEF_MOD("ssi1",         1014,   MOD_CLK_ID(1005)),
0184     DEF_MOD("ssi0",         1015,   MOD_CLK_ID(1005)),
0185     DEF_MOD("scu-all",      1017,   R8A7742_CLK_P),
0186     DEF_MOD("scu-dvc1",     1018,   MOD_CLK_ID(1017)),
0187     DEF_MOD("scu-dvc0",     1019,   MOD_CLK_ID(1017)),
0188     DEF_MOD("scu-ctu1-mix1",    1020,   MOD_CLK_ID(1017)),
0189     DEF_MOD("scu-ctu0-mix0",    1021,   MOD_CLK_ID(1017)),
0190     DEF_MOD("scu-src9",     1022,   MOD_CLK_ID(1017)),
0191     DEF_MOD("scu-src8",     1023,   MOD_CLK_ID(1017)),
0192     DEF_MOD("scu-src7",     1024,   MOD_CLK_ID(1017)),
0193     DEF_MOD("scu-src6",     1025,   MOD_CLK_ID(1017)),
0194     DEF_MOD("scu-src5",     1026,   MOD_CLK_ID(1017)),
0195     DEF_MOD("scu-src4",     1027,   MOD_CLK_ID(1017)),
0196     DEF_MOD("scu-src3",     1028,   MOD_CLK_ID(1017)),
0197     DEF_MOD("scu-src2",     1029,   MOD_CLK_ID(1017)),
0198     DEF_MOD("scu-src1",     1030,   MOD_CLK_ID(1017)),
0199     DEF_MOD("scu-src0",     1031,   MOD_CLK_ID(1017)),
0200 };
0201
0202 static const unsigned int r8a7742_crit_mod_clks[] __initconst = {
0203     MOD_CLK_ID(402),    /* RWDT */
0204     MOD_CLK_ID(408),    /* INTC-SYS (GIC) */
0205 };
0206
0207 /*
0208  * CPG Clock Data
0209  */
0210
0211 /*
0212  *    MD    EXTAL       PLL0    PLL1    PLL3
0213  * 14 13 19 (MHz)       *1  *1
0214  *---------------------------------------------------
0215  * 0  0  0  15      x172/2  x208/2  x106
0216  * 0  0  1  15      x172/2  x208/2  x88
0217  * 0  1  0  20      x130/2  x156/2  x80
0218  * 0  1  1  20      x130/2  x156/2  x66
0219  * 1  0  0  26 / 2      x200/2  x240/2  x122
0220  * 1  0  1  26 / 2      x200/2  x240/2  x102
0221  * 1  1  0  30 / 2      x172/2  x208/2  x106
0222  * 1  1  1  30 / 2      x172/2  x208/2  x88
0223  *
0224  * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
0225  */
0226 #define CPG_PLL_CONFIG_INDEX(md)    ((((md) & BIT(14)) >> 12) | \
0227                      (((md) & BIT(13)) >> 12) | \
0228                      (((md) & BIT(19)) >> 19))
0229
0230 static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
0231     /* EXTAL div    PLL1 mult   PLL3 mult */
0232     { 1,        208,        106,    },
0233     { 1,        208,        88, },
0234     { 1,        156,        80, },
0235     { 1,        156,        66, },
0236     { 2,        240,        122,    },
0237     { 2,        240,        102,    },
0238     { 2,        208,        106,    },
0239     { 2,        208,        88, },
0240 };
0241
0242 static int __init r8a7742_cpg_mssr_init(struct device *dev)
0243 {
0244     const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
0245     u32 cpg_mode;
0246     int error;
0247
0248     error = rcar_rst_read_mode_pins(&cpg_mode);
0249     if (error)
0250         return error;
0251
0252     cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
0253
0254     return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
0255 }
0256
0257 const struct cpg_mssr_info r8a7742_cpg_mssr_info __initconst = {
0258     /* Core Clocks */
0259     .core_clks = r8a7742_core_clks,
0260     .num_core_clks = ARRAY_SIZE(r8a7742_core_clks),
0261     .last_dt_core_clk = LAST_DT_CORE_CLK,
0262     .num_total_core_clks = MOD_CLK_BASE,
0263
0264     /* Module Clocks */
0265     .mod_clks = r8a7742_mod_clks,
0266     .num_mod_clks = ARRAY_SIZE(r8a7742_mod_clks),
0267     .num_hw_mod_clks = 12 * 32,
0268
0269     /* Critical Module Clocks */
0270     .crit_mod_clks = r8a7742_crit_mod_clks,
0271     .num_crit_mod_clks = ARRAY_SIZE(r8a7742_crit_mod_clks),
0272
0273     /* Callbacks */
0274     .init = r8a7742_cpg_mssr_init,
0275     .cpg_clk_register = rcar_gen2_cpg_clk_register,
0276 };