clk/renesas/clk-sh73a0.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * sh73a0 Core CPG Clocks
0004  *
0005  * Copyright (C) 2014  Ulrich Hecht
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/clk/renesas.h>
0010 #include <linux/init.h>
0011 #include <linux/io.h>
0012 #include <linux/kernel.h>
0013 #include <linux/of.h>
0014 #include <linux/of_address.h>
0015 #include <linux/slab.h>
0016 #include <linux/spinlock.h>
0017
0018 struct sh73a0_cpg {
0019     struct clk_onecell_data data;
0020     spinlock_t lock;
0021 };
0022
0023 #define CPG_FRQCRA  0x00
0024 #define CPG_FRQCRB  0x04
0025 #define CPG_SD0CKCR 0x74
0026 #define CPG_SD1CKCR 0x78
0027 #define CPG_SD2CKCR 0x7c
0028 #define CPG_PLLECR  0xd0
0029 #define CPG_PLL0CR  0xd8
0030 #define CPG_PLL1CR  0x28
0031 #define CPG_PLL2CR  0x2c
0032 #define CPG_PLL3CR  0xdc
0033 #define CPG_CKSCR   0xc0
0034 #define CPG_DSI0PHYCR   0x6c
0035 #define CPG_DSI1PHYCR   0x70
0036
0037 #define CLK_ENABLE_ON_INIT BIT(0)
0038
0039 struct div4_clk {
0040     const char *name;
0041     const char *parent;
0042     unsigned int reg;
0043     unsigned int shift;
0044 };
0045
0046 static const struct div4_clk div4_clks[] = {
0047     { "zg", "pll0", CPG_FRQCRA, 16 },
0048     { "m3", "pll1", CPG_FRQCRA, 12 },
0049     { "b",  "pll1", CPG_FRQCRA,  8 },
0050     { "m1", "pll1", CPG_FRQCRA,  4 },
0051     { "m2", "pll1", CPG_FRQCRA,  0 },
0052     { "zx", "pll1", CPG_FRQCRB, 12 },
0053     { "hp", "pll1", CPG_FRQCRB,  4 },
0054     { NULL, NULL, 0, 0 },
0055 };
0056
0057 static const struct clk_div_table div4_div_table[] = {
0058     { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
0059     { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
0060     { 12, 7 }, { 0, 0 }
0061 };
0062
0063 static const struct clk_div_table z_div_table[] = {
0064     /* ZSEL == 0 */
0065     { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, { 4, 1 }, { 5, 1 },
0066     { 6, 1 }, { 7, 1 }, { 8, 1 }, { 9, 1 }, { 10, 1 }, { 11, 1 },
0067     { 12, 1 }, { 13, 1 }, { 14, 1 }, { 15, 1 },
0068     /* ZSEL == 1 */
0069     { 16, 2 }, { 17, 3 }, { 18, 4 }, { 19, 6 }, { 20, 8 }, { 21, 12 },
0070     { 22, 16 }, { 24, 24 }, { 27, 48 }, { 0, 0 }
0071 };
0072
0073 static struct clk * __init
0074 sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
0075               void __iomem *base, const char *name)
0076 {
0077     const struct clk_div_table *table = NULL;
0078     unsigned int shift, reg, width;
0079     const char *parent_name = NULL;
0080     unsigned int mult = 1;
0081     unsigned int div = 1;
0082
0083     if (!strcmp(name, "main")) {
0084         /* extal1, extal1_div2, extal2, extal2_div2 */
0085         u32 parent_idx = (readl(base + CPG_CKSCR) >> 28) & 3;
0086
0087         parent_name = of_clk_get_parent_name(np, parent_idx >> 1);
0088         div = (parent_idx & 1) + 1;
0089     } else if (!strncmp(name, "pll", 3)) {
0090         void __iomem *enable_reg = base;
0091         u32 enable_bit = name[3] - '0';
0092
0093         parent_name = "main";
0094         switch (enable_bit) {
0095         case 0:
0096             enable_reg += CPG_PLL0CR;
0097             break;
0098         case 1:
0099             enable_reg += CPG_PLL1CR;
0100             break;
0101         case 2:
0102             enable_reg += CPG_PLL2CR;
0103             break;
0104         case 3:
0105             enable_reg += CPG_PLL3CR;
0106             break;
0107         default:
0108             return ERR_PTR(-EINVAL);
0109         }
0110         if (readl(base + CPG_PLLECR) & BIT(enable_bit)) {
0111             mult = ((readl(enable_reg) >> 24) & 0x3f) + 1;
0112             /* handle CFG bit for PLL1 and PLL2 */
0113             if (enable_bit == 1 || enable_bit == 2)
0114                 if (readl(enable_reg) & BIT(20))
0115                     mult *= 2;
0116         }
0117     } else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {
0118         u32 phy_no = name[3] - '0';
0119         void __iomem *dsi_reg = base +
0120             (phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR);
0121
0122         parent_name = phy_no ? "dsi1pck" : "dsi0pck";
0123         mult = readl(dsi_reg);
0124         if (!(mult & 0x8000))
0125             mult = 1;
0126         else
0127             mult = (mult & 0x3f) + 1;
0128     } else if (!strcmp(name, "z")) {
0129         parent_name = "pll0";
0130         table = z_div_table;
0131         reg = CPG_FRQCRB;
0132         shift = 24;
0133         width = 5;
0134     } else {
0135         const struct div4_clk *c;
0136
0137         for (c = div4_clks; c->name; c++) {
0138             if (!strcmp(name, c->name)) {
0139                 parent_name = c->parent;
0140                 table = div4_div_table;
0141                 reg = c->reg;
0142                 shift = c->shift;
0143                 width = 4;
0144                 break;
0145             }
0146         }
0147         if (!c->name)
0148             return ERR_PTR(-EINVAL);
0149     }
0150
0151     if (!table) {
0152         return clk_register_fixed_factor(NULL, name, parent_name, 0,
0153                          mult, div);
0154     } else {
0155         return clk_register_divider_table(NULL, name, parent_name, 0,
0156                           base + reg, shift, width, 0,
0157                           table, &cpg->lock);
0158     }
0159 }
0160
0161 static void __init sh73a0_cpg_clocks_init(struct device_node *np)
0162 {
0163     struct sh73a0_cpg *cpg;
0164     void __iomem *base;
0165     struct clk **clks;
0166     unsigned int i;
0167     int num_clks;
0168
0169     num_clks = of_property_count_strings(np, "clock-output-names");
0170     if (num_clks < 0) {
0171         pr_err("%s: failed to count clocks\n", __func__);
0172         return;
0173     }
0174
0175     cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
0176     clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
0177     if (cpg == NULL || clks == NULL) {
0178         /* We're leaking memory on purpose, there's no point in cleaning
0179          * up as the system won't boot anyway.
0180          */
0181         return;
0182     }
0183
0184     spin_lock_init(&cpg->lock);
0185
0186     cpg->data.clks = clks;
0187     cpg->data.clk_num = num_clks;
0188
0189     base = of_iomap(np, 0);
0190     if (WARN_ON(base == NULL))
0191         return;
0192
0193     /* Set SDHI clocks to a known state */
0194     writel(0x108, base + CPG_SD0CKCR);
0195     writel(0x108, base + CPG_SD1CKCR);
0196     writel(0x108, base + CPG_SD2CKCR);
0197
0198     for (i = 0; i < num_clks; ++i) {
0199         const char *name;
0200         struct clk *clk;
0201
0202         of_property_read_string_index(np, "clock-output-names", i,
0203                           &name);
0204
0205         clk = sh73a0_cpg_register_clock(np, cpg, base, name);
0206         if (IS_ERR(clk))
0207             pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
0208                    __func__, np, name, PTR_ERR(clk));
0209         else
0210             cpg->data.clks[i] = clk;
0211     }
0212
0213     of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
0214 }
0215 CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks",
0216            sh73a0_cpg_clocks_init);