clk/renesas/clk-rz.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * RZ/A1 Core CPG Clocks
0004  *
0005  * Copyright (C) 2013 Ideas On Board SPRL
0006  * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
0007  */
0008
0009 #include <linux/clk-provider.h>
0010 #include <linux/clk/renesas.h>
0011 #include <linux/init.h>
0012 #include <linux/io.h>
0013 #include <linux/kernel.h>
0014 #include <linux/of.h>
0015 #include <linux/of_address.h>
0016 #include <linux/slab.h>
0017
0018 #define CPG_FRQCR   0x10
0019 #define CPG_FRQCR2  0x14
0020
0021 #define PPR0        0xFCFE3200
0022 #define PIBC0       0xFCFE7000
0023
0024 #define MD_CLK(x)   ((x >> 2) & 1)  /* P0_2 */
0025
0026 /* -----------------------------------------------------------------------------
0027  * Initialization
0028  */
0029
0030 static u16 __init rz_cpg_read_mode_pins(void)
0031 {
0032     void __iomem *ppr0, *pibc0;
0033     u16 modes;
0034
0035     ppr0 = ioremap(PPR0, 2);
0036     pibc0 = ioremap(PIBC0, 2);
0037     BUG_ON(!ppr0 || !pibc0);
0038     iowrite16(4, pibc0);    /* enable input buffer */
0039     modes = ioread16(ppr0);
0040     iounmap(ppr0);
0041     iounmap(pibc0);
0042
0043     return modes;
0044 }
0045
0046 static struct clk * __init
0047 rz_cpg_register_clock(struct device_node *np, void __iomem *base,
0048               const char *name)
0049 {
0050     u32 val;
0051     unsigned mult;
0052     static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };
0053
0054     if (strcmp(name, "pll") == 0) {
0055         unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());
0056         const char *parent_name = of_clk_get_parent_name(np, cpg_mode);
0057
0058         mult = cpg_mode ? (32 / 4) : 30;
0059
0060         return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
0061     }
0062
0063     /* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
0064     if (!base)
0065         return ERR_PTR(-ENXIO);
0066
0067     /* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
0068      * and the constraint that always g <= i. To get the rz platform started,
0069      * let them run at fixed current speed and implement the details later.
0070      */
0071     if (strcmp(name, "i") == 0)
0072         val = (readl(base + CPG_FRQCR) >> 8) & 3;
0073     else if (strcmp(name, "g") == 0)
0074         val = readl(base + CPG_FRQCR2) & 3;
0075     else
0076         return ERR_PTR(-EINVAL);
0077
0078     mult = frqcr_tab[val];
0079     return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3);
0080 }
0081
0082 static void __init rz_cpg_clocks_init(struct device_node *np)
0083 {
0084     struct clk_onecell_data *data;
0085     struct clk **clks;
0086     void __iomem *base;
0087     unsigned i;
0088     int num_clks;
0089
0090     num_clks = of_property_count_strings(np, "clock-output-names");
0091     if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
0092         return;
0093
0094     data = kzalloc(sizeof(*data), GFP_KERNEL);
0095     clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
0096     BUG_ON(!data || !clks);
0097
0098     data->clks = clks;
0099     data->clk_num = num_clks;
0100
0101     base = of_iomap(np, 0);
0102
0103     for (i = 0; i < num_clks; ++i) {
0104         const char *name;
0105         struct clk *clk;
0106
0107         of_property_read_string_index(np, "clock-output-names", i, &name);
0108
0109         clk = rz_cpg_register_clock(np, base, name);
0110         if (IS_ERR(clk))
0111             pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
0112                    __func__, np, name, PTR_ERR(clk));
0113         else
0114             data->clks[i] = clk;
0115     }
0116
0117     of_clk_add_provider(np, of_clk_src_onecell_get, data);
0118
0119     cpg_mstp_add_clk_domain(np);
0120 }
0121 CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);