clk/renesas/clk-r8a7779.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * r8a7779 Core CPG Clocks
0004  *
0005  * Copyright (C) 2013, 2014 Horms Solutions Ltd.
0006  *
0007  * Contact: Simon Horman <horms@verge.net.au>
0008  */
0009
0010 #include <linux/clk-provider.h>
0011 #include <linux/clk/renesas.h>
0012 #include <linux/init.h>
0013 #include <linux/kernel.h>
0014 #include <linux/of.h>
0015 #include <linux/of_address.h>
0016 #include <linux/slab.h>
0017 #include <linux/spinlock.h>
0018 #include <linux/soc/renesas/rcar-rst.h>
0019
0020 #include <dt-bindings/clock/r8a7779-clock.h>
0021
0022 #define CPG_NUM_CLOCKS          (R8A7779_CLK_OUT + 1)
0023
0024 /* -----------------------------------------------------------------------------
0025  * CPG Clock Data
0026  */
0027
0028 /*
0029  *      MD1 = 1         MD1 = 0
0030  *      (PLLA = 1500)       (PLLA = 1600)
0031  *      (MHz)           (MHz)
0032  *------------------------------------------------+--------------------
0033  * clkz     1000   (2/3)        800   (1/2)
0034  * clkzs     250   (1/6)        200   (1/8)
0035  * clki      750   (1/2)        800   (1/2)
0036  * clks      250   (1/6)        200   (1/8)
0037  * clks1     125   (1/12)       100   (1/16)
0038  * clks3     187.5 (1/8)        200   (1/8)
0039  * clks4      93.7 (1/16)       100   (1/16)
0040  * clkp       62.5 (1/24)        50   (1/32)
0041  * clkg       62.5 (1/24)        66.6 (1/24)
0042  * clkb, CLKOUT
0043  * (MD2 = 0)      62.5 (1/24)        66.6 (1/24)
0044  * (MD2 = 1)      41.6 (1/36)        50   (1/32)
0045  */
0046
0047 #define CPG_CLK_CONFIG_INDEX(md)    (((md) & (BIT(2)|BIT(1))) >> 1)
0048
0049 struct cpg_clk_config {
0050     unsigned int z_mult;
0051     unsigned int z_div;
0052     unsigned int zs_and_s_div;
0053     unsigned int s1_div;
0054     unsigned int p_div;
0055     unsigned int b_and_out_div;
0056 };
0057
0058 static const struct cpg_clk_config cpg_clk_configs[4] __initconst = {
0059     { 1, 2, 8, 16, 32, 24 },
0060     { 2, 3, 6, 12, 24, 24 },
0061     { 1, 2, 8, 16, 32, 32 },
0062     { 2, 3, 6, 12, 24, 36 },
0063 };
0064
0065 /*
0066  *   MD     PLLA Ratio
0067  * 12 11
0068  *------------------------
0069  * 0  0     x42
0070  * 0  1     x48
0071  * 1  0     x56
0072  * 1  1     x64
0073  */
0074
0075 #define CPG_PLLA_MULT_INDEX(md) (((md) & (BIT(12)|BIT(11))) >> 11)
0076
0077 static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 };
0078
0079 /* -----------------------------------------------------------------------------
0080  * Initialization
0081  */
0082
0083 static struct clk * __init
0084 r8a7779_cpg_register_clock(struct device_node *np,
0085                const struct cpg_clk_config *config,
0086                unsigned int plla_mult, const char *name)
0087 {
0088     const char *parent_name = "plla";
0089     unsigned int mult = 1;
0090     unsigned int div = 1;
0091
0092     if (!strcmp(name, "plla")) {
0093         parent_name = of_clk_get_parent_name(np, 0);
0094         mult = plla_mult;
0095     } else if (!strcmp(name, "z")) {
0096         div = config->z_div;
0097         mult = config->z_mult;
0098     } else if (!strcmp(name, "zs") || !strcmp(name, "s")) {
0099         div = config->zs_and_s_div;
0100     } else if (!strcmp(name, "s1")) {
0101         div = config->s1_div;
0102     } else if (!strcmp(name, "p")) {
0103         div = config->p_div;
0104     } else if (!strcmp(name, "b") || !strcmp(name, "out")) {
0105         div = config->b_and_out_div;
0106     } else {
0107         return ERR_PTR(-EINVAL);
0108     }
0109
0110     return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
0111 }
0112
0113 static void __init r8a7779_cpg_clocks_init(struct device_node *np)
0114 {
0115     const struct cpg_clk_config *config;
0116     struct clk_onecell_data *data;
0117     struct clk **clks;
0118     unsigned int i, plla_mult;
0119     int num_clks;
0120     u32 mode;
0121
0122     if (rcar_rst_read_mode_pins(&mode))
0123         return;
0124
0125     num_clks = of_property_count_strings(np, "clock-output-names");
0126     if (num_clks < 0) {
0127         pr_err("%s: failed to count clocks\n", __func__);
0128         return;
0129     }
0130
0131     data = kzalloc(sizeof(*data), GFP_KERNEL);
0132     clks = kcalloc(CPG_NUM_CLOCKS, sizeof(*clks), GFP_KERNEL);
0133     if (data == NULL || clks == NULL) {
0134         /* We're leaking memory on purpose, there's no point in cleaning
0135          * up as the system won't boot anyway.
0136          */
0137         return;
0138     }
0139
0140     data->clks = clks;
0141     data->clk_num = num_clks;
0142
0143     config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)];
0144     plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)];
0145
0146     for (i = 0; i < num_clks; ++i) {
0147         const char *name;
0148         struct clk *clk;
0149
0150         of_property_read_string_index(np, "clock-output-names", i,
0151                           &name);
0152
0153         clk = r8a7779_cpg_register_clock(np, config, plla_mult, name);
0154         if (IS_ERR(clk))
0155             pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
0156                    __func__, np, name, PTR_ERR(clk));
0157         else
0158             data->clks[i] = clk;
0159     }
0160
0161     of_clk_add_provider(np, of_clk_src_onecell_get, data);
0162
0163     cpg_mstp_add_clk_domain(np);
0164 }
0165 CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
0166            r8a7779_cpg_clocks_init);