clk/renesas/clk-r8a7740.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * r8a7740 Core CPG Clocks
0004  *
0005  * Copyright (C) 2014  Ulrich Hecht
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/clk/renesas.h>
0010 #include <linux/init.h>
0011 #include <linux/io.h>
0012 #include <linux/kernel.h>
0013 #include <linux/slab.h>
0014 #include <linux/of.h>
0015 #include <linux/of_address.h>
0016 #include <linux/spinlock.h>
0017
0018 struct r8a7740_cpg {
0019     struct clk_onecell_data data;
0020     spinlock_t lock;
0021 };
0022
0023 #define CPG_FRQCRA  0x00
0024 #define CPG_FRQCRB  0x04
0025 #define CPG_PLLC2CR 0x2c
0026 #define CPG_USBCKCR 0x8c
0027 #define CPG_FRQCRC  0xe0
0028
0029 #define CLK_ENABLE_ON_INIT BIT(0)
0030
0031 struct div4_clk {
0032     const char *name;
0033     unsigned int reg;
0034     unsigned int shift;
0035     int flags;
0036 };
0037
0038 static struct div4_clk div4_clks[] = {
0039     { "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT },
0040     { "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT },
0041     { "b", CPG_FRQCRA,  8, CLK_ENABLE_ON_INIT },
0042     { "m1", CPG_FRQCRA,  4, CLK_ENABLE_ON_INIT },
0043     { "hp", CPG_FRQCRB,  4, 0 },
0044     { "hpp", CPG_FRQCRC, 20, 0 },
0045     { "usbp", CPG_FRQCRC, 16, 0 },
0046     { "s", CPG_FRQCRC, 12, 0 },
0047     { "zb", CPG_FRQCRC,  8, 0 },
0048     { "m3", CPG_FRQCRC,  4, 0 },
0049     { "cp", CPG_FRQCRC,  0, 0 },
0050     { NULL, 0, 0, 0 },
0051 };
0052
0053 static const struct clk_div_table div4_div_table[] = {
0054     { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
0055     { 6, 16 }, { 7, 18 }, { 8, 24 }, { 9, 32 }, { 10, 36 }, { 11, 48 },
0056     { 13, 72 }, { 14, 96 }, { 0, 0 }
0057 };
0058
0059 static u32 cpg_mode __initdata;
0060
0061 static struct clk * __init
0062 r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
0063                void __iomem *base, const char *name)
0064 {
0065     const struct clk_div_table *table = NULL;
0066     const char *parent_name;
0067     unsigned int shift, reg;
0068     unsigned int mult = 1;
0069     unsigned int div = 1;
0070
0071     if (!strcmp(name, "r")) {
0072         switch (cpg_mode & (BIT(2) | BIT(1))) {
0073         case BIT(1) | BIT(2):
0074             /* extal1 */
0075             parent_name = of_clk_get_parent_name(np, 0);
0076             div = 2048;
0077             break;
0078         case BIT(2):
0079             /* extal1 */
0080             parent_name = of_clk_get_parent_name(np, 0);
0081             div = 1024;
0082             break;
0083         default:
0084             /* extalr */
0085             parent_name = of_clk_get_parent_name(np, 2);
0086             break;
0087         }
0088     } else if (!strcmp(name, "system")) {
0089         parent_name = of_clk_get_parent_name(np, 0);
0090         if (cpg_mode & BIT(1))
0091             div = 2;
0092     } else if (!strcmp(name, "pllc0")) {
0093         /* PLLC0/1 are configurable multiplier clocks. Register them as
0094          * fixed factor clocks for now as there's no generic multiplier
0095          * clock implementation and we currently have no need to change
0096          * the multiplier value.
0097          */
0098         u32 value = readl(base + CPG_FRQCRC);
0099         parent_name = "system";
0100         mult = ((value >> 24) & 0x7f) + 1;
0101     } else if (!strcmp(name, "pllc1")) {
0102         u32 value = readl(base + CPG_FRQCRA);
0103         parent_name = "system";
0104         mult = ((value >> 24) & 0x7f) + 1;
0105         div = 2;
0106     } else if (!strcmp(name, "pllc2")) {
0107         u32 value = readl(base + CPG_PLLC2CR);
0108         parent_name = "system";
0109         mult = ((value >> 24) & 0x3f) + 1;
0110     } else if (!strcmp(name, "usb24s")) {
0111         u32 value = readl(base + CPG_USBCKCR);
0112         if (value & BIT(7))
0113             /* extal2 */
0114             parent_name = of_clk_get_parent_name(np, 1);
0115         else
0116             parent_name = "system";
0117         if (!(value & BIT(6)))
0118             div = 2;
0119     } else {
0120         struct div4_clk *c;
0121         for (c = div4_clks; c->name; c++) {
0122             if (!strcmp(name, c->name)) {
0123                 parent_name = "pllc1";
0124                 table = div4_div_table;
0125                 reg = c->reg;
0126                 shift = c->shift;
0127                 break;
0128             }
0129         }
0130         if (!c->name)
0131             return ERR_PTR(-EINVAL);
0132     }
0133
0134     if (!table) {
0135         return clk_register_fixed_factor(NULL, name, parent_name, 0,
0136                          mult, div);
0137     } else {
0138         return clk_register_divider_table(NULL, name, parent_name, 0,
0139                           base + reg, shift, 4, 0,
0140                           table, &cpg->lock);
0141     }
0142 }
0143
0144 static void __init r8a7740_cpg_clocks_init(struct device_node *np)
0145 {
0146     struct r8a7740_cpg *cpg;
0147     void __iomem *base;
0148     struct clk **clks;
0149     unsigned int i;
0150     int num_clks;
0151
0152     if (of_property_read_u32(np, "renesas,mode", &cpg_mode))
0153         pr_warn("%s: missing renesas,mode property\n", __func__);
0154
0155     num_clks = of_property_count_strings(np, "clock-output-names");
0156     if (num_clks < 0) {
0157         pr_err("%s: failed to count clocks\n", __func__);
0158         return;
0159     }
0160
0161     cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
0162     clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
0163     if (cpg == NULL || clks == NULL) {
0164         /* We're leaking memory on purpose, there's no point in cleaning
0165          * up as the system won't boot anyway.
0166          */
0167         return;
0168     }
0169
0170     spin_lock_init(&cpg->lock);
0171
0172     cpg->data.clks = clks;
0173     cpg->data.clk_num = num_clks;
0174
0175     base = of_iomap(np, 0);
0176     if (WARN_ON(base == NULL))
0177         return;
0178
0179     for (i = 0; i < num_clks; ++i) {
0180         const char *name;
0181         struct clk *clk;
0182
0183         of_property_read_string_index(np, "clock-output-names", i,
0184                           &name);
0185
0186         clk = r8a7740_cpg_register_clock(np, cpg, base, name);
0187         if (IS_ERR(clk))
0188             pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
0189                    __func__, np, name, PTR_ERR(clk));
0190         else
0191             cpg->data.clks[i] = clk;
0192     }
0193
0194     of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
0195 }
0196 CLK_OF_DECLARE(r8a7740_cpg_clks, "renesas,r8a7740-cpg-clocks",
0197            r8a7740_cpg_clocks_init);