clk/renesas/clk-r8a73a4.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * r8a73a4 Core CPG Clocks
0004  *
0005  * Copyright (C) 2014  Ulrich Hecht
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/clk/renesas.h>
0010 #include <linux/init.h>
0011 #include <linux/io.h>
0012 #include <linux/kernel.h>
0013 #include <linux/slab.h>
0014 #include <linux/of.h>
0015 #include <linux/of_address.h>
0016 #include <linux/spinlock.h>
0017
0018 struct r8a73a4_cpg {
0019     struct clk_onecell_data data;
0020     spinlock_t lock;
0021 };
0022
0023 #define CPG_CKSCR   0xc0
0024 #define CPG_FRQCRA  0x00
0025 #define CPG_FRQCRB  0x04
0026 #define CPG_FRQCRC  0xe0
0027 #define CPG_PLL0CR  0xd8
0028 #define CPG_PLL1CR  0x28
0029 #define CPG_PLL2CR  0x2c
0030 #define CPG_PLL2HCR 0xe4
0031 #define CPG_PLL2SCR 0xf4
0032
0033 #define CLK_ENABLE_ON_INIT BIT(0)
0034
0035 struct div4_clk {
0036     const char *name;
0037     unsigned int reg;
0038     unsigned int shift;
0039 };
0040
0041 static struct div4_clk div4_clks[] = {
0042     { "i",  CPG_FRQCRA, 20 },
0043     { "m3", CPG_FRQCRA, 12 },
0044     { "b",  CPG_FRQCRA,  8 },
0045     { "m1", CPG_FRQCRA,  4 },
0046     { "m2", CPG_FRQCRA,  0 },
0047     { "zx", CPG_FRQCRB, 12 },
0048     { "zs", CPG_FRQCRB,  8 },
0049     { "hp", CPG_FRQCRB,  4 },
0050     { NULL, 0, 0 },
0051 };
0052
0053 static const struct clk_div_table div4_div_table[] = {
0054     { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
0055     { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
0056     { 12, 10 }, { 0, 0 }
0057 };
0058
0059 static struct clk * __init
0060 r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
0061                void __iomem *base, const char *name)
0062 {
0063     const struct clk_div_table *table = NULL;
0064     const char *parent_name;
0065     unsigned int shift, reg;
0066     unsigned int mult = 1;
0067     unsigned int div = 1;
0068
0069
0070     if (!strcmp(name, "main")) {
0071         u32 ckscr = readl(base + CPG_CKSCR);
0072
0073         switch ((ckscr >> 28) & 3) {
0074         case 0: /* extal1 */
0075             parent_name = of_clk_get_parent_name(np, 0);
0076             break;
0077         case 1: /* extal1 / 2 */
0078             parent_name = of_clk_get_parent_name(np, 0);
0079             div = 2;
0080             break;
0081         case 2: /* extal2 */
0082             parent_name = of_clk_get_parent_name(np, 1);
0083             break;
0084         case 3: /* extal2 / 2 */
0085             parent_name = of_clk_get_parent_name(np, 1);
0086             div = 2;
0087             break;
0088         }
0089     } else if (!strcmp(name, "pll0")) {
0090         /* PLL0/1 are configurable multiplier clocks. Register them as
0091          * fixed factor clocks for now as there's no generic multiplier
0092          * clock implementation and we currently have no need to change
0093          * the multiplier value.
0094          */
0095         u32 value = readl(base + CPG_PLL0CR);
0096
0097         parent_name = "main";
0098         mult = ((value >> 24) & 0x7f) + 1;
0099         if (value & BIT(20))
0100             div = 2;
0101     } else if (!strcmp(name, "pll1")) {
0102         u32 value = readl(base + CPG_PLL1CR);
0103
0104         parent_name = "main";
0105         /* XXX: enable bit? */
0106         mult = ((value >> 24) & 0x7f) + 1;
0107         if (value & BIT(7))
0108             div = 2;
0109     } else if (!strncmp(name, "pll2", 4)) {
0110         u32 value, cr;
0111
0112         switch (name[4]) {
0113         case 0:
0114             cr = CPG_PLL2CR;
0115             break;
0116         case 's':
0117             cr = CPG_PLL2SCR;
0118             break;
0119         case 'h':
0120             cr = CPG_PLL2HCR;
0121             break;
0122         default:
0123             return ERR_PTR(-EINVAL);
0124         }
0125         value = readl(base + cr);
0126         switch ((value >> 5) & 7) {
0127         case 0:
0128             parent_name = "main";
0129             div = 2;
0130             break;
0131         case 1:
0132             parent_name = "extal2";
0133             div = 2;
0134             break;
0135         case 3:
0136             parent_name = "extal2";
0137             div = 4;
0138             break;
0139         case 4:
0140             parent_name = "main";
0141             break;
0142         case 5:
0143             parent_name = "extal2";
0144             break;
0145         default:
0146             pr_warn("%s: unexpected parent of %s\n", __func__,
0147                 name);
0148             return ERR_PTR(-EINVAL);
0149         }
0150         /* XXX: enable bit? */
0151         mult = ((value >> 24) & 0x7f) + 1;
0152     } else if (!strcmp(name, "z") || !strcmp(name, "z2")) {
0153         u32 shift = 8;
0154
0155         parent_name = "pll0";
0156         if (name[1] == '2') {
0157             div = 2;
0158             shift = 0;
0159         }
0160         div *= 32;
0161         mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f);
0162     } else {
0163         struct div4_clk *c;
0164
0165         for (c = div4_clks; c->name; c++) {
0166             if (!strcmp(name, c->name))
0167                 break;
0168         }
0169         if (!c->name)
0170             return ERR_PTR(-EINVAL);
0171
0172         parent_name = "pll1";
0173         table = div4_div_table;
0174         reg = c->reg;
0175         shift = c->shift;
0176     }
0177
0178     if (!table) {
0179         return clk_register_fixed_factor(NULL, name, parent_name, 0,
0180                          mult, div);
0181     } else {
0182         return clk_register_divider_table(NULL, name, parent_name, 0,
0183                           base + reg, shift, 4, 0,
0184                           table, &cpg->lock);
0185     }
0186 }
0187
0188 static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
0189 {
0190     struct r8a73a4_cpg *cpg;
0191     void __iomem *base;
0192     struct clk **clks;
0193     unsigned int i;
0194     int num_clks;
0195
0196     num_clks = of_property_count_strings(np, "clock-output-names");
0197     if (num_clks < 0) {
0198         pr_err("%s: failed to count clocks\n", __func__);
0199         return;
0200     }
0201
0202     cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
0203     clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
0204     if (cpg == NULL || clks == NULL) {
0205         /* We're leaking memory on purpose, there's no point in cleaning
0206          * up as the system won't boot anyway.
0207          */
0208         return;
0209     }
0210
0211     spin_lock_init(&cpg->lock);
0212
0213     cpg->data.clks = clks;
0214     cpg->data.clk_num = num_clks;
0215
0216     base = of_iomap(np, 0);
0217     if (WARN_ON(base == NULL))
0218         return;
0219
0220     for (i = 0; i < num_clks; ++i) {
0221         const char *name;
0222         struct clk *clk;
0223
0224         of_property_read_string_index(np, "clock-output-names", i,
0225                           &name);
0226
0227         clk = r8a73a4_cpg_register_clock(np, cpg, base, name);
0228         if (IS_ERR(clk))
0229             pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
0230                    __func__, np, name, PTR_ERR(clk));
0231         else
0232             cpg->data.clks[i] = clk;
0233     }
0234
0235     of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
0236 }
0237 CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks",
0238            r8a73a4_cpg_clocks_init);