clk/renesas/clk-mstp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * R-Car MSTP clocks
0004  *
0005  * Copyright (C) 2013 Ideas On Board SPRL
0006  * Copyright (C) 2015 Glider bvba
0007  *
0008  * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
0009  */
0010
0011 #include <linux/clk.h>
0012 #include <linux/clk-provider.h>
0013 #include <linux/clkdev.h>
0014 #include <linux/clk/renesas.h>
0015 #include <linux/device.h>
0016 #include <linux/io.h>
0017 #include <linux/of.h>
0018 #include <linux/of_address.h>
0019 #include <linux/pm_clock.h>
0020 #include <linux/pm_domain.h>
0021 #include <linux/spinlock.h>
0022
0023 /*
0024  * MSTP clocks. We can't use standard gate clocks as we need to poll on the
0025  * status register when enabling the clock.
0026  */
0027
0028 #define MSTP_MAX_CLOCKS     32
0029
0030 /**
0031  * struct mstp_clock_group - MSTP gating clocks group
0032  *
0033  * @data: clock specifier translation for clocks in this group
0034  * @smstpcr: module stop control register
0035  * @mstpsr: module stop status register (optional)
0036  * @lock: protects writes to SMSTPCR
0037  * @width_8bit: registers are 8-bit, not 32-bit
0038  * @clks: clocks in this group
0039  */
0040 struct mstp_clock_group {
0041     struct clk_onecell_data data;
0042     void __iomem *smstpcr;
0043     void __iomem *mstpsr;
0044     spinlock_t lock;
0045     bool width_8bit;
0046     struct clk *clks[];
0047 };
0048
0049 /**
0050  * struct mstp_clock - MSTP gating clock
0051  * @hw: handle between common and hardware-specific interfaces
0052  * @bit_index: control bit index
0053  * @group: MSTP clocks group
0054  */
0055 struct mstp_clock {
0056     struct clk_hw hw;
0057     u32 bit_index;
0058     struct mstp_clock_group *group;
0059 };
0060
0061 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
0062
0063 static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
0064                 u32 __iomem *reg)
0065 {
0066     return group->width_8bit ? readb(reg) : readl(reg);
0067 }
0068
0069 static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
0070                   u32 __iomem *reg)
0071 {
0072     group->width_8bit ? writeb(val, reg) : writel(val, reg);
0073 }
0074
0075 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
0076 {
0077     struct mstp_clock *clock = to_mstp_clock(hw);
0078     struct mstp_clock_group *group = clock->group;
0079     u32 bitmask = BIT(clock->bit_index);
0080     unsigned long flags;
0081     unsigned int i;
0082     u32 value;
0083
0084     spin_lock_irqsave(&group->lock, flags);
0085
0086     value = cpg_mstp_read(group, group->smstpcr);
0087     if (enable)
0088         value &= ~bitmask;
0089     else
0090         value |= bitmask;
0091     cpg_mstp_write(group, value, group->smstpcr);
0092
0093     if (!group->mstpsr) {
0094         /* dummy read to ensure write has completed */
0095         cpg_mstp_read(group, group->smstpcr);
0096         barrier_data(group->smstpcr);
0097     }
0098
0099     spin_unlock_irqrestore(&group->lock, flags);
0100
0101     if (!enable || !group->mstpsr)
0102         return 0;
0103
0104     for (i = 1000; i > 0; --i) {
0105         if (!(cpg_mstp_read(group, group->mstpsr) & bitmask))
0106             break;
0107         cpu_relax();
0108     }
0109
0110     if (!i) {
0111         pr_err("%s: failed to enable %p[%d]\n", __func__,
0112                group->smstpcr, clock->bit_index);
0113         return -ETIMEDOUT;
0114     }
0115
0116     return 0;
0117 }
0118
0119 static int cpg_mstp_clock_enable(struct clk_hw *hw)
0120 {
0121     return cpg_mstp_clock_endisable(hw, true);
0122 }
0123
0124 static void cpg_mstp_clock_disable(struct clk_hw *hw)
0125 {
0126     cpg_mstp_clock_endisable(hw, false);
0127 }
0128
0129 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
0130 {
0131     struct mstp_clock *clock = to_mstp_clock(hw);
0132     struct mstp_clock_group *group = clock->group;
0133     u32 value;
0134
0135     if (group->mstpsr)
0136         value = cpg_mstp_read(group, group->mstpsr);
0137     else
0138         value = cpg_mstp_read(group, group->smstpcr);
0139
0140     return !(value & BIT(clock->bit_index));
0141 }
0142
0143 static const struct clk_ops cpg_mstp_clock_ops = {
0144     .enable = cpg_mstp_clock_enable,
0145     .disable = cpg_mstp_clock_disable,
0146     .is_enabled = cpg_mstp_clock_is_enabled,
0147 };
0148
0149 static struct clk * __init cpg_mstp_clock_register(const char *name,
0150     const char *parent_name, unsigned int index,
0151     struct mstp_clock_group *group)
0152 {
0153     struct clk_init_data init = {};
0154     struct mstp_clock *clock;
0155     struct clk *clk;
0156
0157     clock = kzalloc(sizeof(*clock), GFP_KERNEL);
0158     if (!clock)
0159         return ERR_PTR(-ENOMEM);
0160
0161     init.name = name;
0162     init.ops = &cpg_mstp_clock_ops;
0163     init.flags = CLK_SET_RATE_PARENT;
0164     /* INTC-SYS is the module clock of the GIC, and must not be disabled */
0165     if (!strcmp(name, "intc-sys")) {
0166         pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name);
0167         init.flags |= CLK_IS_CRITICAL;
0168     }
0169     init.parent_names = &parent_name;
0170     init.num_parents = 1;
0171
0172     clock->bit_index = index;
0173     clock->group = group;
0174     clock->hw.init = &init;
0175
0176     clk = clk_register(NULL, &clock->hw);
0177
0178     if (IS_ERR(clk))
0179         kfree(clock);
0180
0181     return clk;
0182 }
0183
0184 static void __init cpg_mstp_clocks_init(struct device_node *np)
0185 {
0186     struct mstp_clock_group *group;
0187     const char *idxname;
0188     struct clk **clks;
0189     unsigned int i;
0190
0191     group = kzalloc(struct_size(group, clks, MSTP_MAX_CLOCKS), GFP_KERNEL);
0192     if (!group)
0193         return;
0194
0195     clks = group->clks;
0196     spin_lock_init(&group->lock);
0197     group->data.clks = clks;
0198
0199     group->smstpcr = of_iomap(np, 0);
0200     group->mstpsr = of_iomap(np, 1);
0201
0202     if (group->smstpcr == NULL) {
0203         pr_err("%s: failed to remap SMSTPCR\n", __func__);
0204         kfree(group);
0205         return;
0206     }
0207
0208     if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))
0209         group->width_8bit = true;
0210
0211     for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
0212         clks[i] = ERR_PTR(-ENOENT);
0213
0214     if (of_find_property(np, "clock-indices", &i))
0215         idxname = "clock-indices";
0216     else
0217         idxname = "renesas,clock-indices";
0218
0219     for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
0220         const char *parent_name;
0221         const char *name;
0222         u32 clkidx;
0223         int ret;
0224
0225         /* Skip clocks with no name. */
0226         ret = of_property_read_string_index(np, "clock-output-names",
0227                             i, &name);
0228         if (ret < 0 || strlen(name) == 0)
0229             continue;
0230
0231         parent_name = of_clk_get_parent_name(np, i);
0232         ret = of_property_read_u32_index(np, idxname, i, &clkidx);
0233         if (parent_name == NULL || ret < 0)
0234             break;
0235
0236         if (clkidx >= MSTP_MAX_CLOCKS) {
0237             pr_err("%s: invalid clock %pOFn %s index %u\n",
0238                    __func__, np, name, clkidx);
0239             continue;
0240         }
0241
0242         clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
0243                                clkidx, group);
0244         if (!IS_ERR(clks[clkidx])) {
0245             group->data.clk_num = max(group->data.clk_num,
0246                           clkidx + 1);
0247             /*
0248              * Register a clkdev to let board code retrieve the
0249              * clock by name and register aliases for non-DT
0250              * devices.
0251              *
0252              * FIXME: Remove this when all devices that require a
0253              * clock will be instantiated from DT.
0254              */
0255             clk_register_clkdev(clks[clkidx], name, NULL);
0256         } else {
0257             pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
0258                    __func__, np, name, PTR_ERR(clks[clkidx]));
0259         }
0260     }
0261
0262     of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
0263 }
0264 CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
0265
0266 int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev)
0267 {
0268     struct device_node *np = dev->of_node;
0269     struct of_phandle_args clkspec;
0270     struct clk *clk;
0271     int i = 0;
0272     int error;
0273
0274     while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
0275                        &clkspec)) {
0276         if (of_device_is_compatible(clkspec.np,
0277                         "renesas,cpg-mstp-clocks"))
0278             goto found;
0279
0280         /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */
0281         if (of_node_name_eq(clkspec.np, "zb_clk"))
0282             goto found;
0283
0284         of_node_put(clkspec.np);
0285         i++;
0286     }
0287
0288     return 0;
0289
0290 found:
0291     clk = of_clk_get_from_provider(&clkspec);
0292     of_node_put(clkspec.np);
0293
0294     if (IS_ERR(clk))
0295         return PTR_ERR(clk);
0296
0297     error = pm_clk_create(dev);
0298     if (error)
0299         goto fail_put;
0300
0301     error = pm_clk_add_clk(dev, clk);
0302     if (error)
0303         goto fail_destroy;
0304
0305     return 0;
0306
0307 fail_destroy:
0308     pm_clk_destroy(dev);
0309 fail_put:
0310     clk_put(clk);
0311     return error;
0312 }
0313
0314 void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)
0315 {
0316     if (!pm_clk_no_clocks(dev))
0317         pm_clk_destroy(dev);
0318 }
0319
0320 void __init cpg_mstp_add_clk_domain(struct device_node *np)
0321 {
0322     struct generic_pm_domain *pd;
0323     u32 ncells;
0324
0325     if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
0326         pr_warn("%pOF lacks #power-domain-cells\n", np);
0327         return;
0328     }
0329
0330     pd = kzalloc(sizeof(*pd), GFP_KERNEL);
0331     if (!pd)
0332         return;
0333
0334     pd->name = np->name;
0335     pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
0336             GENPD_FLAG_ACTIVE_WAKEUP;
0337     pd->attach_dev = cpg_mstp_attach_dev;
0338     pd->detach_dev = cpg_mstp_detach_dev;
0339     pm_genpd_init(pd, &pm_domain_always_on_gov, false);
0340
0341     of_genpd_add_provider_simple(np, pd);
0342 }