clk/renesas/clk-emev2.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * EMMA Mobile EV2 common clock framework support
0004  *
0005  * Copyright (C) 2013 Takashi Yoshii <takashi.yoshii.ze@renesas.com>
0006  * Copyright (C) 2012 Magnus Damm
0007  */
0008 #include <linux/clk-provider.h>
0009 #include <linux/clkdev.h>
0010 #include <linux/io.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013
0014 /* EMEV2 SMU registers */
0015 #define USIAU0_RSTCTRL 0x094
0016 #define USIBU1_RSTCTRL 0x0ac
0017 #define USIBU2_RSTCTRL 0x0b0
0018 #define USIBU3_RSTCTRL 0x0b4
0019 #define IIC0_RSTCTRL 0x0dc
0020 #define IIC1_RSTCTRL 0x0e0
0021 #define STI_RSTCTRL 0x124
0022 #define STI_CLKSEL 0x688
0023
0024 static DEFINE_SPINLOCK(lock);
0025
0026 /* not pretty, but hey */
0027 static void __iomem *smu_base;
0028
0029 static void __init emev2_smu_write(unsigned long value, int offs)
0030 {
0031     BUG_ON(!smu_base || (offs >= PAGE_SIZE));
0032     writel_relaxed(value, smu_base + offs);
0033 }
0034
0035 static const struct of_device_id smu_id[] __initconst = {
0036     { .compatible = "renesas,emev2-smu", },
0037     {},
0038 };
0039
0040 static void __init emev2_smu_init(void)
0041 {
0042     struct device_node *np;
0043
0044     np = of_find_matching_node(NULL, smu_id);
0045     BUG_ON(!np);
0046     smu_base = of_iomap(np, 0);
0047     BUG_ON(!smu_base);
0048     of_node_put(np);
0049
0050     /* setup STI timer to run on 32.768 kHz and deassert reset */
0051     emev2_smu_write(0, STI_CLKSEL);
0052     emev2_smu_write(1, STI_RSTCTRL);
0053
0054     /* deassert reset for UART0->UART3 */
0055     emev2_smu_write(2, USIAU0_RSTCTRL);
0056     emev2_smu_write(2, USIBU1_RSTCTRL);
0057     emev2_smu_write(2, USIBU2_RSTCTRL);
0058     emev2_smu_write(2, USIBU3_RSTCTRL);
0059
0060     /* deassert reset for IIC0->IIC1 */
0061     emev2_smu_write(1, IIC0_RSTCTRL);
0062     emev2_smu_write(1, IIC1_RSTCTRL);
0063 }
0064
0065 static void __init emev2_smu_clkdiv_init(struct device_node *np)
0066 {
0067     u32 reg[2];
0068     struct clk *clk;
0069     const char *parent_name = of_clk_get_parent_name(np, 0);
0070     if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
0071         return;
0072     if (!smu_base)
0073         emev2_smu_init();
0074     clk = clk_register_divider(NULL, np->name, parent_name, 0,
0075                    smu_base + reg[0], reg[1], 8, 0, &lock);
0076     of_clk_add_provider(np, of_clk_src_simple_get, clk);
0077     clk_register_clkdev(clk, np->full_name, NULL);
0078     pr_debug("## %s %pOFn %p\n", __func__, np, clk);
0079 }
0080 CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv",
0081         emev2_smu_clkdiv_init);
0082
0083 static void __init emev2_smu_gclk_init(struct device_node *np)
0084 {
0085     u32 reg[2];
0086     struct clk *clk;
0087     const char *parent_name = of_clk_get_parent_name(np, 0);
0088     if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
0089         return;
0090     if (!smu_base)
0091         emev2_smu_init();
0092     clk = clk_register_gate(NULL, np->name, parent_name, 0,
0093                 smu_base + reg[0], reg[1], 0, &lock);
0094     of_clk_add_provider(np, of_clk_src_simple_get, clk);
0095     clk_register_clkdev(clk, np->full_name, NULL);
0096     pr_debug("## %s %pOFn %p\n", __func__, np, clk);
0097 }
0098 CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);